CN117792400A - High-precision Sigma Delta ADC adopting multi-bit SAR quantization - Google Patents

Abstract

The invention discloses a high-precision Sigma Delta ADC adopting multi-bit SAR quantization, which comprises the following steps: the loop filter is used for carrying out discrete integration processing on the analog input signal by utilizing a plurality of integrators; the 4Bit SAR quantizer is used for quantizing all the discrete integration results after the amplification factor processing to obtain a 4Bit digital code; the improved 4Bit DAC is used for carrying out first-order noise shaping and eliminating higher harmonics on the 4Bit digital code by utilizing the IDWA circuit, and then carrying out digital-to-analog conversion on the processed 4Bit digital code to obtain an analog output signal; the loop filter is also used for carrying out difference solving processing on the analog output signal and the analog input signal, taking a difference solving result as a new analog input signal in the loop filter, and carrying out discrete integration processing on the new analog input signal by utilizing a plurality of integrators. The invention can be applied to radar chips with high integration and high reliability.

Description

High-precision Sigma Delta ADC adopting multi-bit SAR quantization

Technical Field

The invention belongs to the technical field of laser radar optical signal front-end ADC systems, and particularly relates to a high-precision Sigma Delta ADC quantized by multi-bit SAR.

Background

With the development of integrated technology, various high-precision Analog-to-Digital Converter (ADC) are widely used, such as an Electrocardiogram (ECG) device system, an Electroencephalogram (EEG) device system, a laser radar chip, and various sensor chips, etc.

The laser radar generally comprises a transmitter, an optical system and a receiver system, wherein the receiver system receives a laser pulse signal reflected by an object, and a front-end photoelectric detector, such as an avalanche photodiode, converts the laser pulse signal into a current pulse signal, and then the receiver system converts and amplifies the current pulse signal into a voltage signal. In the design and research of a laser radar chip with high integration and high reliability, the signal to be detected has the characteristics of narrow frequency band and wide range to be detected. An analog-to-digital converter (a/D) converting an analog signal into a digital signal has a high dynamic range, low distortion characteristic to ensure the quality of signal processing. Sigma-Delta ADC based on over-sampling and noise shaping techniques is more suitable for the above application, and Sigma-Delta ADC is divided into two types: continuous time Sigma-Delta ADC and discrete time Sigma-Delta ADC, continuous time Sigma-Delta ADC is realized with continuous time loop filter, discrete time Sigma-Delta ADC is realized with switch capacitor circuit, and the switch capacitor circuit has better matching and low sensitivity to clock jitter of feedback digital-to-analog converter, so that the application of discrete time Sigma-Delta ADC is wider. For example, the Sigma-Delta ADC with the discrete time feedforward (Cascade ofIntegrators with Feed Forward, abbreviated as CIFF) structure adopted at present has the advantages that the gain of the first-stage integrator is only required to be very large because a very small error signal passes through the loop filter, so that in-band noise can be well restrained, and the later-stage integrator does not process a feedback signal with high-frequency noise, so that the requirement of the later-stage operational amplifier is not high, and the low-power consumption design is realized.

However, the discrete-time Sigma-Delta ADC described above requires an active adder in front of the quantizer, which requires a higher level of operational amplification at the last stage, and increases power consumption and system delay.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a high-precision Sigma Delta ADC employing multi-bit SAR quantization. The technical problems to be solved by the invention are realized by the following technical scheme:

the embodiment of the invention provides a high-precision Sigma Delta ADC adopting multi-bit SAR quantization, which comprises the following steps: loop filter, 4Bit SAR quantizer, improved 4Bit DAC; wherein,

the loop filter is used for performing discrete integration processing on the analog input signal by using a plurality of integrators; in the processing process, the discrete integration result of each integrator is divided into two parts, one part is input into the next integrator after being processed by a reduction coefficient, and the other part is input into the 4Bit SAR quantizer after being processed by an amplification coefficient;

the 4Bit SAR quantizer is connected with the loop filter and is used for performing quantization processing on all discrete integration results processed by the amplification coefficient to obtain a 4Bit digital code;

the improved 4Bit DAC is connected with the 4Bit SAR quantizer; the improved 4Bit DAC comprises an IDWA circuit; the improved 4Bit DAC is used for performing first-order noise shaping and eliminating higher harmonics on the 4Bit digital code by using the IDWA circuit, and performing digital-to-analog conversion processing on the 4Bit digital code processed by the IDWA circuit to obtain an analog output signal;

the loop filter is connected with the improved 4Bit DAC and is also used for carrying out difference solving processing on the analog output signal after the coefficient reduction processing and the analog input signal after the coefficient reduction processing, taking a difference solving result as a new analog input signal in the loop filter, and carrying out discrete integration processing on the new analog input signal by utilizing a plurality of integrators.

In one embodiment of the invention, the loop filter comprises three integrators and an analog subtractor; wherein,

the input end of the analog subtracter is connected with the input end of the analog input signal and the improved 4Bit DAC, the output end of the analog subtracter is connected with the input end of a first integrator, the output end of the first integrator is connected with the input end of a second integrator and the 4Bit SAR quantizer, the output end of the second integrator is connected with the input end of a third integrator and the 4Bit SAR quantizer, and the output end of the third integrator is connected with the 4Bit SAR quantizer.

In one embodiment of the present invention, the 4Bit SAR quantizer comprises a first switching leg, a second switching leg, a comparator, and SAR logic circuitry; wherein,

the first switch branch circuit and the second switch branch circuit are connected with the input end of the comparator, the output end of the comparator is connected with the signal input end of the SAR logic circuit, the time sequence output end of the SAR logic circuit is connected with the first switch branch circuit and the second switch branch circuit, and the signal output end of the SAR logic circuit is connected with the improved 4Bit DAC.

In one embodiment of the present invention, the first switching leg and the second switching leg have the same circuit structure; the first switch branch comprises a switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first selection switch, a second selection switch, a third selection switch and a fourth selection switch; wherein,

one end of the switch, one end of the first capacitor, one end of the second capacitor, one end of the third capacitor and one end of the fourth capacitor are all connected with the input end of the comparator, the other end of the switch is connected with the common-mode voltage input end, the other end of the first capacitor is connected with one end of the first selection switch, the other end of the second capacitor is connected with one end of the second selection switch, the other end of the third capacitor is connected with one end of the third selection switch, the other end of the fourth capacitor is connected with the fourth selection switch, the other end of the first selection switch is connected with the input end of the common-mode voltage or the other end of the switch, the other end of the second selection switch is connected with the input end of the reference voltage or the output end of the first integrator, the other end of the third selection switch is connected with the input end of the reference voltage or the output end of the third integrator, and the other end of the fourth selection switch is connected with the input end of the reference voltage or the output end of the second integrator.

In one embodiment of the present invention, the capacitance value ratio of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor is 1:1:2:4.

In one embodiment of the present invention, the timing output terminal of the SAR logic circuit provides a switching clock signal, the other end of the first selection switch is controlled to be connected to the input terminal of the common mode voltage or the other end of the switch according to the switching clock signal, the other end of the second selection switch is connected to the input terminal of the reference voltage or the output terminal of the first integrator, the other end of the third selection switch is connected to the input terminal of the reference voltage or the output terminal of the third integrator, and the other end of the fourth selection switch is connected to the input terminal of the reference voltage or the output terminal of the second integrator.

In one embodiment of the present invention, the IDWA circuit is implemented by an IDWA algorithm; the IDWA algorithm is based on the DWA algorithm, and is added with a device.

In one embodiment of the present invention, the IDWA algorithm implementation process includes:

the number of the initialized unit component is S ₁ ～S ₈ The method comprises the steps of carrying out a first treatment on the surface of the Each moment corresponds to a unit component, and the unit component comprises 8 components to be selected;

the IDWA circuit receives the 4Bit digital code, converts the 4Bit digital code into a thermometer code, the number of 1's in the thermometer code represents the number of devices selected from unit components at the current moment, selects a corresponding number of devices from the unit components at the current moment, and takes the next device of the last device selected as the starting position of the device selected at the next moment;

and returning to the step of receiving the 4Bit digital codes by the IDWA circuit until the 4Bit digital codes received by the IDWA circuit at all moments are processed.

In one embodiment of the present invention, the value of the reduction coefficient is less than 1; the amplification factor is greater than or equal to 1.

The invention has the beneficial effects that:

the high-precision Sigma Delta ADC adopting multi-Bit SAR quantization provided by the invention can realize the Sigma Delta ADC with high precision based on the 4Bit SAR quantizer and the IDWA technology, and the specific Sigma Delta ADC comprises: loop filter, 4Bit SAR quantizer, improved 4Bit DAC; the loop filter is used for performing discrete integration processing on the analog input signal by using a plurality of integrators; in the processing process, the discrete integration result of each integrator is divided into two parts, one part is input into the next integrator after being processed by a reduction coefficient, and the other part is input into the 4Bit SAR quantizer after being processed by an amplification coefficient; the 4Bit SAR quantizer is connected with the loop filter and is used for performing quantization processing on all discrete integration results processed by the amplification coefficient to obtain a 4Bit digital code; the improved 4Bit DAC is connected with the 4Bit SAR quantizer; the improved 4Bit DAC comprises an IDWA circuit; the improved 4Bit DAC is used for carrying out first-order noise shaping and eliminating higher harmonics on the 4Bit digital code by using the IDWA circuit, and then carrying out digital-to-analog conversion processing on the 4Bit digital code processed by the IDWA circuit to obtain an analog output signal; the loop filter is connected with the improved 4Bit DAC and is also used for carrying out difference solving processing on the analog output signal after the coefficient reduction processing and the analog input signal after the coefficient reduction processing, taking a difference solving result as a new analog input signal in the loop filter, and carrying out discrete integration processing on the new analog input signal by utilizing a plurality of integrators. Compared with the traditional passive adder, the active SAR quantizer structure is adopted, and can reduce the power consumption and layout design area of the Sigma Delta ADC and delay of the Sigma Delta ADC; meanwhile, aiming at the problem that DAC (digital-to-analog converter) linear mismatch caused by a multi-bit quantizer cannot be shaped by a loop filter, the invention designs an IDWA (integrated circuit capable of solving the problem of DAC linear mismatch caused by the multi-bit quantizer and effectively improving SNDR of an analog output signal; the invention realizes the high-precision Sigma Delta ADC at the front end of the laser radar chip, and can be applied to the radar chip with high integration level and high reliability.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a schematic diagram of a high-precision Sigma Delta ADC employing multi-bit SAR quantization according to an embodiment of the present invention;

FIG. 2 is an exemplary schematic diagram of a high-precision Sigma Delta ADC employing multi-bit SAR quantization provided by an embodiment of the present invention;

FIGS. 3 (a) -3 (b) are schematic diagrams of detailed circuit structures of conventional 4Bit SAR quantizer;

FIG. 4 is a schematic diagram of a 4Bit SAR quantizer according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a detailed circuit structure of a 4Bit SAR quantizer according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of selection situations of corresponding unit components when a DWA circuit and an IDWA circuit are adopted in the embodiment of the invention;

FIG. 7 is a schematic diagram of an output spectrum diagram of a DWA circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of an output spectrum diagram of an IDWA circuit according to an embodiment of the present invention;

fig. 9 is a schematic diagram of an analog output signal spectrum diagram of an improved 4Bit DAC output according to an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Referring to fig. 1, an embodiment of the present invention provides a high-precision Sigma Delta ADC employing multi-bit SAR quantization, comprising: loop filter, 4Bit SAR quantizer, improved 4Bit DAC; wherein,

a loop filter for performing discrete integration processing on the analog input signal using a plurality of integrators; in the processing process, the discrete integration result of each integrator is divided into two parts, one part is input into the next integrator after being processed by a reduction coefficient, and the other part is input into the 4Bit SAR quantizer after being processed by an amplification coefficient;

the 4Bit SAR quantizer is connected with the loop filter and is used for performing quantization processing on all discrete integration results processed by the amplification coefficient to obtain a 4Bit digital code;

the improved 4Bit DAC is connected with the 4Bit SAR quantizer; the improved 4Bit DAC comprises an IDWA circuit; the improved 4Bit DAC is used for carrying out first-order noise shaping and eliminating higher harmonics on the 4Bit digital code by using the IDWA circuit, and then carrying out digital-to-analog conversion processing on the 4Bit digital code processed by the IDWA circuit to obtain an analog output signal;

the loop filter is connected with the improved 4Bit DAC and is also used for carrying out difference solving processing on the analog output signal after the coefficient reduction processing and the analog input signal after the coefficient reduction processing, taking a difference solving result as a new analog input signal in the loop filter, and carrying out discrete integration processing on the new analog input signal by utilizing a plurality of integrators.

Next, each section will be described in detail.

The loop filter in the embodiment of the invention comprises three integrators and an analog subtracter; the input end of the analog subtracter is connected with the input end of the analog input signal and the improved 4Bit DAC, the output end of the analog subtracter is connected with the input end of the first integrator, the output end of the first integrator is connected with the input end of the second integrator and the 4Bit SAR quantizer, the output end of the second integrator is connected with the input end of the third integrator and the 4Bit SAR quantizer, and the output end of the third integrator is connected with the 4Bit SAR quantizer. Wherein the three integrators can be implemented in a discrete structure of the existing structure.

As can be seen from fig. 1, at the input of the analog input signal UP, an analog subtractor (fig. 1'"shown"), between the modified 4Bit DAC and the analog subtractor, between the first integrator Q1 and the second integrator Q2, the second productThe divider Q2 and the third integrator Q3 are subjected to a reduction coefficient processing, that is, the reduction coefficient has a value smaller than 1, that is, the values of C1, C2, C3, and C4 are all smaller than 1, as in an example in the process shown in fig. 2, c1=c3=c4=0.8, and c2=0.7; the first integrator Q1 and the 4Bit SAR quantizer, the second integrator Q2 and the 4Bit SAR quantizer, and the third integrator Q3 and the 4Bit SAR quantizer are subjected to amplification factor processing, that is, the amplification factor is greater than or equal to 1, that is, the values of A1, A2, and A3 are all greater than or equal to 1, as shown in an example a1=2, a2=a3=1 in a process; the specific C1, C2, C3, C4, A1, A2 and A3 can be adjusted in real time according to actual conditions.

As can be seen from fig. 2, the analog input signal UP is subjected to discrete integration processing by the first integrator Q1 to generate a discrete integration result X1, the discrete integration result X12 is generated by the X1 subjected to reduction coefficient processing and is input into the second integrator Q2, the discrete integration result X11 is generated by the X1 subjected to amplification coefficient processing and is input into the 4Bit SAR quantizer; similarly, the second integrator Q2 performs discrete integration processing to generate X2, the X22 subjected to the reduced coefficient processing is input into the third integrator Q3, the X21 subjected to the amplified coefficient processing is input into the 4Bit SAR quantizer, the third integrator Q3 performs discrete integration processing to generate X3, and the X31 subjected to the amplified coefficient processing is input into the 4Bit SAR quantizer.

Further, the conventional N Bit FLASH quantizer comprises 2 ^N -1 unit component, the working principle of which is as follows: the binary code of the FLASH quantizer is first converted into a thermometer code, and then the sum of the outputs of the elements corresponding to the thermometer code "1" is selected as the analog output signal of the DAC. Table 1 shows the manner in which a conventional DAC uses thermometer code selection elements, taking a 3Bit DAC as an example, assuming a reference level of + -VREF, when the analog input signal UP is greater thanLess than->When the output binary code is 100, the binary code is converted into thermometer code bits 0001111, which indicates that the first 4 unit components are usedFor N-bit binary codes, the thermometer code 2 is converted ^N -1 bit. Assuming that each unit component of the DAC has mismatch, the mismatch value of the ith unit component is epsilon _i (i＝1～2 ^N -1) and each mismatch value is different, it can be seen from table 1 that for the unit components corresponding to the thermometer code "1" code, the mismatch value HUI is always accumulated and not eliminated. However, the number of comparators in the traditional multi-bit FLASH quantizer is too large, so that the power consumption brought by the FLASH quantizer is too high, the occupation of layout area is too large, and the selection is not optimal.

Table 1 manner in which a conventional DAC selects elements using thermometer codes

Through the above analysis, the embodiment of the present invention selects a 4Bit SAR quantizer, and compared with a single Bit SAR quantizer, the multi Bit SAR quantizer has many advantages compared with the single Bit SAR quantizer, and according to the Signal-to-Noise-Ratio (SNR) formula:

wherein N represents the Bit number of the SAR quantizer; l represents the quantizer order and OSR represents the Sigma delta ADC oversampling rate. The formula can be known: the SAR quantizer increases the SNR by 6.02dB every Bit, and the roll-off requirement of the extraction filter for suppressing out-of-band noise is further relaxed. Meanwhile, compared with a single Bit SAR quantizer, the multi Bit SAR quantizer has no change in signal amplitude due to the increase of quantization orders, so that the quantization interval of each step is reduced, and the Sigma delta ADC is more linear and stable; meanwhile, the requirement on the front integrator is reduced, so that the slew rate of the front integrator is greatly reduced, and the maximum stable amplitude (Maximum Stabilized Amplitude, MSA for short) of the analog input signal is large.

As shown in fig. 3 (a) to 3 (b), a conventional 4Bit SAR quantizer can be seen: in the conventional 4Bit SAR quantizer, the switch logic timing needs to be pre-set in advance, that is, the maximum capacitor 8C at the positive end of the comparator is connected to VREFP, the maximum capacitor 8C at the negative end of the comparator is connected to VREFN, and the process is reset according to the comparison result, which consumes a lot of energy. The invention provides a novel 4Bit SAR quantizer aiming at a traditional 4Bit SAR quantizer, as shown in fig. 4, wherein the 4Bit SAR quantizer comprises a first switch branch, a second switch branch, a comparator and an SAR logic circuit; the first switch branch and the second switch branch are connected with the input end of the comparator, the output end of the comparator is connected with the signal input end of the SAR logic circuit, the time sequence output end of the SAR logic circuit is connected with the first switch branch and the second switch branch, and the signal output end of the SAR logic circuit is connected with the improved 4Bit DAC. The detailed circuit of the 4Bit SAR quantizer provided by the embodiment of the invention is shown in fig. 5, and it can be seen that the circuit structures of the first switch branch and the second switch branch are the same. Taking circuit connection of a first switch branch as an example, the first switch branch comprises a switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first selection switch, a second selection switch, a third selection switch and a fourth selection switch; one end of the switch, one end of the first capacitor, one end of the second capacitor, one end of the third capacitor and one end of the fourth capacitor are all connected with the input end of the comparator, the other end of the switch is connected with the common-mode voltage input end, the other end of the first capacitor is connected with one end of the first selection switch, the other end of the second capacitor is connected with one end of the second selection switch, the other end of the third capacitor is connected with the fourth selection switch, the other end of the first selection switch is connected with the input end of the common-mode voltage or the other end of the switch, the other end of the second selection switch is connected with the input end of the reference voltage or the output end of the first integrator, the other end of the third selection switch is connected with the input end of the reference voltage or the output end of the third integrator, and the other end of the fourth selection switch is connected with the input end of the reference voltage or the output end of the second integrator. Preferably, the capacitance value ratio of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor is 1:1:2:4.

In the practice of the inventionIn an example, the timing output end of the SAR logic circuit provides a switch clock signal, the other end of the first selection switch is controlled to be connected with the input end of the common mode voltage or the other end of the switch according to the switch clock signal, the other end of the second selection switch is connected with the input end of the reference voltage or the output end of the first integrator, the other end of the third selection switch is connected with the input end of the reference voltage or the output end of the third integrator, and the other end of the fourth selection switch is connected with the input end of the reference voltage or the output end of the second integrator, such as the clock phi generated by the SAR logic circuit ₁ And phi is ₂ To control the selection, the opening and closing of the switch being controlled by a clock phi generated by the SAR logic circuit _2d To control. At the same time, the SAR logic circuit generates a clock phi _X For controlling the comparator; clock Φ generated by SAR logic _1d For timing control of loop filters.

Correspondingly, the working principle of the 4Bit SAR quantizer provided by the embodiment of the invention is as follows:

the discrete integration results X11, X21 and X31 output by the loop filter are simultaneously transmitted to a 4Bit SAR quantizer for quantization, and two phases of the discrete integration results are not overlapped with clock phi ₂ And phi is ₁ Phi is as follows ₂ Delayed off clock Φ of (2) _2d Control, first clock Φ ₂ On, sampling the input signals X11, X21 and X31, the sampling capacitances 8C, 4C and (2C+1C+1C) are found, the ratio of which is 2:1:1, the corresponding X11, X21 and X31 are passed to the quantizer front-end by a factor of 2, 1 and 1. Then clock phi _2d Turn off so that the comparator is at a common mode voltage VCM, after which the switching process is equivalent to VCM-based capacitive switching timing as shown in the lower right of fig. 5, the charge at the positive input of the comparator can be expressed as: vy=2vcm—vin, VIN represents the sum of voltages of the first switching branch corresponding to the input signals X11, X21 and X31, and similarly the charge at the negative input terminal is vx=2vcm—vip, VIP represents the sum of voltages of the second switching branch corresponding to the input signals X11, X21 and X31, vx and Vy are directly compared, compared with the conventional SAR lower plate sampling, the capacitor lower plate of the embodiment of the present invention is connected to the input signals, upperThe stage board is connected to the common mode voltage VCM. And VCM-based timing is shown as 5, the lower plates of all capacitors are connected to VCM first, and the upper plates sample the input signal. After sampling is finished, the sampling switch is disconnected, the comparator directly performs first comparison, if Vy is larger than Vx, the output high-order code is 1, meanwhile, the maximum capacitor 8C connected with Vy is grounded, the maximum capacitor 8C connected with Vx is connected with VREF, otherwise, the output high-order code is 0, meanwhile, the maximum capacitor 8C connected with Vx is grounded, the maximum capacitor 8C connected with Vy is connected with VREF, and then next comparison is performed, so that a high-order-1 digital code is obtained. Each time sampling is completed, phi _X Conducting for 4 times to finish 4Bit quantization and obtain 4Bit digital codes. Compared with the traditional 4Bit SAR quantization time sequence, the 4Bit SAR quantizer as shown in fig. 5 does not need to prefabricate bits, so that the power consumption is smaller.

The embodiment of the invention adopts a 4Bit SAR quantizer, and does not adopt a traditional multi-Bit FLASH quantizer any more, and compared with the traditional 4Bit FLASH quantizer, the embodiment of the invention needs 2 ⁴ 1 comparator, while a 4Bit SAR quantizer requires only one comparator, can greatly reduce power consumption, and adopts a multi-Bit SAR quantization structure instead of a passive adder, can reduce the complexity of the design of the Sigma-Delta ADC and reduce the delay of the Sigma-Delta ADC.

Compared with the traditional multi-bit FLASH quantizer, the number of comparators is only one, so that consumed power consumption is greatly reduced, and complexity of layout design is also reduced.

Further, compared to a single Bit SAR quantizer, its feedback DAC only feeds back the two voltage signals 0 and 1 to the loop filter, so there is no non-linearity problem. For the multi-bit SAR quantizer, the DAC needs to feed back the multi-level Signal to the loop filter, and because of the mismatch between the multi-bit SAR quantizer and the capacitor or resistor, the output voltage of the DAC is difficult to maintain a linear relationship, and the Signal output by the DAC is directly fed back to the input of the first-stage integrator of the loop filter and is not shaped by the loop filter, so that serious nonlinear Distortion is caused, and the Signal-to-Noise-and-Distortion Ratio (SNDR) of the output Signal is reduced.

Based on the problems, the invention is toEmbodiments propose to use a data weighted average algorithm (Data Weighted Averaging, DWA for short) in a dynamic element matching (Dynamic Element Matching, DEM for short) technique to reduce the offset caused by multi-bit quantization, and implement a DWA circuit with the DWA algorithm. As shown in fig. 6, the unit component numbers of the 4Bit DAC are denoted by S in turn ₁ ～S ₇ The period represents the time when the 4Bit digital code is input into the DWA circuit, the input represents the number of '1' in the thermometer code, namely, the 4Bit digital code corresponds to the number of '1' in the thermometer code, the initial pointer represents the first device pointing to each unit component in the DAC, and the end pointer represents the last device pointing to each unit component selected in the DAC. And after the unit components in the current period are selected, the unit components in the next period take the next component of the last component in the unit components in the current period as the starting position of component selection. Such as in fig. 6: when the thermometer code corresponding to the input 4Bit digital code in the period 1 is 0001111, 0001111, the number 1 represents that 4 devices in the unit components corresponding to the period 1 are used, namely the first 4 square cells corresponding to the first row of the DWA in fig. 6 are filled with blue to indicate that the devices are used, the square cells are filled with white to indicate that the devices are not used, and the last device in the period 1 is S ₄ Then device S is set in cycle 2 ₄ Is the next device S ₅ The device selected in period 1 is S as the starting position of device selection ₁ ～S ₄ The method comprises the steps of carrying out a first treatment on the surface of the When the thermometer code corresponding to the period 2 input 4Bit digital code is 0011111, 0011111, the number 1 represents 5 devices in the unit components corresponding to the period 2 to be used, and the initial position selected by the period 2 device is S in the unit components corresponding to the period 1 ₅ And period 1 corresponds to S in the unit component ₅ ～S ₇ Although not selected, it still belongs to the unit component corresponding to period 1, from the first row S of period 1 ₅ Initially, S is selected from the second row ₅ ～S ₇ And then select S from the second row ₁ ～S ₂ Then the last device in period 2 is S ₂ Device S is set in cycle 3 ₂ Is the next device S ₃ The device selected in period 2 is S as the starting position of device selection ₁ ～S ₂ And S ₅ ～S ₇ The method comprises the steps of carrying out a first treatment on the surface of the And so on, each device can be selected, and the probability of using the devices in each unit component is guaranteed to be the same. The arrow in fig. 6 indicates the start position of the first device in the next cycle, i.e., the initial pointer.

The inventor researches that if a device is added on the basis of a DWA algorithm, the noise can be better transferred to the out-of-band, the noise introduced by the 4Bit DAC can be better shaped in a first order, harmonic waves caused by nonlinearity can be eliminated, and higher SDNR is realized. Ideally both DWA and IDWA are capable of first order DAC noise shaping, but the IDWA algorithm is more capable of removing noise within the signal bandwidth and can produce a higher SNDR than the DWA algorithm. It can be seen that the embodiment of the invention provides an IDWA circuit, which is realized by an IDWA algorithm; the IDWA algorithm is based on the DWA algorithm, and is added with a device. Specifically:

the implementation process of the IDWA algorithm in the embodiment of the invention comprises the following steps: initializing the serial numbers of the unit components; each moment corresponds to a unit component, and the unit component comprises 8 components to be selected; the IDWA circuit receives the 4Bit digital code, converts the 4Bit digital code into a thermometer code, the number of 1's in the thermometer code represents the number of selected devices in the unit components at the current moment, selects the devices with the corresponding number from the unit components at the current moment, and takes the next device of the last device selected as the starting position of the selected device at the next moment; returning to the step of the IDWA circuit receiving the 4Bit digital code until the processing of the 4Bit digital code received by the IDWA circuit at all moments is completed. The number of the initializing unit component is S as in the IDWA of FIG. 6 ₁ ～S ₈ Each period of device selection is referred to above in the DWA algorithm, except that the IDWA algorithm adds a device S ₈ The thermometer code is 8 digits, and the whole selection process is the same as the DWA algorithm, and is not repeated here.

As shown in fig. 7 and 8, fig. 7 shows a schematic diagram of an output spectrum based on a DWA circuit, fig. 8 shows a schematic diagram of an output spectrum based on an IDWA circuit, and the horizontal and vertical marks of fig. 7 and 8 represent signal frequencies in Hz, and the vertical marks represent signal amplitudes after fourier transformation in dB, as can be seen: compared to DWA circuits, IDWA circuits increase SNDR by 11dB, and their significant bit number (Effective Number of Bits, ENOB for short) by two bits.

The embodiment of the invention designs and completes all circuits, adopts a Smic 0.18 mu m CMOS process flow sheet, wherein the working voltage is 3.3V, the input reference level VREF is +/-1.5V, the frequency of an analog input signal UP is 9.5KHz, the obtained signal-to-noise ratio SNR and signal-to-noise distortion SNDR ratio are respectively 94.7dB and 94.7dB, the effective bit ENOB is 15.44bit, the power consumption is only 1mV, the area is about 1mm multiplied by 1mm, the requirements of a Sigma Delta ADC at the front end of a laser radar chip are met, the obtained signal spectrum is shown in figure 9, the abscissa in figure 9 represents the signal frequency in Hz, the ordinate represents the full swing normalized amplitude in dB.

In summary, the high-precision Sigma Delta ADC using multi-Bit SAR quantization according to the embodiment of the present invention may implement a Sigma Delta ADC having high precision based on a 4Bit SAR quantizer and an IDWA technique, and the specific Sigma Delta ADC includes: loop filter, 4Bit SAR quantizer, improved 4Bit DAC; the loop filter is used for performing discrete integration processing on the analog input signal by using a plurality of integrators; in the processing process, the discrete integration result of each integrator is divided into two parts, one part is input into the next integrator after being processed by a reduction coefficient, and the other part is input into the 4Bit SAR quantizer after being processed by an amplification coefficient; the 4Bit SAR quantizer is connected with the loop filter and is used for performing quantization processing on all discrete integration results processed by the amplification coefficient to obtain a 4Bit digital code; the improved 4Bit DAC is connected with the 4Bit SAR quantizer; the improved 4Bit DAC comprises an IDWA circuit; the improved 4Bit DAC is used for carrying out first-order noise shaping and eliminating higher harmonics on the 4Bit digital code by using the IDWA circuit, and then carrying out digital-to-analog conversion processing on the 4Bit digital code processed by the IDWA circuit to obtain an analog output signal; the loop filter is connected with the improved 4Bit DAC and is also used for carrying out difference solving processing on the analog output signal after the coefficient reduction processing and the analog input signal after the coefficient reduction processing, taking a difference solving result as a new analog input signal in the loop filter, and carrying out discrete integration processing on the new analog input signal by utilizing a plurality of integrators. Compared with a traditional passive adder, the embodiment of the invention adopts an active SAR quantizer structure, which can reduce the power consumption and layout design area of the Sigma Delta ADC and reduce the delay of the Sigma-Delta ADC; meanwhile, aiming at the problem that DAC (digital-to-analog converter) linear mismatch caused by a multi-bit quantizer cannot be shaped by a loop filter, the embodiment of the invention designs an IDWA (integrated circuit, which solves the problem of DAC linear mismatch caused by the multi-bit quantizer and effectively improves SNDR of an analog output signal; the embodiment of the invention realizes the high-precision Sigma Delta ADC at the front end of the laser radar chip, and can be applied to the radar chip with high integration level and high reliability.

In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the specification and the drawings. In the description, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (9)

1. The high-precision Sigma Delta ADC adopting multi-Bit SAR quantization is characterized by comprising a loop filter, a 4Bit SAR quantizer and an improved 4Bit DAC; wherein,

the loop filter is used for performing discrete integration processing on the analog input signal by using a plurality of integrators; in the processing process, the discrete integration result of each integrator is divided into two parts, one part is input into the next integrator after being processed by a reduction coefficient, and the other part is input into the 4Bit SAR quantizer after being processed by an amplification coefficient;

the 4Bit SAR quantizer is connected with the loop filter and is used for performing quantization processing on all discrete integration results processed by the amplification coefficient to obtain a 4Bit digital code;

the improved 4Bit DAC is connected with the 4Bit SAR quantizer; the improved 4Bit DAC comprises an IDWA circuit; the improved 4Bit DAC is used for performing first-order noise shaping and eliminating higher harmonics on the 4Bit digital code by using the IDWA circuit, and performing digital-to-analog conversion processing on the 4Bit digital code processed by the IDWA circuit to obtain an analog output signal;

the loop filter is connected with the improved 4Bit DAC and is also used for carrying out difference solving processing on the analog output signal after the coefficient reduction processing and the analog input signal after the coefficient reduction processing, taking a difference solving result as a new analog input signal in the loop filter, and carrying out discrete integration processing on the new analog input signal by utilizing a plurality of integrators.

2. The high precision Sigma Delta ADC employing multi-bit SAR quantization of claim 1, wherein said loop filter comprises three integrators and an analog subtractor; wherein,

the input end of the analog subtracter is connected with the input end of the analog input signal and the improved 4Bit DAC, the output end of the analog subtracter is connected with the input end of a first integrator, the output end of the first integrator is connected with the input end of a second integrator and the 4Bit SAR quantizer, the output end of the second integrator is connected with the input end of a third integrator and the 4Bit SAR quantizer, and the output end of the third integrator is connected with the 4Bit SAR quantizer.

3. The high precision Sigma Delta ADC employing multi-Bit SAR quantization of claim 1, wherein said 4Bit SAR quantizer comprises a first switching leg, a second switching leg, a comparator, and SAR logic circuitry; wherein,

the first switch branch circuit and the second switch branch circuit are connected with the input end of the comparator, the output end of the comparator is connected with the signal input end of the SAR logic circuit, the time sequence output end of the SAR logic circuit is connected with the first switch branch circuit and the second switch branch circuit, and the signal output end of the SAR logic circuit is connected with the improved 4Bit DAC.

4. A high precision Sigma Delta ADC employing multi-bit SAR quantization according to claim 3, wherein the circuit structures of the first switching leg and the second switching leg are identical; the first switch branch comprises a switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first selection switch, a second selection switch, a third selection switch and a fourth selection switch; wherein,

one end of the switch, one end of the first capacitor, one end of the second capacitor, one end of the third capacitor and one end of the fourth capacitor are all connected with the input end of the comparator, the other end of the switch is connected with the common-mode voltage input end, the other end of the first capacitor is connected with one end of the first selection switch, the other end of the second capacitor is connected with one end of the second selection switch, the other end of the third capacitor is connected with one end of the third selection switch, the other end of the fourth capacitor is connected with the fourth selection switch, the other end of the first selection switch is connected with the input end of the common-mode voltage or the other end of the switch, the other end of the second selection switch is connected with the input end of the reference voltage or the output end of the first integrator, the other end of the third selection switch is connected with the input end of the reference voltage or the output end of the third integrator, and the other end of the fourth selection switch is connected with the input end of the reference voltage or the output end of the second integrator.

5. The high precision Sigma Delta ADC of claim 4, wherein a capacitance value ratio of said first capacitance, said second capacitance, said third capacitance, said fourth capacitance is 1:1:2:4.

6. The high precision Sigma Delta ADC of claim 4, wherein said SAR logic circuit provides a switching clock signal at a timing output, said switching clock signal controls said first selector switch to have its other end connected to said common mode voltage input or said switch other end, said second selector switch to have its other end connected to said reference voltage input or said first integrator output, said third selector switch to have its other end connected to said reference voltage input or said third integrator output, and said fourth selector switch to have its other end connected to said reference voltage input or said second integrator output.

7. The high precision Sigma Delta ADC employing multi-bit SAR quantization of claim 1, wherein said IDWA circuit is implemented by an IDWA algorithm; the IDWA algorithm is based on the DWA algorithm, and is added with a device.

8. The high precision Sigma Delta ADC employing multi-bit SAR quantization of claim 7, wherein said IDWA algorithm implementation comprises:

the number of the initialized unit component is S ₁ ～S ₈ The method comprises the steps of carrying out a first treatment on the surface of the Each time corresponds to a unit component, and the unit component comprises 8 to-be-selected devicesA piece;

the IDWA circuit receives the 4Bit digital code, converts the 4Bit digital code into a thermometer code, the number of 1's in the thermometer code represents the number of devices selected from unit components at the current moment, selects a corresponding number of devices from the unit components at the current moment, and takes the next device of the last device selected as the starting position of the device selected at the next moment;

and returning to the step of receiving the 4Bit digital codes by the IDWA circuit until the 4Bit digital codes received by the IDWA circuit at all moments are processed.

9. The high precision Sigma Delta ADC employing multi-bit SAR quantization of claim 1, wherein said scaling factor has a value of less than 1; the amplification factor is greater than or equal to 1.