CN117792394A - Cyclic analog-to-digital converter and method thereof - Google Patents

Abstract

The application discloses a cyclic analog-to-digital converter and a method thereof. The cyclic analog-to-digital converter comprises a cyclic processing unit, wherein the cyclic processing unit comprises a first conversion unit and a second conversion unit which are cascaded, and the first conversion unit and the second conversion unit generate multi-bit intermediate data in a plurality of cycles of a conversion period; a register for storing at least multi-bit intermediate data generated in the last cycle among the plurality of cycles; and a logic unit for performing a dislocation process on the multi-bit intermediate data to generate multi-bit output data corresponding to the analog input signal bit by bit, wherein the first conversion unit and the second conversion unit interleave a sampling stage and an amplifying stage in each of the plurality of cycles. The cyclic analog-to-digital converter can implement multi-bit cyclic conversion to increase conversion rate.

Description

Cyclic analog-to-digital converter and method thereof

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a cyclic analog-to-digital converter and a method thereof.

Background

An analog-to-digital converter (ADC) is a device for converting an analog signal into a digital signal. Analog signals are continuous and may be represented as physical quantities of sound, image, temperature, etc., while digital signals are discrete and may be processed by digital devices such as computers. Analog-to-digital converters are widely used in electronic products, for example, for digitizing analog signals such as sensor signals, audio signals, image signals, etc.

The analog-to-digital converter works by converting an analog signal into a digital signal through three steps of sampling, quantization and encoding. Sampling is the conversion of a continuous analog signal into a discrete signal, quantization is the conversion of each sample value into a finite number, and encoding is the conversion of each quantized value into a binary code.

Pipelined analog-to-digital converters (Pipeline ADCs) and Cyclic analog-to-digital converters (Cyclic ADCs) are two common analog-to-digital converter architectures. The pipelined analog-to-digital converter consists of a plurality of cascaded sub-modules, each sub-module is responsible for processing a part of an input signal, and the input signal is sequentially subjected to analog-to-digital conversion and digital filtering processing in each sub-module to finally obtain an output result. The cyclic analog-to-digital converter comprises a single-stage sub-analog-to-digital converter and a sub-digital-to-analog converter. In each clock cycle, the sub-digital converter compares the input signal with a reference voltage corresponding to the bit weight to obtain a digital value of the corresponding bit weight, and in a plurality of clock cycles, the single-stage sub-digital converter and the sub-digital-analog converter are cyclically utilized to quantize the input signal, gradually approach the analog value of the input signal, and finally digital output is obtained. The advantages of the cyclic analog-to-digital converter are low power consumption and low complexity compared to the pipelined analog-to-digital converter.

The existing cyclic analog-to-digital converter basically adopts a single-stage conversion unit, and the cyclic processing of single bits causes long conversion period and low conversion rate, so that the cyclic analog-to-digital converter cannot be applied to an application scene of high-speed sampling.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a novel cyclic analog-to-digital converter in which a sampling stage and an amplifying stage are interleaved with a first converting unit and a second converting unit in cascade to achieve cyclic conversion of multiple bits to increase a conversion rate.

According to an aspect of the present invention, there is provided a cyclic analog-to-digital converter including: the cyclic processing unit comprises a first conversion unit and a second conversion unit which are cascaded, wherein the first conversion unit and the second conversion unit generate multi-bit intermediate data in a plurality of cycles of a conversion period; a register for storing at least multi-bit intermediate data generated in the last cycle among the plurality of cycles; and a logic unit for performing a dislocation process on the multi-bit intermediate data to generate multi-bit output data corresponding to the analog input signal bit by bit, wherein the first conversion unit and the second conversion unit interleave a sampling stage and an amplifying stage in each of the plurality of cycles.

Optionally, in each of the multiple cycles, the first conversion unit generates a bipolar intermediate analog signal and the second conversion unit generates a bipolar cycle analog signal.

Optionally, in a first one of the multiple cycles, the first conversion unit samples an analog input signal of a single polarity and compares the analog input signal with an input reference voltage to generate a first set of intermediate data.

Optionally, in a cycle subsequent to the multiple cycles, the first conversion unit samples a cyclic analog signal generated in a previous cycle and compares the cyclic analog signal with a quantized reference voltage to generate a first set of intermediate data.

Optionally, in the multiple cycles, the second conversion unit samples the intermediate analog signal and compares the intermediate analog signal with a quantized reference voltage to generate a second set of intermediate data.

Optionally, the output end of the first conversion unit is connected with a first switch, the output end of the second conversion unit is connected with a second switch, the first switch is closed and the second switch is opened in the sampling stage of the first conversion unit, and the first switch is opened and the second switch is closed in the amplifying stage of the first conversion unit.

Optionally, the first conversion unit and the second conversion unit each include: a sub-analog-to-digital converter for converting the first analog signal into multi-bit intermediate data; a sub digital-to-analog converter for converting the multi-bit intermediate data into a second analog signal; and the differential amplification module is used for amplifying the residual difference signal of the first analog signal and the second analog signal to generate an intermediate analog signal or a cyclic analog signal.

Optionally, the differential amplifying module includes an operational amplifier and a switched capacitor network, where the switched capacitor network includes a plurality of switches, and the switches are configured to switch the working state of the differential amplifying module in a sampling stage and an amplifying stage of the differential amplifying module.

Optionally, the first switch is connected between the in-phase output terminal and the anti-phase output terminal of the operational amplifier in the first conversion unit, and the second switch is connected between the in-phase output terminal and the anti-phase output terminal of the operational amplifier in the second conversion unit.

According to another aspect of the present invention, there is provided a cyclic analog-to-digital conversion method including: generating multi-bit intermediate data in a plurality of cycles of a conversion period; storing at least multi-bit intermediate data generated in the last cycle in the multiple cycles; and performing dislocation processing on the multi-bit intermediate data to generate multi-bit output data corresponding to an analog input signal bit by bit, wherein in each cycle of the multiple cycles, first-stage conversion and second-stage conversion are sequentially performed to generate a first group of intermediate data and a second group of intermediate data, and the first-stage conversion and the second-stage conversion interleave a sampling stage and an amplifying stage.

Optionally, in a first cycle of the plurality of cycles, the first stage conversion comprises sampling an analog input signal of a single polarity and comparing the analog input signal to an input reference voltage to produce the first set of intermediate data.

Optionally, in a cycle subsequent to the multiple cycles, the first stage conversion includes sampling a cyclic analog signal generated in a previous cycle and comparing the cyclic analog signal to a quantized reference voltage to generate the first set of intermediate data.

Optionally, in the multiple cycles, the second stage conversion comprises sampling an intermediate analog signal and comparing the intermediate analog signal with a quantized reference voltage to produce the second set of intermediate data.

Optionally, the cyclic analog-to-digital conversion method is used for converting an analog input signal into 2N bits of output data, and the conversion period of the analog input signal at least includes n+1 cycles, where N is an integer greater than or equal to 1.

Optionally, the cyclic analog-to-digital conversion method is used for converting an analog input signal into 2n+1 bits of output data, and the conversion period of the analog input signal at least includes n+2 cycles, where N is an integer greater than or equal to 1.

According to the cyclic analog-to-digital converter provided by the embodiment of the invention, the differential amplifying module in the first converting unit and the differential amplifying module in the second converting unit have the same circuit structure, but the working time sequences are complementary. In the sampling stage of the differential amplification module in the second conversion unit, the in-phase output end and the anti-phase output end of the operational amplifier are in short circuit, and no output signal is provided at the output end. At this time, the differential amplification module in the first conversion unit is in an amplification stage. In the amplifying stage of the differential amplifying module in the second converting unit, the in-phase output terminal and the anti-phase output terminal of the operational amplifier are disconnected from each other, and an output signal is provided at the output terminal. At this time, the differential amplification module in the first conversion unit acquires the output signal of the second stage conversion via the selector, and the first conversion unit is in a sampling stage and samples the output signal of the second conversion unit.

Thus, the differential amplification module in the first conversion unit and the differential amplification module in the second conversion unit interleave the sampling phase and the amplification phase in each cycle of the conversion period.

In summary, compared to the cyclic analog-to-digital converter of the single-stage conversion, the cyclic analog-to-digital converter according to the embodiment of the present invention includes two stages of conversion units, and although the conversion stage number is increased from single stage to two stages, since the two stages of conversion units interleave the sampling stage and the amplifying stage, the clock period consumed in each cycle of the conversion period is substantially the same. Therefore, the cyclic analog-to-digital converter according to the embodiment of the invention can increase the conversion speed to approximately 2 times.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic block diagram of a cyclic analog-to-digital converter according to the prior art.

Fig. 2 shows a schematic block diagram of a cyclic analog-to-digital converter according to an embodiment of the invention.

Fig. 3a and 3b show schematic circuit diagrams of the differential amplification module in the cyclic analog-to-digital converter of fig. 2, respectively, at different stages of the first cycle.

Fig. 4a and 4b show schematic circuit diagrams of the differential amplification module in the cyclic analog-to-digital converter of fig. 2, respectively, at different stages of a subsequent cycle.

Fig. 5 shows an operational waveform diagram of the cyclic analog-to-digital converter shown in fig. 2.

Fig. 6 shows a schematic diagram of the logical operation of the cyclic analog-to-digital converter shown in fig. 2.

Fig. 7 shows a schematic flow chart of a cyclic analog-to-digital conversion method according to an embodiment of the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.

Furthermore, it should be noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Fig. 1 shows a schematic block diagram of a cyclic analog-to-digital converter according to the prior art. The cyclic analog-to-digital converter 100 includes a selector 110, a cyclic processing unit 120, and a register 130.

The selector 110 selects one of the analog input signal Vin and the cyclic analog signal Vo as an input signal of the cyclic processing unit 120.

The cyclic processing unit 120 is configured to collect the digital value of the highest order bit from the analog input signal Vin, collect the digital values of the remaining order bits from the cyclic analog signal Vo, perform cyclic processing, and convert the analog input signal Vin into multi-bit DATA [9:0] in order from the higher order bit to the lower order bit.

Further, the cyclic processing unit 120 includes a sub-digital-to-analog converter 11, a sub-digital-to-analog converter 12, a subtractor 13, an amplifying module 14, and a sample-and-hold module 15.

The sub-analog-to-digital converter 11 compares an input signal with a reference voltage and outputs the comparison result as binary data Di. When the voltage of the input signal is higher than the reference voltage, the sub-analog-digital converter 11 outputs "1" (high) as binary data Di. When the voltage of the input signal is lower than the reference voltage, the sub-analog-digital converter 11 outputs "0" (low) as binary data Di. When the voltage of the input signal is equal to the reference voltage, the sub-analog-digital converter 11 may output "0" (low) or "1" (high) as binary data Di as needed.

The sub digital-to-analog converter 12 converts the binary data Di output from the sub digital-to-analog converter 11 into an analog signal. When the binary data Di is "1" (high), the sub digital-to-analog converter 12 outputs a reference voltage as an analog signal. When the binary data Di is "0" (low), the sub digital-to-analog converter 12 outputs 0, i.e., a ground voltage, as an analog signal.

The subtractor 13 subtracts the analog signal output from the sub digital-to-analog converter 12 from the input signal to obtain a differential signal.

The amplification module 14 amplifies the differential signal twice to obtain an amplified differential signal.

The sample-and-hold module 15 samples the amplified differential signal and outputs the sampled signal as a cyclic analog signal Vo.

The conversion period of the cyclic analog-to-digital converter 100 described above includes a predetermined number of cycles controlled with a counter. In the first cycle, the selector 110 supplies the analog input signal Vin to the input terminal of the cyclic conversion unit 120, and the sub-analog-to-digital converter 11 receives the input signal as an analog input signal.

In the second or subsequent cycle, the selector 110 supplies the cyclic analog signal Vo sampled in the previous cycle to the input terminal of the cyclic conversion unit 120, and the sub analog converter 11 receives the cyclic analog signal Vo sampled in the previous cycle as an input signal.

The cyclic analog-to-digital converter 100 collects the digital value of the highest order bit from the analog input signal Vin, collects the digital values of the remaining order bits from the cyclic analog signal Vo, performs cyclic processing, and converts the analog input signal Vin into binary data bit by bit in the order from the high order bit to the low order bit. The register 130 stores binary DATA Di bit by bit in a cycle of the conversion period, and obtains multi-bit output DATA [9:0] corresponding to the analog input signal at the end of the conversion period.

The existing cyclic analog-to-digital converter shown in fig. 1 adopts a single-stage conversion unit during cyclic processing, so that a capacitive switch network circuit for sampling and holding is complex, and the conversion rate is low due to cyclic processing of single bits, so that the cyclic analog-to-digital converter is difficult to be applied to an application scene of high-speed sampling.

Fig. 2 shows a schematic block diagram of a cyclic analog-to-digital converter according to an embodiment of the invention. The cyclic analog-to-digital converter 200 includes a selector 210, a cyclic processing unit 220, a register 230, and a logic unit 240.

The selector 210 selects the unipolar analog input signal Vin and the input reference voltage Vref as the input signals of the cyclic processing unit 220 in the first cycle of the conversion period, and selects the bipolar cyclic analog signals Vop and Von as the input signals of the cyclic processing unit 220 in the subsequent cycles of the conversion period.

The cyclic processing unit 220 collects the digital value of the highest order bit from the differential signal of the analog input signal Vin and the input reference voltage Vref, collects the digital values of the remaining order bits from the differential signal of the cyclic analog signals Vop and Von, performs cyclic processing, and converts the analog input signal Vin into multi-bit DATA [9:0] in order from the high order bit to the low order bit.

Unlike the cyclic analog-to-digital converter 100 shown in fig. 1, the cyclic analog-to-digital converter 200 according to the embodiment of the present invention includes a first conversion unit 221 and a second conversion unit 222 in cascade. The circuit configuration of the first conversion unit 221 and the second conversion unit 222 are the same, and the internal circuit configuration of the conversion unit will be described in detail below using only the first stage conversion unit 221 as an example.

The first conversion unit 221 of the cyclic processing unit 220 includes a differential amplifying module 20, a sub-digital-to-analog converter 21, a sub-digital-to-analog converter 22, and a switch K1.

The differential amplification module 20 is connected to the selector 210 to receive the input signal. The differential amplification module 20 is a circuit composed of a single operational amplifier and a switched capacitor network. Depending on the switching state, the differential amplification module 20 may operate in a variety of modes, thus sampling and amplifying the input signal during a variety of phases of the conversion cycle.

In the first cycle of the conversion period, the input signal of the differential amplifying module 20 is an analog input signal Vin and an input reference voltage Vref, and converts the single-polarity analog input signal Vin into a dual-polarity output signal. In a subsequent cycle of the conversion period, the input signal of the differential amplification module 20 is cyclic analog signals Vop and Von generated by the previous cyclic process, and the cyclic analog signals Vop and Von are compared with the quantized reference voltages Vrp and Vrn to obtain intermediate data.

The sub analog-to-digital converter 21 outputs the comparison result obtained according to the first condition as intermediate data D of a higher order, and outputs the comparison result obtained according to the second condition as intermediate data B of a lower order. When the comparison result of the input signals meets the first condition, the sub-analog-digital converter 21 outputs "1" (high) as the intermediate data D. When the comparison result of the input signals does not meet the first condition, the sub-analog-digital converter 21 outputs "0" (low) as the intermediate data D. When the comparison result of the input signals meets the second condition, the sub-analog-digital converter 21 outputs "1" (high) as the intermediate data B. When the comparison result of the input signals does not meet the second condition, the sub-analog-digital converter 21 outputs "0" (low) as the intermediate data B.

The sub digital-to-analog converter 22 reconverts the intermediate data D and B output from the sub digital-to-analog converter 21 into analog signals, and thus can generate analog signals corresponding to the intermediate data D and B.

The cyclic analog-to-digital converter 200 according to an embodiment of the present invention includes a first conversion unit 221 and a second conversion unit 222 in cascade. The first conversion unit 221 and the second conversion unit 22 together generate four bits of intermediate data A, B, C, D in each cycle of the conversion period.

Further, the register 230 stores at least four bits of intermediate data A, B, C, D of the previous cycle. The logic unit 240 adds the four-bit intermediate DATA of the previous cycle with the four-bit intermediate DATA of the present cycle in a staggered manner, and obtains multi-bit output DATA [9:0] corresponding to the analog input signal at the end of the conversion period.

According to the cyclic analog-to-digital converter 200 of the embodiment of the present invention, the first converting unit 221 includes a first switch K1 connected between the bipolar output terminals, and the second converting unit 222 includes a second switch K2 connected between the bipolar output terminals. During the sampling phase of the first conversion unit 221, the first switch K1 is closed to disable the signal output of the first conversion unit 221 and the second switch K2 is opened to enable the signal output of the second conversion unit 222. During the sampling phase of the second conversion unit 222, the first switch K1 is opened to enable the signal output of the first conversion unit 221, and the second switch K2 is closed to disable the signal output of the second conversion unit 222.

Accordingly, the first conversion unit 221 and the second conversion unit 222 may interleave the sampling phase and the amplifying phase in the conversion period. The cyclic analog-to-digital converter 200 according to the embodiment of the present invention can increase the conversion speed to approximately 2 times as compared with the cyclic analog-to-digital converter of single-stage conversion.

Fig. 3a and 3b show schematic circuit diagrams of the differential amplification module in the cyclic analog-to-digital converter of fig. 2, respectively, at different stages of the first cycle.

The circuit structures of the first conversion unit 221 and the second conversion unit 222 in the cyclic analog-to-digital converter 200 according to the embodiment of the present invention are the same, and the circuit structure of the differential amplification module 20 in the first conversion unit 221 is the same as the circuit structure of the differential amplification module 30 in the second conversion unit 222.

The circuit configuration of the conversion unit will be described in detail below taking the differential amplification module 20 in the first stage conversion unit 221 as an example only.

The differential amplification module 20 includes an operational amplifier U1, capacitors C1 to C4, switches S1 to S7, and S11 and S12.

The first input terminal of the differential amplification module 20 is connected to the non-inverting input terminal of the operational amplifier U1 via a series circuit of the switch S1 and the capacitor C1, and to the non-inverting input terminal of the operational amplifier U1 via a series circuit of the switch S2 and the capacitor C2. The second input terminal of the differential amplification module 20 is connected to the inverting input terminal of the operational amplifier U1 via a series circuit of the switch S3 and the capacitor C3, and to the inverting input terminal of the operational amplifier U1 via a series circuit of the switch S4 and the capacitor C4.

The inverting output terminal of the differential amplification module 20 is connected to the intermediate node of the switch S1 and the capacitor C1 via the switch S5, and the non-inverting output terminal is connected to the intermediate node of the switch S3 and the capacitor C3 via the switch S6.

A switch S7 is connected between the non-inverting input terminal and the inverting input terminal of the operational amplifier U1, and a series circuit of switches S11 and S12 is connected. A switch K1 is connected between the in-phase output terminal and the reverse output terminal of the operational amplifier U1.

In the first cycle of the conversion period, the differential amplifying module 20 receives the analog input signal Vin and the input reference voltage Vref of a single polarity. The differential amplification module 20 goes through the sampling phase and the amplification phase in sequence.

Referring to fig. 3a, during the sampling phase, switches S1 to S4 and S7, and switch K1 are closed, with the remaining switches being open. The analog input signal Vin, together with the input reference voltage Vref, charges the capacitors C1 to C4. Thus, the sampling phase samples the analog input signal Vin with respect to the input reference voltage Vref. At this time, the operational amplifier U1 stops operating, the in-phase output terminal and the anti-phase output terminal of the operational amplifier U1 are short-circuited, and no output signal is provided at the output terminal.

Further, in the sampling stage, the sub-analog-to-digital converter 21 in the first converting unit 221 compares the analog input signal Vin with the input reference voltage Vref to obtain intermediate data D and B of the present cycle processing.

Referring to fig. 3b, during the amplification phase, switches S5 and S6 are closed and the remaining switches are open. The capacitors C1 and C2 are disconnected from the analog input signal Vin, and the capacitors C3 and C4 are disconnected from the input reference voltage Vref. The first conversion unit 221 also receives a second analog signal Vdac corresponding to the intermediate data D and B. The operational amplifier U1 starts to operate, multiplies the differential sampling signal of the analog input signal Vin relative to the input reference voltage Vref by 2, and then subtracts the differential sampling signal from the second analog signal Vdac to obtain a residual signal of the current cycle processing. The non-inverting output terminal and the inverting output terminal of the operational amplifier U1 are disconnected from each other, and the intermediate analog signals Vp1 and Vn1 generated by the first stage conversion are supplied at the output terminals.

The differential amplifying module 20 in the first converting unit 221 has the same circuit structure as the differential amplifying module 30 in the second converting unit 222, but the operation timings are complementary. In the sampling phase of the differential amplifying module 20 in the first converting unit 221, the non-inverting output terminal and the inverting output terminal of the operational amplifier U1 are short-circuited, and an output signal is not supplied at the output terminal. At this time, the differential amplification module 30 in the second conversion unit 222 is in an amplification stage. In the amplifying stage of the differential amplifying module 20 in the first converting unit 221, the non-inverting output terminal and the inverting output terminal of the operational amplifier U1 are disconnected from each other, and an output signal is supplied at the output terminal. At this time, the differential amplifying module 30 in the second converting unit 222 is in a sampling stage, and samples the output signal of the first converting unit 221.

Accordingly, the differential amplification module 20 in the first conversion unit 221 and the differential amplification module 30 in the second conversion unit 222 may interleave the sampling phase and the amplification phase in the first cycle of the conversion period.

In the first cycle of the conversion period, the differential amplification module 20 converts the unipolar analog input signal Vin into a bipolar output signal. The bipolar signal is directly circularly processed in the subsequent cycle of the conversion period, and the input reference voltage is obtained from the outside only in the first cycle in the plurality of cycles, and the dynamically changed input reference voltage is not required to be obtained from the outside in the subsequent cycle, so that the circuit complexity and the power consumption related to the input reference voltage can be simplified.

Fig. 4a and 4b show schematic circuit diagrams of the differential amplification module in the cyclic analog-to-digital converter of fig. 2, respectively, at different stages of a subsequent cycle.

In a subsequent cycle of the conversion period, the differential amplification module 20 receives bipolar cyclic analog signals Vop and Von. The differential amplification module 20 goes through the sampling phase and the amplification phase in sequence in each cycle.

Referring to fig. 4a, during the sampling phase, switches S1 to S4, S7, S11 and S12, and switch K1 are closed, with the remaining switches being open. The cyclic analog signals Vop and Von together charge the capacitances C1 to C4. Thus, the differential signal of the cyclic analog signals Vop and Von is sampled in the sampling stage, and further, the common mode voltage Vcom is superimposed on the sampled signal. At this time, the operational amplifier U1 stops operating, the in-phase output terminal and the anti-phase output terminal of the operational amplifier U1 are short-circuited, and no output signal is provided at the output terminal.

Referring to fig. 4b, during the amplification phase, switches S5 and S6 are closed and the remaining switches are open. The capacitors C1 to C4 are disconnected from the cyclic analog signals Vop and Von. The first conversion unit 221 also receives a second analog signal Vdac corresponding to the intermediate data D and B. The operational amplifier U1 starts to operate, multiplies the differential sampling signal of the cyclic analog signals Vop and Von by 2, and then subtracts the second analog signal Vdac to obtain a residual signal of the current cyclic process. The non-inverting output terminal and the inverting output terminal of the operational amplifier U1 are disconnected from each other, and the intermediate analog signals Vp1 and Vn1 generated by the first stage conversion are supplied at the output terminals. Since the common mode voltage Vcom is already superimposed on the sampled signal in the sampling phase, the operating point of the operational amplifier U1 is set to operate linearly over the entire dynamic range.

The differential amplifying module 20 in the first converting unit 221 has the same circuit structure as the differential amplifying module 30 in the second converting unit 222, but the operation timings are complementary. In the sampling phase of the differential amplification module 30 in the second conversion unit 222, the non-inverting output terminal and the inverting output terminal of the operational amplifier U1 are short-circuited, and no output signal is provided at the output terminal. At this time, the differential amplification module 20 in the first conversion unit 221 is in an amplification stage. In the amplifying stage of the differential amplifying module 30 in the second converting unit 222, the non-inverting output terminal and the inverting output terminal of the operational amplifier U1 are disconnected from each other, and an output signal is supplied at the output terminal. At this time, the differential amplifying module 20 in the first converting unit 221 acquires the output signal of the second converting unit 221 via the selector 210, and the first converting unit 221 is in a sampling stage to sample the output signal of the second converting unit 222.

Further, the amplifying stage of the second converting unit 222 is the same as that of the first converting unit 221, and the second converting unit 22 multiplies the differential sampling signal by 2 in the amplifying stage and subtracts the differential sampling signal from the second analog signal Vdac to obtain the residual signal of the current cycle processing.

Accordingly, the differential amplification module 20 in the first conversion unit 221 and the differential amplification module 30 in the second conversion unit 222 may interleave the sampling phase and the amplification phase in each cycle of the conversion period.

In the subsequent cycle of the conversion period, the differential amplifying module 20 superimposes the common mode voltage on the sampling signal, multiplies the differential sampling signal by 2, and subtracts the second analog signal Vdac to obtain the residual signal processed in the present cycle. The superposition of the same common-mode voltage at the input of the differential amplification module 20 is advantageous for maintaining the normal operating state of the amplifier during multiple cycles of the cyclic processing unit.

In contrast to a single-stage converted cyclic analog-to-digital converter, the cyclic analog-to-digital converter 200 according to an embodiment of the present invention includes two-stage conversion units, and although the conversion stage number is increased from single stage to two stage, since the two-stage conversion units interleave the sampling stage and the amplifying stage, the clock period consumed in each cycle of the conversion period is substantially the same. Therefore, the cyclic analog-to-digital converter 200 according to the embodiment of the present invention can increase the conversion speed to approximately 2 times.

Fig. 5 shows an operational waveform diagram of the cyclic analog-to-digital converter shown in fig. 2. Fig. 6 shows a schematic diagram of the logical operation of the cyclic analog-to-digital converter shown in fig. 2.

In fig. 2, a reference symbol CLK denotes a clock signal for switching cycle counts, and a reference symbol SEL denotes a selection signal for a selector.

Taking a 10-bit resolution cyclic analog-to-digital converter as an example, the conversion period Tbyte of the cyclic analog-to-digital converter according to the embodiment of the present invention takes 6 clock cycles.

In the first clock period, the selector selects the analog input signal Vin and the input reference voltage Vref as input signals of the loop processing unit 220. In the subsequent 5 clock cycles, the selector selects the cyclic analog signals Vop and Von as input signals to the cyclic processing unit 220.

In the consecutive 5 clock cycles from the start of the conversion cycle, the cyclic analog-to-digital converter performs a cyclic process once per clock cycle. In each cycle, the two stages of conversion units of the cyclic analog-to-digital converter together produce four bits of intermediate data A, B, C, D. For example, at the first cycle, the first conversion unit generates the high-order intermediate data D4 and the low-order intermediate data B4, and the second conversion unit generates the high-order intermediate data C4 and the low-order intermediate data A4.

After 5 cycles of the conversion period, the cyclic analog-to-digital converter commonly produces 10 bits of high-order intermediate data and 10 bits of low-order intermediate data. Referring to fig. 6, the logic unit 240 adds the four-bit intermediate DATA of the previous cycle with the four-bit intermediate DATA of the current cycle in a staggered manner, and obtains multi-bit output DATA [9:0] corresponding to the analog input signal at the end of the conversion period.

Although the present embodiment is described taking an analog-to-digital converter with 10-bit precision as an example, the present invention is not limited to an analog-to-digital converter with specific precision.

For a 2N precision analog-to-digital converter, the analog-to-digital converter is configured to convert an analog input signal into 2N bits of output data, where a conversion period of the analog input signal includes at least n+1 cycles, where N is an integer greater than or equal to 1.

For a 2n+1 precision analog-to-digital converter, the analog-to-digital converter is configured to convert an analog input signal into 2n+1 bits of output data, where the conversion period of the analog input signal includes at least n+2 cycles, where N is an integer greater than or equal to 1.

Fig. 7 shows a schematic flow chart of an analog-to-digital conversion method according to an embodiment of the invention. The main steps of the corresponding analog-to-digital conversion method are further described with reference to the cyclic analog-to-digital converter 200 shown in fig. 2.

In step S01, the transition is started.

In this step, the cyclic analog-to-digital converter 200 receives an analog input signal Vin.

In step S02, four bits of intermediate data are generated based on the analog signal.

In the first of the multiple cycles, the first stage conversion includes sampling an analog input signal Vin of a single polarity and comparing the analog input signal Vin to an input reference voltage to produce a first set of intermediate data D and B.

In a subsequent cycle of the multiple cycles, the first stage conversion includes sampling the cyclic analog signals Vop and Von generated in the last cycle and comparing the cyclic analog signals Vop and Von with the quantized reference voltages Vrn and Vrp to generate a first set of intermediate data D and B.

In each of the plurality of cycles, the second stage conversion includes sampling the intermediate analog signals Vp1 and Vn1 generated by the first stage conversion and comparing the intermediate analog signals Vp1 and Vn1 with the quantized reference voltages Vrn and Vrp to generate a second set of intermediate data C and a.

Optionally, in each of the plurality of cycles, the second stage of conversion includes sampling the intermediate analog signal and comparing the intermediate analog signal to a quantized reference voltage to produce a second set of intermediate data.

In step S03, the generated four-bit intermediate data is stored using a register.

In step S04, the residual of the analog signal is obtained as a cyclic analog signal.

In the first of the multiple cycles, the first stage conversion includes multiplying the differential sampled signal of the analog input signal Vin and the input reference voltage Vref by 2 and subtracting the analog signals corresponding to the first set of intermediate data D and B to obtain intermediate analog signals Vp1 and Vn1.

In a subsequent one of the multiple cycles, the first stage of conversion comprises multiplying the differential sampled signals of the cyclic analog signals Vop and Von by 2 and subtracting the analog signals corresponding to the first set of intermediate data D and B to obtain the intermediate analog signals Vp1 and Vn1.

In each of the plurality of cycles, the second stage conversion includes multiplying the differential sampled signals of the intermediate analog signals Vp1 and Vn1 by 2 and subtracting the analog signals corresponding to the second set of intermediate data C and a to obtain the cyclic analog signals Vop and Von.

In step S05, a logic unit is used to perform a dislocation process, for example, performing a dislocation addition on the multi-bit intermediate data generated in the previous cycle and the multi-bit intermediate data generated in the current cycle, so as to obtain at least one bit of output data.

In step S06, it is determined whether the number of cycles in the conversion period reaches a predetermined value.

For a 2N precision analog-to-digital converter, the analog-to-digital converter is configured to convert an analog input signal into 2N bits of output data, where a conversion period of the analog input signal includes at least n+1 cycles, where N is an integer greater than or equal to 1.

For a 2n+1 precision analog-to-digital converter, the analog-to-digital converter is configured to convert an analog input signal into 2n+1 bits of output data, where the conversion period of the analog input signal includes at least n+2 cycles, where N is an integer greater than or equal to 1.

If the number of cycles is N or less, the process returns to step S02 to perform the next cycle. If the number of loops is greater than N, step S07 is executed, ending the conversion.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.

Claims (15)

1. A cyclic analog-to-digital converter comprising:

the cyclic processing unit comprises a first conversion unit and a second conversion unit which are cascaded, wherein the first conversion unit and the second conversion unit generate multi-bit intermediate data in a plurality of cycles of a conversion period;

a register for storing at least multi-bit intermediate data generated in the last cycle among the plurality of cycles; and

a logic unit for performing dislocation processing on the multi-bit intermediate data to generate multi-bit output data corresponding to the analog input signal bit by bit,

wherein the first and second conversion units interleave sampling and amplification phases in each of the multiple cycles.

2. The cyclic analog-to-digital converter of claim 1, wherein the first conversion unit generates a bipolar intermediate analog signal and the second conversion unit generates a bipolar cyclic analog signal in each of the plurality of cycles.

3. The cyclic analog-to-digital converter of claim 2, wherein in a first one of the multiple cycles the first conversion unit samples an analog input signal of a single polarity and compares the analog input signal to an input reference voltage to produce a first set of intermediate data.

4. The cyclic analog-to-digital converter of claim 2, wherein in a subsequent cycle of the multiple cycles, the first conversion unit samples a cyclic analog signal generated by a last cycle and compares the cyclic analog signal with a quantized reference voltage to generate a first set of intermediate data.

5. The cyclic analog-to-digital converter of claim 2, wherein in the multiple cycles the second conversion unit samples the intermediate analog signal and compares the intermediate analog signal with a quantized reference voltage to produce a second set of intermediate data.

6. The cyclic analog-to-digital converter of claim 1, wherein the output of the first conversion unit is connected to a first switch and the output of the second conversion unit is connected to a second switch, the first switch being closed and the second switch being open during a sampling phase of the first conversion unit and the first switch being open and the second switch being closed during an amplification phase of the first conversion unit.

7. The cyclic analog-to-digital converter of claim 6, wherein the first and second conversion units each comprise:

a sub-analog-to-digital converter for converting the first analog signal into multi-bit intermediate data;

a sub digital-to-analog converter for converting the multi-bit intermediate data into a second analog signal;

and the differential amplification module is used for amplifying the residual difference signal of the first analog signal and the second analog signal to generate an intermediate analog signal or a cyclic analog signal.

8. The cyclic analog-to-digital converter of claim 7, wherein the differential amplification module comprises an operational amplifier and a switched capacitor network comprising a plurality of switches for switching the operating state of the differential amplification module between a sampling phase and an amplification phase of the differential amplification module.

9. The cyclic analog-to-digital converter of claim 8, wherein the first switch is connected between the in-phase output and the anti-phase output of the operational amplifier in the first conversion unit, and the second switch is connected between the in-phase output and the anti-phase output of the operational amplifier in the second conversion unit.

10. A cyclic analog-to-digital conversion method comprising:

generating multi-bit intermediate data in a plurality of cycles of a conversion period;

storing at least multi-bit intermediate data generated in the last cycle in the multiple cycles; and

performing dislocation processing on the multi-bit intermediate data to generate multi-bit output data corresponding to the analog input signal bit by bit,

wherein, in each of the multiple cycles, a first stage conversion and a second stage conversion are performed in sequence to produce a first set of intermediate data and a second set of intermediate data, and the first stage conversion and the second stage conversion interleave a sampling stage and an amplifying stage.

11. The cyclic analog-to-digital conversion method of claim 10, wherein in a first one of the plurality of cycles, a first stage of conversion includes sampling an analog input signal of a single polarity and comparing the analog input signal to an input reference voltage to produce the first set of intermediate data.

12. The cyclic analog-to-digital conversion method of claim 10, wherein in a subsequent cycle of the multiple cycles, a first stage of conversion includes sampling a cyclic analog signal generated from a last cycle and comparing the cyclic analog signal to a quantized reference voltage to generate the first set of intermediate data.

13. The cyclic analog-to-digital conversion method of claim 10, wherein in the multiple cycles, a second stage of conversion includes sampling an intermediate analog signal and comparing the intermediate analog signal to a quantized reference voltage to produce the second set of intermediate data.

14. The cyclic analog-to-digital conversion method according to claim 10, wherein the cyclic analog-to-digital conversion method is for converting an analog input signal into 2N-bit output data, and the conversion period of the analog input signal includes at least n+1 cycles, where N is an integer of 1 or more.

15. The cyclic analog-to-digital conversion method of claim 10, wherein the cyclic analog-to-digital conversion method is used for converting an analog input signal into 2n+1 bits of output data, and the conversion period of the analog input signal includes at least n+2 cycles, where N is an integer greater than or equal to 1.