CN117792358A

CN117792358A - Reset circuit

Info

Publication number: CN117792358A
Application number: CN202311600669.XA
Authority: CN
Inventors: 张利地
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2023-11-28
Filing date: 2023-11-28
Publication date: 2024-03-29

Abstract

The invention discloses a reset circuit, which comprises a first current branch circuit, a second current branch circuit and a reset circuit, wherein the first current branch circuit generates a first current which changes along with a power supply voltage, and the first voltage is generated according to the first current; a second current branch circuit for generating a second current which changes along with the power supply voltage and generating a second voltage according to the second current; a comparator generating a reset signal according to the first voltage and the second voltage; and the hysteresis control circuit increases the first voltage by reducing the impedance of the first current branch in the power-down process of the power supply voltage, wherein the comparator is configured to be a first level when the power supply voltage is larger than a power-on turnover threshold in the power-up process of the power supply voltage, the reset signal is a second level when the power supply voltage is smaller than the power-off turnover threshold in the power-down process of the power supply voltage, and the power-off turnover threshold is smaller than the power-on turnover threshold.

Description

Reset circuit

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a reset circuit.

Background

The power-on reset circuit (Power on Reset Circuit, POR for short) can improve the stability and reliability of the circuit, and is widely applied to electronic products such as computers, mobile phones, televisions, automobile circuits and the like.

When the chip is electrified, the power supply voltage gradually rises from 0V to normal working voltage, and then components in the circuit gradually start to work. However, during the power supply voltage rising process, due to the existence of components such as capacitance and inductance, abnormal signals or voltages may occur in the circuit, and these abnormal signals or voltages may cause the chip to fail to work or generate logic errors. To avoid this, a power-on reset circuit needs to be added to the circuit. The power-on reset circuit is a circuit capable of automatically resetting when the chip is powered on, and can enable the chip to start working from an initial state when the chip is powered on.

Fig. 1 shows a schematic diagram of a power-on reset circuit according to the prior art. Referring to fig. 1, the power-on reset circuit 100 includes a transistor Mp1 and a capacitor C1 sequentially connected between a power voltage VCC and ground, and a buffer 110 having an input terminal connected to a common node a of the transistor Mp1 and the capacitor C1 and an output terminal providing a reset signal Por. In the process that the power supply voltage VCC starts to rise from 0, the voltage of the node a is 0V before the transistor Mp1 is turned on, the reset signal Por is also low, the capacitor C1 is charged through the transistor Mp1 after the power supply voltage VCC rises to turn on the transistor Mp1, and the reset signal Por becomes high when the voltage of the node a exceeds the inversion threshold of the buffer 110. Because the flip threshold of the buffer 110 is related to the power supply voltage VCC and varies widely with process and temperature, the reset voltage point of the chip is poorly defined.

In addition, in some chips, it is necessary to achieve a reset to an initial state when the power supply voltage VCC decreases to a certain voltage, for example, 1V, at which time the power supply voltage vcc=1v can maintain the maintenance of the entire logic circuit state. For the power-on reset circuit 100, during normal operation, the voltage of the node a is charged to the power supply voltage VCC, and in the process of reducing the power supply voltage VCC from the normal operation voltage to 0V, the node a is always in a state equal to or greater than the power supply voltage VCC, until the power supply voltage VCC is equal to 0, the reset signal Por may not become a low level, but at this time, the entire chip is completely powered down, and cannot be reset to the initial state. Therefore, the power-on reset circuit 100 cannot perform effective reset during the power-down process of the chip.

Therefore, a new reset circuit has to be proposed to solve the above-mentioned problems.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a reset circuit, so that an effective reset signal can be generated when the power supply voltage is powered up and powered down, and the power-up threshold voltage is greater than the power-down threshold voltage, so that the reset circuit is not easy to oscillate.

According to an aspect of the present invention, there is provided a reset circuit comprising a first current branch for generating a first current that follows a change in a supply voltage and generating a first voltage in dependence on the first current; a second current branch for generating a second current that follows the power supply voltage variation and generating a second voltage according to the second current; a comparator for generating a reset signal according to the first voltage and the second voltage; and a hysteresis control circuit configured to increase the first voltage by decreasing the impedance of the first current branch during a power-down process of the power supply voltage, wherein the comparator is configured such that, during a power-up process of the power supply voltage, when the power supply voltage is greater than the power-up inversion threshold, the reset signal is at a first level, and during a power-down process of the power supply voltage, when the power supply voltage is less than the power-down inversion threshold, the reset signal is at a second level, and the power-down inversion threshold is less than the power-up inversion threshold.

Optionally, the first current branch includes a first resistor, a second resistor, a first triode, a third resistor and a fourth resistor sequentially connected between the power supply voltage and ground, wherein a base of the first triode is connected to the power supply voltage, and a common node of the second resistor and the first triode provides the first voltage.

Optionally, the second current branch includes: the third resistor is connected with the common node of the fourth resistor, and the fourth resistor is connected with the power voltage through the third resistor.

Optionally, the resistance of the first resistor is equal to the resistance of the fifth resistor, and the resistance of the second resistor is equal to the resistance of the sixth resistor.

Optionally, the ratio of the dimensional ratios of the first transistor and the second transistor is greater than 1.

Optionally, the hysteresis control circuit includes an inverter for generating a control signal according to the reset signal; and the transistor is connected with the first resistor in parallel, and the control end receives the control signal, wherein the on-resistance of the transistor is far smaller than the resistance value of the first resistor.

Optionally, the transistor is a PMOS transistor.

Optionally, the hysteresis control circuit includes a switch and a seventh resistor connected in sequence between the power supply voltage and a common node of the first resistor and the second resistor, where a resistance value of the seventh resistor is far smaller than a resistance value of the first resistor, and the switch is controlled by the reset signal.

Optionally, the hysteresis control circuit sets the power-down flip threshold by setting an on-resistance of the transistor.

Optionally, the hysteresis control circuit sets the power-down flip threshold by setting a resistance value of the seventh resistor.

The reset circuit provided by the embodiment of the invention can generate effective reset signals when the power supply voltage is powered on and powered off, and the power-on turning threshold value is larger than the power-off turning threshold value, so that hysteresis exists in the turning level of the reset signal, and the reset circuit is not easy to oscillate. In addition, when the reset circuit is powered on at the power supply voltage, the power-on turnover threshold value can be lower than that in the prior art, and the band-gap reference core circuit is adopted to determine the power-on turnover threshold value, so that the power-on turnover threshold value basically does not change along with temperature, and the precision of a reset signal is higher. The circuit does not need to divide the power supply voltage, and has high response speed.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a power-on reset circuit according to the prior art;

fig. 2 shows a schematic diagram of a reset circuit according to the prior art;

fig. 3 shows a schematic diagram of a reset circuit according to an embodiment of the present invention;

FIG. 4 shows a schematic diagram of a first current and a second current of a reset circuit as a function of supply voltage according to an embodiment of the invention;

FIG. 5 illustrates waveforms of the reset circuit at power up and power down of the power supply voltage according to an embodiment of the present invention;

fig. 6 shows a schematic circuit diagram of a bandgap reference voltage generating circuit.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.

Furthermore, it should be noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Fig. 2 shows a schematic diagram of a reset circuit according to the prior art. Referring to fig. 2, the reset circuit 200 includes a bandgap reference voltage source 210, a comparator 220, and a voltage division module 230.

The bandgap reference voltage source 210 generates a reference voltage Vref having a voltage value of 1.2V, and compares the reference voltage Vref with the divided voltage V1 of the power supply voltage VCC by the comparator 200. In the power-on and power-off processes of the chip, when V1 is smaller than Vref, the reset signal Vdet outputs a low level, and when V1 is larger than Vref, the reset signal Vdet outputs a high level. Thus, the power-on reset circuit 200 can generate a valid reset signal during both power-up and power-down of the circuit.

However, the reset circuit 200 has the following problems:

1. if it is to be ensured that all devices are saturated, the power supply voltage VCC is at least greater than 1.5V when the reset signal Vdet is inverted.

2. The power-on and power-off turnover levels are the same, hysteresis is avoided, and oscillation is easy.

3. The power supply voltage VCC needs to be divided, and has an influence on the response speed.

Based on this, the inventors of the present application have proposed a new reset circuit to solve the above-mentioned problems.

Fig. 3 shows a schematic diagram of a reset circuit according to an embodiment of the invention. Referring to fig. 3, the reset circuit 300 includes a first current branch 310, a second current branch 320, a comparator 330, and a hysteresis control circuit 340.

The first current branch 310 is configured to generate a first current Ip that varies along with the power supply voltage VCC, and to generate a first voltage Vp according to the first current Ip.

The second current branch 320 is configured to generate a second current In that varies along with the power supply voltage VCC, and generate a second voltage Vn according to the second current In.

The comparator 330 is configured to compare the first voltage Vp and the second voltage Vn to generate a reset signal port.

The hysteresis control circuit 340 is configured to increase the first voltage Vp by decreasing the impedance of the first current branch 310 during the power-down of the power supply voltage VCC.

The comparator 300 is configured such that during power-up of the power supply voltage VCC, the reset signal Por is at a first level when the power supply voltage VCC is greater than the power-up flip threshold Vref, and during power-down of the power supply voltage VCC, the reset signal Por is at a second level when the power supply voltage VCC is less than the power-down flip threshold, and the power-down flip threshold is less than the power-up flip threshold Vref. Wherein, the chip using the reset circuit 300 is controlled to work normally when the reset signal Por is at the first level, and the chip using the reset circuit 300 is controlled to reset to the initial state when the reset signal Por is at the second level.

As shown In fig. 4, when the power supply voltage VCC is equal to the power-on inversion threshold Vref, the first current Ip is equal to the second current In, when the power supply voltage VCC is smaller than the power-on inversion threshold Vref, the first current Ip is larger than the second current In, and when the power supply voltage VCC is larger than the power-on inversion threshold Vref, the first current Ip is smaller than the second current In.

During the power-up process of the power supply voltage VCC, when the first current Ip is equal to the second current In

When the first voltage Vp is equal to the second voltage Vn, the first current Ip is greater than the second current In

The first voltage Vp is smaller than the second voltage Vn, and the first voltage Vp is larger than the second voltage Vn when the first current Ip is smaller than the second current In.

Optionally, the non-inverting input terminal of the comparator 330 receives the first voltage Vp, the inverting input terminal of the comparator 330 receives the second voltage Vn, and the output terminal of the comparator 330 provides the reset signal Por, and the first level is high and the second level is low.

The first current branch 310 includes a resistor Rp1, a resistor Rp2, a transistor Q1, a resistor R1, and a resistor R2 connected in sequence between the power supply voltage VCC and ground. The second current branch 320 includes a resistor Rn1, a resistor Rn2, and a transistor Q2 connected in sequence between the power supply voltage VCC and a common node of the resistor R1 and the resistor R2. The bases of the transistor Q1 and the transistor Q2 are connected to the power voltage VCC, the common node of the resistor Rp2 and the transistor Q1 provides the first voltage Vp, and the common node of the resistor Rn2 and the transistor Q2 provides the second voltage Vn.

Alternatively, the resistances of the resistor Rp1 and the resistor Rn1 are equal, and the resistances of the resistor Rp2 and the resistor Rn2 are equal.

Alternatively, the transistor Q1, the transistor Q2, the resistor R1, and the resistor R2 constitute a bandgap reference core circuit of the bandgap reference voltage generating circuit shown in fig. 6. The reference voltage Vref generated by the bandgap reference voltage generating circuit is the power-on flip threshold Vref in the present application, and the power-on flip threshold is, for example, 1.2V. The first current Ip and the second current In are enabled to follow the power supply voltage VCC by enabling the base voltages of the triode Q1 and the triode Q2 to follow the power supply voltage VCC.

Optionally, the size ratio of transistor Q1 to transistor Q2 is m:1. Wherein m is greater than 1. For example, the size ratio of transistor Q1 to transistor Q2 is 8:1.

the hysteresis control circuit 340 includes an inverter 341 and a transistor Mp1. The inverter 341 is configured to generate a control signal hys according to the reset signal port. The transistor Mp1 is connected between the power voltage VCC and a common node of the resistor Rp1 and the resistor Rp2, and the control terminal of the transistor Mp1 receives the control signal hys. The transistor Mp1 is connected in parallel with the resistor Rp1, and the on-resistance of the transistor Mp1 is far smaller than the resistance of the resistor Rp1, and the transistor Mp1 is a PMOS (P-Metal-Oxide-Semiconductor) tube.

In another embodiment of the present invention, the hysteresis control circuit 340 may also include a switch and a resistor Rn (not shown) connected in sequence between the power supply voltage VCC and the common node of the resistor Rp1 and the resistor Rp2, the switch being controlled by the reset signal Por, and the resistance of the resistor Rn being much smaller than the resistance of the resistor Rp 1.

The reset circuit 300 determines a power-down flip threshold by setting the on-resistance of the transistor Mp1 or setting the resistance value of the resistor Rn, where the power supply voltage VCC corresponding to the power-down flip threshold needs to ensure that the logic circuit can work normally. For example, during a power-down of the power supply voltage VCC, the reset signal Por is flipped to the second level when the power supply voltage VCC is 1V. A waveform diagram of the reset signal Por according to the power supply voltage VCC is shown in fig. 5.

The specific principle is that, since the impedance of the hysteresis control circuit 340 is far smaller than the resistor Rp1, after the hysteresis control circuit 340 is turned on and the hysteresis control circuit 340 is connected to the first current branch 310 instead of the resistor Rp1 In the power-down process of the power supply voltage VCC, since the voltage drop of the hysteresis control circuit 340 is smaller than the voltage drop of the resistor Rn1 In the case that the current values of the first current Ip and the second current In are equal, the first voltage Vp is larger than the second voltage Vn even if the first current Ip is equal to the second current In the power-down process of the power supply voltage VCC, and the first voltage Vp is equal to the second voltage Vn only when the voltage drop of the hysteresis control circuit 340 is equal to the voltage drop of the resistor Rn1, the power-down threshold can be determined by setting the on-resistance of the transistor Mp1 or the resistance value of the resistor Rn, and the on-resistance of the transistor Mp1 or the resistance value of the resistor Rn is smaller.

The reset circuit 300 provided by the embodiment of the invention can generate the effective reset signal Por when the power supply voltage VCC is powered on and powered off, and the power-on turnover threshold Vref is larger than the power-off turnover threshold, so that the turnover level of the reset signal Por is hysteresis, and the reset circuit 300 is not easy to oscillate. In addition, when the power supply voltage VCC of the reset circuit is electrified, the electrification turnover threshold Vref can be lower than that of the prior art, and the electrification turnover threshold Vref is determined by adopting the band-gap reference core circuit and basically does not change along with temperature, so that the precision of the reset signal Por is higher. The circuit does not need to divide the power supply voltage VCC, and has high response speed.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.

Claims

1. A reset circuit, comprising:

a first current branch for generating a first current which follows the change of the power supply voltage and generating a first voltage according to the first current;

a second current branch for generating a second current that follows the power supply voltage variation and generating a second voltage according to the second current;

a comparator for generating a reset signal according to the first voltage and the second voltage; and

a hysteresis control circuit for increasing the first voltage by decreasing the impedance of the first current branch during the power-down of the power supply voltage,

wherein the comparator is configured to, during a power-up of the power supply voltage, when the power supply voltage is greater than the power-up flip threshold, the reset signal is at a first level, and

in the power-down process of the power supply voltage, when the power supply voltage is smaller than a power-down turning threshold, the reset signal is of a second level, and the power-down turning threshold is smaller than the power-up turning threshold.

2. The reset circuit of claim 1, wherein the first current branch comprises:

the first resistor, the second resistor, the first triode, the third resistor and the fourth resistor are sequentially connected between the power supply voltage and the ground,

the base electrode of the first triode is connected to the power supply voltage, and the common node of the second resistor and the first triode provides the first voltage.

3. The reset circuit of claim 2, wherein the second current branch comprises:

a fifth resistor, a sixth resistor and a second triode connected in sequence between the power supply voltage and a common node of the third resistor and the fourth resistor,

the base electrode of the second triode is connected to the power supply voltage, and the common node of the sixth resistor and the second triode provides the second voltage.

4. The reset circuit of claim 3, wherein the first resistor has a resistance equal to a resistance of the fifth resistor and the second resistor has a resistance equal to a resistance of the sixth resistor.

5. The reset circuit of claim 3, wherein a ratio of a dimensional ratio of the first transistor to the second transistor is greater than 1.

6. The reset circuit of claim 2, wherein the hysteresis control circuit comprises:

an inverter for generating a control signal according to the reset signal;

a transistor connected in parallel with the first resistor, a control terminal receiving the control signal,

wherein, the on-resistance of the transistor is far smaller than the resistance value of the first resistor.

7. The reset circuit of claim 6, wherein the transistor is a PMOS transistor.

8. The reset circuit of claim 2, wherein the hysteresis control circuit comprises:

and the switch and the seventh resistor are sequentially connected between the power supply voltage and a common node of the first resistor and the second resistor, wherein the resistance value of the seventh resistor is far smaller than that of the first resistor, and the switch is controlled by the reset signal.

9. The reset circuit of claim 6, wherein the hysteresis control circuit sets the power down flip threshold by setting an on-resistance of the transistor.

10. The reset circuit of claim 8, wherein the hysteresis control circuit sets the power down flip threshold by setting a resistance value of the seventh resistor.