CN117792288A - Circuit with DiSEqC command demodulation function - Google Patents
Circuit with DiSEqC command demodulation function Download PDFInfo
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- CN117792288A CN117792288A CN202311849292.1A CN202311849292A CN117792288A CN 117792288 A CN117792288 A CN 117792288A CN 202311849292 A CN202311849292 A CN 202311849292A CN 117792288 A CN117792288 A CN 117792288A
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- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 230000000903 blocking effect Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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Abstract
The invention relates to a circuit with a DiSEqC command demodulation function. The invention comprises a demodulation circuit, an amplifying circuit and a matching circuit. The demodulation circuit comprises an NMOS tube, a Schottky diode, four resistors and three capacitors. The amplifying circuit comprises an NMOS tube, a capacitor and three resistors. The matching circuit includes a resistor, a capacitor and an inductor. The invention can demodulate the DiSEqC carrier signal of 22K into the standard CMOS level, and the upper computer CPU judges 0 and 1 by detecting the CMOS levels with different widths, thereby completing command analysis. The invention adopts the simple discrete component of triode/resistor/diode, the circuit can be conveniently integrated into the chip, and the quantity and cost of peripheral devices are reduced.
Description
Technical Field
The invention belongs to the technical field of circuit hardware, and relates to a circuit with a DiSEqC command demodulation function.
Background
The chip is a large-scale integrated circuit, which contains a large number of digital analog module units, but the voltage of the level of the chip IO port is relatively fixed (the voltage value is mostly 1.8/2.5/3.3V level, and the voltage value is mostly 3.3V), if the chip is communicated with a small signal or a signal with relatively low voltage, such as a carrier signal with the DiSEqC signal transmission amplitude of 650 mV+/-250 mV and the frequency of 22Khz, the chip IO port needs to be converted into a CMOS level which can be identified by the chip IO. The chip industry also provides the IP of the DiSEqC function module, but the cost is high, and particularly the integrated chip is short and expensive, so that a demodulation module circuit designed by using a simple discrete element such as a triode/resistor/diode is very preferable under the condition of high cost requirement, and the circuit can be conveniently integrated into the chip, so that fewer peripheral devices have lower cost.
Disclosure of Invention
The invention aims at providing a circuit with a DiSEqC command demodulation function aiming at a general digital chip, and the circuit converts a DiSEqC signal into a CMOS level function which can be identified by a chip IO.
The invention comprises a demodulation circuit, an amplifying circuit and a matching circuit.
The demodulation circuit comprises an NMOS tube, a Schottky diode, four resistors and three capacitors. One end of the first resistor R1 is connected with the collector of the first NMOS tube Q1, and is used as an output end DISEQC_IN of the whole circuit and connected with an IO port of the integrated circuit. One end of the second resistor R2 and one end of the first capacitor C1 are connected with the base electrode of the first NMOS tube Q1, and the emitter electrode of the first NMOS tube Q1 and the other end of the first capacitor C1 are grounded. The other end of the first resistor R1, one end of the third resistor R3 and one end of the second capacitor C2 are connected and then connected with a +3.3V power supply, and the other end of the second capacitor C2 is grounded. The other end of the third resistor R3 is connected with the anode of the Schottky diode D, the other end of the second resistor R2, one end of the fourth resistor R4 and one end of the third capacitor C3 are connected with the cathode of the Schottky diode D, and the other end of the fourth resistor R4 and the other end of the third capacitor C3 are grounded.
The amplifying circuit comprises an NMOS tube, a capacitor and three resistors. One end of the fifth resistor R5 is connected with the collector of the second NMOS tube Q2 and then connected with the anode of the Schottky diode D, one end of the sixth resistor R6 is connected with the base of the second NMOS tube Q2, one end of the fifth resistor R5 and one end of the seventh resistor R7 are connected with one end of the fourth capacitor C4 and then connected with a +3.3V power supply, the emitter of the second NMOS tube Q2 and the other end of the fourth capacitor C4 are grounded, and the other end of the sixth resistor R6 and the other end of the seventh resistor R7 are connected as signal input ends.
The matching circuit comprises a resistor, a capacitor and an inductor, wherein one end of an eighth resistor R8, a fifth capacitor C5 and an inductor L which are connected in parallel is connected with a signal input end through a blocking capacitor C, and the other end of the eighth resistor R8, the fifth capacitor C5 and the inductor L which are connected in parallel is used as an input end for_LNB of the whole circuit and is connected with DiSEqC equipment.
The invention can demodulate the DiSEqC carrier signal of 22K into the standard CMOS level, and the upper computer CPU judges 0 and 1 by detecting the CMOS levels with different widths, thereby completing command analysis. The invention adopts the simple discrete component of triode/resistor/diode, the circuit can be integrated into the chip conveniently, and the quantity and cost of peripheral devices are reduced.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
As shown in fig. 1, the circuit with DiSEqC command demodulation function includes a demodulation circuit, an amplifying circuit, and a matching circuit.
The demodulation circuit (left dashed box in the figure) includes an NMOS transistor, a schottky diode, four resistors, and three capacitors. One end of the first resistor R1 (6.2 KΩ) is connected with the collector of the first NMOS transistor Q1 (C1815), and is used as an output end DISEQC_IN of the whole circuit to be connected with the IO port of the integrated circuit. One end (10 nF) of the second resistor R2 (4.7 kΩ) and one end (10 nF) of the first capacitor C1 are connected to the base of the first NMOS transistor Q1, and the emitter of the first NMOS transistor Q1 and the other end of the first capacitor C1 are grounded. The other end of the first resistor R1, one end of the third resistor R3 (51 KΩ) and one end (100 nF) of the second capacitor C2 are connected and then connected with a +3.3V power supply, and the other end of the second capacitor C2 is grounded. The other end of the third resistor R3 is connected with the anode of the Schottky diode D, the other end of the second resistor R2, one end of the fourth resistor R4 (51 KΩ) and one end of the third capacitor C3 (10 nF) are connected with the cathode of the Schottky diode D, and the other end of the fourth resistor R4 and the other end of the third capacitor C3 are grounded.
The amplifying circuit (middle dashed box in the figure) comprises an NMOS tube, a capacitor and three resistors. One end of a fifth resistor R5 (6.2 KΩ) is connected with the collector of the second NMOS tube Q2 (C1815) and then connected with the anode of the Schottky diode D, one end of a sixth resistor R6 (2.2 KΩ) is connected with the base of the second NMOS tube Q2, one end of a fifth resistor R5, one end of a seventh resistor R7 (56 KΩ) and one end of a fourth capacitor C4 (100 nF) are connected and then connected with a +3.3V power supply, the emitter of the second NMOS tube Q2 and the other end of the fourth capacitor C4 are grounded, and the other end of the sixth resistor R6 and the other end of the seventh resistor R7 are connected as signal input ends.
The matching circuit (a dotted line box on the right side of the figure) comprises a resistor, a capacitor and an inductor, wherein one end of an eighth resistor R8 (10Ω), a fifth capacitor C5 (220 nF) and an inductor L (220 uH) which are connected in parallel is connected with a signal input end through a blocking capacitor C (100 nF), and the other end of the parallel is used as an input end for_LNB of the whole circuit and is connected with DiSEqC equipment.
The amplifying circuit amplifies the small signal amplitude of the DiSEqC carrier wave of 650mV to 3.3V, then sends the small signal amplitude to the post-stage demodulation circuit to demodulate the useful signal, R3, R4, C3 and D1 are detection parts, a diode detection circuit is adopted, the capacitor C3 is charged by utilizing the unidirectional property of the diode D1, the diode is cut off C3 and discharges through R4 during discharging, the charging time constant RdC is far smaller than the discharging constant RC, the voltage on the capacitor is close to the peak voltage of the triangular wave of the DiSEqC signal, the demodulation function is realized, the useful signal is demodulated, the CMOS level of 3.3V is output after the useful signal is shaped and reversed through Q1, and the DiSEqC command and data are analyzed by the chip IO. The DiSEqC signal in the matching circuit is input into the matching circuit, L1, C5 and R8 in the matching circuit are input signal frequency selection circuits, the function is to screen out useful 22K carrier signals and send the useful 22K carrier signals into a later-stage circuit, and the circuit is an RLC parallel resonance band-stop filter with a resonance point of 22KHZ.
It should be understood that the foregoing examples are illustrative of the present invention and are not intended to be limiting, and that any invention that does not depart from the spirit and scope of the present invention falls within the scope of the present invention.
Claims (1)
1. A circuit with DiSEqC command demodulation function, characterized in that:
comprises a demodulation circuit, an amplifying circuit and a matching circuit;
the demodulation circuit comprises an NMOS tube, a Schottky diode, four resistors and three capacitors; one end of the first resistor R1 is connected with the collector of the first NMOS tube Q1 and is used as an output end DISEQC_IN of the whole circuit to be connected with an IO port of the integrated circuit; one end of the second resistor R2 and one end of the first capacitor C1 are connected with the base electrode of the first NMOS tube Q1, and the emitter electrode of the first NMOS tube Q1 and the other end of the first capacitor C1 are grounded; the other end of the first resistor R1, one end of the third resistor R3 and one end of the second capacitor C2 are connected and then connected with a +3.3V power supply, and the other end of the second capacitor C2 is grounded; the other end of the third resistor R3 is connected with the anode of the Schottky diode D, the other end of the second resistor R2, one end of the fourth resistor R4 and one end of the third capacitor C3 are connected with the cathode of the Schottky diode D, and the other end of the fourth resistor R4 and the other end of the third capacitor C3 are grounded;
the amplifying circuit comprises an NMOS tube, a capacitor and three resistors; one end of a fifth resistor R5 is connected with the collector of a second NMOS tube Q2 and then connected with the anode of a Schottky diode D, one end of a sixth resistor R6 is connected with the base of the second NMOS tube Q2, one end of a seventh resistor R7 and one end of a fourth capacitor C4 are connected and then connected with a +3.3V power supply, the emitter of the second NMOS tube Q2 and the other end of the fourth capacitor C4 are grounded, and the other end of the sixth resistor R6 and the other end of the seventh resistor R7 are connected as signal input ends;
the matching circuit comprises a resistor, a capacitor and an inductor, wherein one end of the eighth resistor R8, one end of the fifth capacitor C5 and one end of the inductor L which are connected in parallel are connected with the signal input end through the blocking capacitor C, and the other end of the eighth resistor R8, the fifth capacitor C5 and the inductor L which are connected in parallel are used as an input end for_LNB of the whole circuit and are connected with DiSEqC equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311849292.1A CN117792288A (en) | 2023-12-28 | 2023-12-28 | Circuit with DiSEqC command demodulation function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311849292.1A CN117792288A (en) | 2023-12-28 | 2023-12-28 | Circuit with DiSEqC command demodulation function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117792288A true CN117792288A (en) | 2024-03-29 |
Family
ID=90384864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311849292.1A Pending CN117792288A (en) | 2023-12-28 | 2023-12-28 | Circuit with DiSEqC command demodulation function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117792288A (en) |
-
2023
- 2023-12-28 CN CN202311849292.1A patent/CN117792288A/en active Pending
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