CN117792093A

CN117792093A - Slope compensation and comparator circuit

Info

Publication number: CN117792093A
Application number: CN202410211006.7A
Authority: CN
Inventors: 许锦龙; 李瑞平
Original assignee: Shanghai Xinlong Semiconductor Technology Co ltd
Current assignee: Shanghai Xinlong Semiconductor Technology Co ltd
Priority date: 2024-02-27
Filing date: 2024-02-27
Publication date: 2024-03-29
Anticipated expiration: 2044-02-27

Abstract

The invention provides a slope compensation and comparator circuit which comprises a voltage superposition module, a voltage amplification module and a voltage comparison module. The voltage superposition module is used for superposing the ramp signal and the sampling signal and improving the load carrying capacity of the output signal. The voltage amplifying module is used for amplifying the output signal of the voltage superposition module. The voltage comparison module is used for comparing the output signal of the voltage amplification module with the output signal of the error amplifier of the booster circuit and cooperatively controlling the power tube of the booster circuit based on the comparison result output signal. The configuration can realize the functions of comparison and slope compensation on the one hand, and on the other hand, the circuit is simple, the working frequency is high, the compensation proportion is convenient to adjust, a compensation capacitor is not needed, the occupied area on the layout is small, and the cost is easier to control. The invention solves the problem that a slope compensation and comparator circuit which works at high frequency and is manufactured by using a BCD process is lacked in the prior art.

Description

Slope compensation and comparator circuit

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a slope compensation and comparator circuit.

Background

In the DC-DC circuit in the power supply field, the boost circuit is widely used, and generally needs to work in a current mode, when the duty ratio of the boost circuit is greater than 50%, subharmonic oscillation is likely to be generated, and the slope compensation is performed on the circuit in a mode of solving the subharmonic oscillation. The so-called slope compensation is to superimpose a sawtooth wave (i.e. a slope) generated by a specific circuit and a current or voltage slope sampled by a main power tube of a booster circuit according to a certain proportion to obtain a voltage, and compare the voltage with the output voltage of an Error Amplifier (EA) to generate a duty cycle signal so as to control the on duty cycle of the power tube.

In a BIPOLAR circuit, a comparator with a common base input mode is generally used for realizing the functions of slope compensation and comparison, and the circuit has high working frequency and good effect and is widely applied to a boost circuit based on the BIPOLAR. Because of the update of technology, many designs need to be designed by using a BCD process, and the original slope compensation and comparator circuit is not applicable any more, and it is necessary to provide a slope compensation and comparator circuit which is applicable to work at high frequency and is manufactured by using the BCD process.

In summary, there is a lack of a slope compensation and comparator circuit operating at high frequencies and fabricated using BCD processes.

Disclosure of Invention

The invention aims to provide a slope compensation and comparator circuit which is used for solving the technical problem that related circuits are lacked in the prior art.

In order to solve the technical problems, the invention provides a slope compensation and comparator circuit for compensating a boost circuit, which comprises a voltage superposition module, a voltage amplification module and a voltage comparison module.

The voltage superposition module is used for superposing a slope signal and a sampling signal, the sampling signal is used for representing the current of a power tube of the booster circuit, and the voltage superposition module is also used for improving the load carrying capacity of an output signal of the voltage superposition module compared with the slope signal.

The voltage amplifying module is used for amplifying the output signal of the voltage superposition module.

The voltage comparison module is used for comparing the output signal of the voltage amplification module with the output signal of the error amplifier of the booster circuit and outputting a high level or a low level based on a comparison result; and the output signal of the voltage comparison module is used for cooperatively controlling the power tube of the booster circuit.

Optionally, the voltage superposition module includes a current source, a first cascades current mirror, a first triode, and a second triode.

The first CASCODE current mirror is used for copying and amplifying the current output by the current source.

The first triode is a PNP triode, the second triode is an NPN triode, the emitter of the first triode is connected with the base electrode of the second triode, and the collector electrode of the first triode is grounded; the base electrode of the first triode is used for acquiring the slope signal, the emitter electrode of the second triode is used for outputting an intermediate signal, and the carrying capacity of the intermediate signal is higher than that of the slope signal; the voltage superposition module generates an output signal based on the intermediate signal.

The first cascades current mirror is used for providing current required by the operation of the first triode; and the collector electrode of the second triode is used for being connected with a power supply.

Optionally, the voltage superposition module further includes a first resistor and a second resistor; the first end of the first resistor is connected with the emitter of the second triode, the second end of the first resistor is connected with the first end of the second resistor, the second end of the second resistor is used for acquiring the sampling signal, and the second end of the first resistor is configured as the output end of the voltage superposition module.

Optionally, the voltage amplifying module is of a single-stage folding type common-source common-gate structure.

Optionally, the voltage amplifying module includes a second cascades current mirror, a third cascades current mirror, a differential pair, a first MOS transistor, a third resistor, and a fourth resistor.

The second CASCODE current mirror is used for outputting bias current of the differential pair.

The first input end of the differential pair is connected with the output end of the voltage superposition module, and the second input end of the differential pair is connected with the second end of the third resistor; the first output end of the differential pair is connected with the first branch of the third CASCODE current mirror; and a second output end of the differential pair is connected with a second branch of the third CASCODE current mirror.

The first MOS tube is an NMOS tube, the drain electrode of the first MOS tube is used for being connected with a power supply, the grid electrode of the first MOS tube is connected with the second branch of the third CASCODE current mirror, and the source electrode of the first MOS tube is connected with the first end of the third resistor.

The second end of the third resistor is connected with the first end of the fourth resistor, and the second end of the fourth resistor is used for being grounded; the first end of the third resistor is configured as an output end of the voltage amplifying module.

Optionally, the voltage comparison module includes a comparison unit, where the comparison unit is configured to compare an output signal of the voltage amplification module with an output signal of the error amplifier, and the comparison unit has a lead correction characteristic and a hysteresis characteristic.

Optionally, the comparing unit includes a second MOS tube and a third MOS tube, a control end of the second MOS tube is used for obtaining an output signal of the voltage amplifying module, a control end of the third MOS tube is used for obtaining an output signal of the error amplifier, and an aspect ratio of the third MOS tube is greater than an aspect ratio of the second MOS tube to achieve an advanced correction characteristic.

Optionally, the comparing unit includes a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube, the width-to-length ratio of the fourth MOS tube is equal to that of the fifth MOS tube, the width-to-length ratio of the sixth MOS tube is equal to that of the seventh MOS tube, the width-to-length ratio of the sixth MOS tube is greater than that of the fourth MOS tube, and the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are used for realizing hysteresis characteristics.

Optionally, the voltage comparison module further includes two inverters, and the output signal of the comparison unit sequentially passes through the two inverters and then serves as the output signal of the slope compensation and comparator circuit.

Optionally, the voltage comparison module includes a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor.

The second MOS tube is a PMOS tube, the source electrode of the second MOS tube is used for obtaining bias current, and the grid electrode of the second MOS tube is connected with the output end of the voltage amplification module.

The third MOS tube is a PMOS tube, a source electrode of the third MOS tube is connected with a source electrode of the second MOS tube, and a grid electrode of the third MOS tube is used for obtaining an output signal of the error amplifier.

The fourth MOS tube is an NMOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the fourth MOS tube is connected with the grid electrode of the fourth MOS tube, and the source electrode of the fourth MOS tube is used for being grounded.

The fifth MOS tube is an NMOS tube, the drain electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, the drain electrode of the fifth MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the fifth MOS tube is used for being grounded.

The sixth MOS tube is an NMOS tube, the drain electrode of the sixth MOS tube is connected with the drain electrode of the third MOS tube, the grid electrode of the sixth MOS tube is connected with the grid electrode of the fourth MOS tube, and the source electrode of the sixth MOS tube is used for being grounded.

The seventh MOS tube is an NMOS tube, the drain electrode of the seventh MOS tube is connected with the drain electrode of the second MOS tube, the grid electrode of the seventh MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the seventh MOS tube is used for being grounded.

The eighth MOS tube is a PMOS tube, a source electrode of the eighth MOS tube is used for being connected with a power supply, and a grid electrode of the eighth MOS tube is connected with a drain electrode of the eighth MOS tube.

The ninth MOS tube is an NMOS tube, the drain electrode of the ninth MOS tube is connected with the drain electrode of the eighth MOS tube, the grid electrode of the ninth MOS tube is connected with the drain electrode of the second MOS tube, and the source electrode of the ninth MOS tube is used for being grounded.

The tenth MOS tube is a PMOS tube, the source electrode of the tenth MOS tube is used for connecting a power supply, and the grid electrode of the tenth MOS tube is connected with the grid electrode of the eighth MOS tube.

The eleventh MOS tube is an NMOS tube, the drain electrode of the eleventh MOS tube is connected with the drain electrode of the tenth MOS tube, the grid electrode of the eleventh MOS tube is connected with the drain electrode of the third MOS tube, and the source electrode of the eleventh MOS tube is used for being grounded.

Compared with the prior art, the slope compensation and comparator circuit provided by the invention comprises a voltage superposition module, a voltage amplification module and a voltage comparison module. The voltage superposition module is used for superposing a slope signal and a sampling signal, the sampling signal is used for representing the current or the voltage of the power tube of the booster circuit, and the voltage superposition module is also used for improving the load carrying capacity of an output signal. The voltage amplifying module is used for amplifying the output signal of the voltage superposition module. The voltage comparison module is used for comparing the output signal of the voltage amplification module with the output signal of the error amplifier of the booster circuit and outputting a high level or a low level based on a comparison result; and the output signal of the voltage comparison module is used for cooperatively controlling the power tube of the booster circuit. The configuration can realize the functions of comparison and slope compensation on one hand, and on the other hand, the circuit is simple, the working frequency is high, the compensation proportion is convenient to adjust, a compensation capacitor is not needed, the occupied area on the layout is small, and the cost is easier to control. The invention solves the problem that a slope compensation and comparator circuit which works at high frequency and is manufactured by using a BCD process is lacked in the prior art.

Drawings

Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

FIG. 1 is a block diagram of a slope compensation and comparator circuit according to one embodiment of the present invention;

FIG. 2 is a circuit diagram of a slope compensation and comparator circuit according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a slope compensation and comparator circuit according to yet another embodiment of the present invention;

FIG. 4 is an exemplary waveform of the embodiment shown in FIG. 3;

fig. 5 is a partial enlarged view of fig. 4 when V2 rises;

fig. 6 is a partial enlarged view of fig. 4 when V2 is lowered.

Wherein:

1-a voltage superposition module; a 2-voltage amplification module; 3-a voltage comparison module.

Detailed Description

The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.

As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "first," "second," "third," or "third" may explicitly or implicitly include one or at least two such features, with "one end" and "another end" and "proximal end" and "distal end" generally referring to the respective two portions, including not only the endpoints, but also the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, e.g., as being either a fixed connection, a removable connection, or as being integral therewith; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. Furthermore, as used in this disclosure, an element disposed on another element generally only refers to a connection, coupling, cooperation or transmission between two elements, and the connection, coupling, cooperation or transmission between two elements may be direct or indirect through intermediate elements, and should not be construed as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation, such as inside, outside, above, below, or on one side, of the other element unless the context clearly indicates otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

The core idea of the invention is to provide a slope compensation and comparator circuit to solve the technical problem of lack of related circuits in the prior art.

The following description refers to the accompanying drawings.

Referring to fig. 1, the present embodiment provides a slope compensation and comparator circuit for compensating a boost circuit, which includes a voltage superposition module 1, a voltage amplification module 2 and a voltage comparison module 3.

Wherein the voltage superposition module 1 is used for superposing a ramp signal V _SAW And sample signal V _CS The sampling signal is used for representing the current or the voltage of the power tube of the booster circuit, and the voltage superposition module is also used for improving the load carrying capacity of the output signal of the voltage superposition module compared with the ramp signal.

The voltage amplifying module 2 is used for amplifying the output signal of the voltage superposition module 1.

The voltage comparison module 3 is used for comparing the output signal of the voltage amplification module with the output signal of the error amplifier of the boost circuit and outputting a high level or a low level based on the comparison result; and the output signal of the voltage comparison module is used for cooperatively controlling the power tube of the booster circuit.

Referring to fig. 2 and 3, in an embodiment, the voltage superposition module includes a current source I1, a first cascades current mirror, a first transistor Q1 and a second transistor Q2.

The first triode is a PNP triode, the second triode is an NPN triode, the emitter of the first triode is connected with the base electrode of the second triode, and the collector electrode of the first triode is grounded; the base electrode of the first triode is used for acquiring the ramp signal V _SAW The emitter of the second triode is used for outputting an intermediate signal, and the carrying capacity of the intermediate signal is higher than that of the slope signal; the voltage superposition module generates an output signal based on the intermediate signal.

The first cascades current mirror is used for providing current required by the operation of the first triode; the collector electrode of the second triode is used for being connected with a power supply VDD.

The first cascades current mirror includes a seventeenth MOS tube PM1, an eighteenth MOS tube PM2, a nineteenth MOS tube PM3, a twentieth MOS tube PM4 and a fifth resistor R1, and the specific connection relationship of the foregoing elements may be obtained according to fig. 1.

Based on the connection relation, the ramp signal V can be generated at the emitter of the second triode Q2 _SAW The same signal, while also improving the load carrying capacity.

Further, the voltage superposition module further comprises a first resistor R2 and a second resistor R3; the first end of the first resistor R2 is connected with the emitter of the second triode, the second end of the first resistor R2 is connected with the first end of the second resistor R3, the second end of the second resistor R3 is used for acquiring the sampling signal, and the second end of the first resistor R2 is configured as the output end of the voltage superposition module.

The principle of operation of the voltage superposition module is analyzed as follows: the present stage is a voltage superposition stage. I1 is a current source, PM1, PM2, PM3, PM4 and R1 form a CASCODE current mirror together, wherein PM1 and PM3 are PMOS of the same type, PM2 and PM4 are PMOS of the same type and are used for proportionally copying the current of I1, and the current is copied by the current mirrorThe ratio is N, and the current IQ 1=n×i1 flowing through the emitter of Q1. V (V) _SAW The signal is a sawtooth voltage, which is a ramp signal of a specific slope, specific frequency, generated by other circuits, which needs to be superimposed with a signal characterizing the current of the power tube. Due to V _SAW The output impedance of a signal is generally high and cannot be directly loaded, so that the signal needs to be processed to improve the loading capacity of the signal.

The emitter voltage of Q1 is first calculated and can be written as:

V _Q1E =V _SAW +V _EB1 the method comprises the steps of carrying out a first treatment on the surface of the Wherein V is _Q1E Emitter voltage of Q1, V _EB1 EB voltage of Q1.

Emitter voltage V of Q2 _Q2E Can be written as:

V _Q2E =V _Q1E -V _BE2 the method comprises the steps of carrying out a first treatment on the surface of the Wherein V is _EB2 EB voltage of Q2.

The approximation calculation can be considered as V _EB1 =V _BE2 Therefore, V can be obtained _Q2E =V _SAW Because Q2 is the connection of the emitter follower, the emitter follower has relatively large current output capacity and can output certain current in a load way.

V _CS To characterize the current of the power tube, the signal is generally obtained directly from the sampling resistor, V _CS The output impedance of the voltage source at the end is extremely low, so that the signal does not need to be processed and can be directly used for superposition.

V1 is the output of this stage, the voltage of which can be calculated as follows:

V1=V _SAW ×R3/(R2+R3)+V _CS ×R2/(R2+R3)。

generally, the V1 signal can be directly used in a comparator, but the signal amplitude of V1 is too small, which results in too high requirement for the comparator, and thus, the comparator cannot be quickly compared, and the V1 signal cannot be applied to a high-frequency switching power supply circuit. Therefore, the invention amplifies the V1 signal at high speed, and uses the amplified signal to compare with a post-stage circuit so as to realize the function of high-speed comparison.

Referring to fig. 2 and 3, the voltage amplifying module 2 is a single-stage folded cascode structure. The structure can realize the stability of the circuit without additional compensation capacitance, has higher bandwidth because of no compensation capacitance, can process V1 signals at high speed, has no additional capacitance, and can effectively reduce layout area; on the other hand, CMOS technology has lower gain than BIPOLAR technology, and therefore only a cascode structure can be used to increase the DC gain of the amplifier.

Specifically, the voltage amplifying module includes a second cascades current mirror, a third cascades current mirror, a differential pair, a first MOS transistor NM5, a third resistor R5, and a fourth resistor R6.

The second CASCODE current mirror is used for outputting bias current of the differential pair. The second cascades current mirror includes: PM1, PM2, R1, twenty-first MOS transistor PM5, twenty-second MOS transistor PM6.

The differential pair is composed of a twenty-third MOS tube PM7 and a twenty-fourth MOS tube PM8, wherein the grid electrode of the twenty-third MOS tube is configured as a first input end of the differential pair, the drain electrode of the twenty-third MOS tube is configured as a first output end of the differential pair, the grid electrode of the twenty-fourth MOS tube is configured as a second input end of the differential pair, and the drain electrode of the twenty-fourth MOS tube is configured as a second output end of the differential pair.

The third cascades current mirror includes: twenty-fifth MOS tube PM9, twenty-sixteen MOS tube PM10, twenty-seventeenth MOS tube PM11, twenty-eighteenth MOS tube PM12, sixth resistor R4, twenty-ninth MOS tube NM1, thirty-eighth MOS tube NM2, thirty-eleventh MOS tube NM3 and thirty-eighth MOS tube NM4. Wherein PM9, PM10, R4, NM1 and NM2 constitute a first branch of the third CASCODE current mirror, and PM11, PM12, NM3 and NM4 constitute a second branch of the third CASCODE current mirror.

The amplifier uses a single stage folded cascode configuration. Wherein PM5 and PM6 are current mirrors, duplicate currents of PM1 and PM2, and are used for providing bias currents for a differential pair formed by PM7 and PM8, and gates of PM7 and PM8 are a non-inverting input terminal and an inverting input terminal of the amplifier respectively. PM 9-PM 12 are CASCODE current mirrors, so that the output impedance of the CASCODE current mirrors can be improved, the DC gain of the stage is improved, and similarly, NM 1-NM 4 and R4 jointly form the CASCODE current mirrors, so that the output impedance of the CASCODE current mirrors can be improved, and the DC gain of the stage is improved; NM5 is the output stage of this stage, NM5 is the source follower, can export great electric current, provides the load current for R5, R6. R5 and R6 are feedback resistors for setting the amplification factor of the stage.

The gate of PM7 is the non-inverting input of the stage, i.e., V1, the gate of PM8 is the inverting input of the stage, and V2 is the output of the stage, where the output of V2 is:

V2=V1×(R5+R6)/R6。

when r5/r6=r2/R3, it is possible to obtain:

V2=V _SAW +V _CS ×R2/R3。

the final V2 is V _CS And V is equal to _SAW By adjusting the ratio of the R2 and R3 (or R5 and R6) resistances, V can be easily adjusted _SAW And V _CS Is added to realize slope compensation.

Finally, to increase speed, R5 and R6 require the use of resistors of as small a size as possible (e.g., using the minimum width allowed by the process) to reduce the effect of parasitic capacitance.

The specific structure of the voltage comparison module can have various choices, and the following two embodiments are described in the specification: according to the embodiment shown in fig. 2 or, according to the embodiment shown in fig. 3.

As shown in fig. 2, the voltage comparison module includes: thirty-third MOS tube PM20, thirty-fourth MOS tube PM21, thirty-fifth MOS tube PM22, thirty-sixth MOS tube PM23, thirty-seventeenth MOS tube PM24, thirty-eighth MOS tube PM25, thirty-ninth MOS tube PM26, fortieth MOS tube PM27, seventh resistor R7, forty-first MOS tube NM14, forty-second MOS tube NM15, forty-third MOS tube NM16, forty-fourth MOS tube NM17, forty-fifth MOS tube PM28, forty-sixty-first MOS tube NM18, forty-seventeenth MOS tube PM29, forty-eighth MOS tube NM19, forty-ninth MOS tube PM30 and fifty-fifth MOS tube NM20.

The main circuit of the stage is largely similar to the part of the voltage amplifying module, except that the corresponding output stage is omitted. The comparator of the stage is of a folding type common-source common-gate structure, and the whole circuit gain can be improved by using the structure, so that the sensitivity of the comparator is improved, and the speed of the comparator is improved. NM18 and PM28 form an inverter, NM19 and PM29 form an inverter, and NM20 and PM30 form an inverter. Although only one set of inverters may be used here, three sets of inverters may better shape the output of the comparator. The OUT terminal is the output of the comparator. In order to increase the speed, the sizes of the PM22 and the PM23 are as small as possible, and parasitic capacitance is reduced, and the typical value is 1-5 times of the minimum-size MOS allowed by the process.

VE is the output signal of the error amplifier, the V2 signal is compared with the VE signal, wherein a duty ratio signal is obtained, and the duty ratio signal is used for controlling the on-off time of a power tube of the booster circuit, so that the purpose of controlling output is achieved.

The flip-point of the final comparator can be written as:

VE=V _SAW +V _CS ×R2/R3

this expression can be used to calculate and design the content related to the slope compensation of the boost circuit, and will not be described here again.

Due to V _SAW The signal generally has a slow rising edge variation and a very steep falling edge variation due toThe V2 signal is also mainly composed of V _SAW The signal determination is such that the rising edge of the V2 signal changes slowly and the falling edge changes very steeply. VE is an output signal of an error amplifier (not shown), which generally changes slowly and can be considered as a direct current signal for a certain period of time. The characteristics of the V2 signal and the VE signal lead to small change rate of V2 relative to VE when the V2 signal rises and the conventional comparator needs to overturn, so that the conventional comparator cannot overturn rapidly, the output delay is high, and the system design in high-frequency application is not facilitated; when the V2 signal rises, the change rate of V2 relative to VE is high, and the conventional comparator can be turned over quickly without influence.

Based on the above analysis, please refer to fig. 3, in a preferred embodiment, the voltage comparing module includes a comparing unit, the comparing unit is configured to compare the output signal of the voltage amplifying module and the output signal of the error amplifier, and the comparing unit has an advanced correction characteristic and a hysteresis characteristic.

Specifically, the comparing unit includes a second MOS tube PM14 and a third MOS tube PM15, where a control end of the second MOS tube PM14 is configured to obtain an output signal of the voltage amplifying module, a control end of the third MOS tube PM15 is configured to obtain an output signal VE of the error amplifier, and a width-to-length ratio of the third MOS tube PM15 is greater than a width-to-length ratio of the second MOS tube PM14 to implement advanced correction characteristics.

Specifically, the comparing unit includes a fourth MOS transistor NM6, a fifth MOS transistor NM7, a sixth MOS transistor NM8, and a seventh MOS transistor NM9, the width-to-length ratio of the fourth MOS transistor NM6 and the fifth MOS transistor NM7 are equal, the width-to-length ratio of the sixth MOS transistor NM8 and the seventh MOS transistor NM9 are equal, the width-to-length ratio of the sixth MOS transistor NM8 is greater than the width-to-length ratio of the fourth MOS transistor NM6, and the fourth MOS transistor NM6, the fifth MOS transistor NM7, the sixth MOS transistor NM8, and the seventh MOS transistor NM9 are used for realizing hysteresis characteristics.

Specifically, the voltage comparison module further comprises two inverters, and the output signal of the comparison unit sequentially passes through the two inverters and then serves as the output signal of the slope compensation and comparator circuit.

Further, the voltage comparison module comprises a second MOS tube PM14, a third MOS tube PM15, a fourth MOS tube NM6, a fifth MOS tube NM7, a sixth MOS tube NM8, a seventh MOS tube NM9, an eighth MOS tube PM16, a ninth MOS tube NM10, a tenth MOS tube PM17, an eleventh MOS tube NM11, a twelfth MOS tube PM13, a thirteenth MOS tube PM18, a fourteenth MOS tube NM12, a fifteenth MOS tube PM19 and a sixteenth MOS tube NM13; wherein,

the twelfth MOS tube is a PMOS tube, a source electrode of the twelfth MOS tube is used for being connected with a power supply, and a grid electrode of the twelfth MOS tube is used for obtaining a bias voltage so that a drain electrode of the twelfth MOS tube outputs bias current. In this embodiment, the bias current is generated by the second CASCODE current mirror. The bias current is typically 4uA to 40uA.

The second MOS tube is a PMOS tube, the source electrode of the second MOS tube is connected with the drain electrode of the twelfth MOS tube to obtain bias current, and the grid electrode of the second MOS tube is connected with the output end of the voltage amplifying module.

The thirteenth MOS tube is a PMOS tube, a source electrode of the thirteenth MOS tube is used for being connected with a power supply, and a grid electrode of the thirteenth MOS tube is connected with a drain electrode of the eleventh MOS tube.

The fourteenth MOS tube is an NMOS tube, the drain electrode of the fourteenth MOS tube is connected with the drain electrode of the thirteenth MOS tube, the grid electrode of the fourteenth MOS tube is connected with the grid electrode of the thirteenth MOS tube, and the source electrode of the fourteenth MOS tube is used for being grounded.

The fifteenth MOS tube is a PMOS tube, a source electrode of the fifteenth MOS tube is used for being connected with a power supply, and a grid electrode of the fifteenth MOS tube is connected with a drain electrode of the thirteenth MOS tube.

The sixteenth MOS tube is an NMOS tube, the drain electrode of the sixteenth MOS tube is connected with the drain electrode of the fifteenth MOS tube, the grid electrode of the sixteenth MOS tube is connected with the grid electrode of the fifteenth MOS tube, and the source electrode of the sixteenth MOS tube is used for being grounded.

The thirteenth MOS tube and the fourteenth MOS tube form one inverter, and the fifteenth MOS tube and the sixteenth MOS tube form the other inverter. The remaining MOS tubes constitute the comparison unit.

As can be seen from the complete fig. 2 or 3, the compensation capacitor is not present in the full circuit diagram of the embodiment, and the full circuit diagram can work without the compensation capacitor.

In view of the problem that the output delay of the turning-over output is high when the V2 rises, the problem that the output delay of the comparison unit is high when the V2 rises can be effectively solved by using the asymmetric differential input tube for advanced correction; meanwhile, the slope of the V2 is very large when the V2 is reduced, so that the asymmetric differential input tube cannot cause large errors on the output of the V2 when the V2 is reduced, namely, the hysteresis characteristic cannot cause large errors. The ratio of width to length of PM14 and PM15 can be based on the output delay T at the rise of V2 when using symmetrical differential input tubes _D ，V _SAW Rising slope S of signal _R Comparing bias current I of unit _PB The calculation, technological parameters and the like are calculated as follows:

wherein mu _P Mobility of P-type material, C _OX Capacitance per unit area, M ₁₄ Is PM ₁₄ Ratio of width to length, V _OV14 VGS overdrive voltage for PM14, where μ _P And C _OX As process-related parameters, when I _PB And M ₁₄ Is well set to obtain V _OV14 。

The OFFSET voltage to be compensated is V _OFFSET The method comprises the following steps:

V _OFFSET =S _R T _D ×R3/(R3+R2)。

wherein T is _D Can be obtained through calculation or simulation, S _R Is V (V) _SAW The rising slope of the signal voltage.

The aspect ratio M of PM15 can be obtained by the following equation ₁₅ ：

M ₁₅ =I _PB /(μ _P C _OX (V _OV14 -V _OFFSET ) ² )。

NM 6-NM 9 is used for setting a hysteresis window of a hysteresis comparison unit, wherein the width-to-length ratio of NM6 is equal to that of NM7, and the width-to-length ratio of NM8 is equal to that of NM 9. The aspect ratio of NM8 and NM9 is slightly larger than that of NM6 and NM7, and the hysteresis comparison unit is typically characterized in that the hysteresis window is generally 1mv to 20mv.

The NM10, NM11, PM16, PM17 constitute the output stage of the comparison unit, wherein the aspect ratio of NM10 is equal to the aspect ratio of NM11, the aspect ratio of PM16 is equal to the aspect ratio of PM17, and the dimensions of these pipes are as small as possible to increase the response speed.

In order to make the rising and falling edge slopes of the output signal of the comparison unit larger, two stages of inverters are additionally added for shaping, wherein NM12 and PM18 are one group, and NM13 and PM19 are one group. Because of the high frequency application, the size of the inverter of one group of NM12 and PM18 is as small as possible, the capacitance is reduced, and the response speed of the front stage is improved; the inverters of the NM13 and PM19 group may be sized appropriately to increase the output load capability of STAGE 3.

The OUT signal is an output signal of the voltage comparison module, and is generally used for controlling the power tube to be turned on or turned off.

Through the arrangement, the following functions are realized:

1. the voltage superposition module realizes V _SAW Signal and V _CS Linear superposition of the signals.

2. The voltage amplification module amplifies the V1 signal at a high speed, and by setting R5/R6=R2/R3, the superposition of high-quality slope signals is realized, and the slope compensation function is completed; meanwhile, the high-speed amplification of the voltage amplification module provides a basis for the high-speed comparison of the voltage comparison module.

3. The voltage comparison module uses an asymmetric differential input tube with careful design, realizes advanced correction, can also have quick response when V2 slowly rises, is matched with a hysteresis comparator with a hysteresis window of 1-20 mV, realizes high-precision and high-speed comparator overturning, and can be applied to a high-frequency BOOST comparator.

The beneficial effects of this embodiment are demonstrated by figures 4, 5 and 6.

Fig. 4 is a typical waveform of the present circuit, wherein:

first behavior V _SAW The waveform of the voltage signal is 0V-1.5V, and the period is 1us.

Second behavior of the sampling signal V of the power current _CS The voltage signal is 10 mV-30 mV, and the period is 1us.

A third behavior V1 signal, which can be seen as V _SAW Signal and V _CS And (3) superposing signals, wherein the superposed signals are voltage signals of about 0V-0.25V.

The fourth behavior is a V2 signal and a VE signal, where the V2 signal is an amplification of the V1 signal, approximately 6 times greater in the figure, the VE signal is at a fixed level, approximately 800mv, and the VE signal is to be compared with the V2 signal.

The fifth action is OUT output signal, namely the output result after the VE signal is compared with the V2 signal.

The circuit can realize the functions of voltage superposition and comparison, is convenient to superpose, has no obvious distortion and can meet most application scenes.

Fig. 5 is an enlarged image of V2 rising, and it can be seen from the figure that after V2 and VE intersect, the comparator turns over about 10ns, so that the response speed is very fast, and most of BOOST circuit applications can be satisfied.

Fig. 6 is an enlarged image of V2 falling, and it can be seen from the figure that after V2 and VE intersect, the comparator turns over after about 17ns, and the response speed is very fast, so that most of BOOST circuit applications can be satisfied.

In summary, the present embodiment provides a slope compensation and comparator circuit. The slope compensation and comparator circuit comprises a voltage superposition module, a voltage amplification module and a voltage comparison module. The voltage superposition module is used for superposing a slope signal and a sampling signal, the sampling signal is used for representing the current or the voltage of the power tube of the booster circuit, and the voltage superposition module is also used for improving the load carrying capacity of an output signal. The voltage amplifying module is used for amplifying the output signal of the voltage superposition module. The voltage comparison module is used for comparing the output signal of the voltage amplification module with the output signal of the error amplifier of the booster circuit and outputting a high level or a low level based on a comparison result; and the output signal of the voltage comparison module is used for cooperatively controlling the power tube of the booster circuit. The configuration can realize the functions of comparison and slope compensation on the one hand, and on the other hand, the circuit of the embodiment is simple, the working frequency is high, the compensation proportion is convenient to adjust, compensation capacitors are not needed, the occupied area on the layout is small, and the cost is easier to control. The embodiment solves the problem that a slope compensation and comparator circuit which works at high frequency and is manufactured by using a BCD process is lacked in the prior art.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.

Claims

1. The slope compensation and comparator circuit is used for compensating the boost circuit and is characterized by comprising a voltage superposition module, a voltage amplification module and a voltage comparison module; wherein,

the voltage superposition module is used for superposing a slope signal and a sampling signal, the sampling signal is used for representing the current of a power tube of the booster circuit, and the voltage superposition module is also used for improving the load carrying capacity of an output signal of the voltage superposition module compared with the slope signal;

the voltage amplifying module is used for amplifying the output signal of the voltage superposition module;

2. The slope compensation and comparator circuit of claim 1, wherein the voltage superposition module comprises a current source, a first cascades current mirror, a first transistor, and a second transistor; wherein,

the first CASCODE current mirror is used for copying and amplifying the current output by the current source;

the first triode is a PNP triode, the second triode is an NPN triode, the emitter of the first triode is connected with the base electrode of the second triode, and the collector electrode of the first triode is grounded; the base electrode of the first triode is used for acquiring the slope signal, the emitter electrode of the second triode is used for outputting an intermediate signal, and the carrying capacity of the intermediate signal is higher than that of the slope signal; the voltage superposition module generates an output signal based on the intermediate signal;

3. The slope compensation and comparator circuit of claim 2, wherein the voltage superposition module further comprises a first resistor and a second resistor; the first end of the first resistor is connected with the emitter of the second triode, the second end of the first resistor is connected with the first end of the second resistor, the second end of the second resistor is used for acquiring the sampling signal, and the second end of the first resistor is configured as the output end of the voltage superposition module.

4. The slope compensation and comparator circuit of claim 1, wherein the voltage amplification module is a single stage folded cascode structure.

5. The slope compensation and comparator circuit of claim 4, wherein the voltage amplification module comprises a second cascades current mirror, a third cascades current mirror, a differential pair, a first MOS transistor, a third resistor, and a fourth resistor; wherein,

the second cascades current mirror is used for outputting bias current of the differential pair;

the first input end of the differential pair is connected with the output end of the voltage superposition module, and the second input end of the differential pair is connected with the second end of the third resistor; the first input end of the differential pair is connected with the first branch of the third CASCODE current mirror; the second output end of the differential pair is connected with the second branch of the third CASCODE current mirror;

the first MOS tube is an NMOS tube, the drain electrode of the first MOS tube is used for being connected with a power supply, the grid electrode of the first MOS tube is connected with the second branch of the third CASCODE current mirror, and the source electrode of the first MOS tube is connected with the first end of the third resistor;

6. The slope compensation and comparator circuit of claim 1, wherein the voltage comparison module comprises a comparison unit for comparing an output signal of the voltage amplification module with an output signal of the error amplifier, the comparison unit having a lead correction characteristic and a hysteresis characteristic.

7. The slope compensation and comparator circuit of claim 6, wherein the comparison unit comprises a second MOS transistor and a third MOS transistor, a control end of the second MOS transistor is configured to obtain an output signal of the voltage amplification module, a control end of the third MOS transistor is configured to obtain an output signal of the error amplifier, and an aspect ratio of the third MOS transistor is greater than an aspect ratio of the second MOS transistor to achieve an advanced correction characteristic.

8. The slope compensation and comparator circuit of claim 6, wherein the comparison unit comprises a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor, the width-to-length ratios of the fourth MOS transistor and the fifth MOS transistor are equal, the width-to-length ratio of the sixth MOS transistor and the seventh MOS transistor are equal, the width-to-length ratio of the sixth MOS transistor is greater than the width-to-length ratio of the fourth MOS transistor, and the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are configured to implement hysteresis characteristics.

9. The slope compensation and comparator circuit of claim 6, wherein said voltage comparison module further comprises two inverters, and wherein the output signal of said comparison unit sequentially passes through said two inverters to be used as the output signal of said slope compensation and comparator circuit.

10. The slope compensation and comparator circuit of claim 6, wherein the voltage comparison module comprises a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor; wherein,

the second MOS tube is a PMOS tube, the source electrode of the second MOS tube is used for obtaining bias current, and the grid electrode of the second MOS tube is connected with the output end of the voltage amplifying module;

the third MOS tube is a PMOS tube, the source electrode of the third MOS tube is connected with the source electrode of the second MOS tube, and the grid electrode of the third MOS tube is used for obtaining the output signal of the error amplifier;

the fourth MOS tube is an NMOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the fourth MOS tube is connected with the grid electrode of the fourth MOS tube, and the source electrode of the fourth MOS tube is used for being grounded;

the fifth MOS tube is an NMOS tube, the drain electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, the drain electrode of the fifth MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the fifth MOS tube is used for being grounded;

the sixth MOS tube is an NMOS tube, the drain electrode of the sixth MOS tube is connected with the drain electrode of the third MOS tube, the grid electrode of the sixth MOS tube is connected with the grid electrode of the fourth MOS tube, and the source electrode of the sixth MOS tube is used for being grounded;

the seventh MOS tube is an NMOS tube, the drain electrode of the seventh MOS tube is connected with the drain electrode of the second MOS tube, the grid electrode of the seventh MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the seventh MOS tube is used for being grounded;

the eighth MOS tube is a PMOS tube, the source electrode of the eighth MOS tube is used for connecting a power supply, and the grid electrode of the eighth MOS tube is connected with the drain electrode of the eighth MOS tube;

the ninth MOS tube is an NMOS tube, the drain electrode of the ninth MOS tube is connected with the drain electrode of the eighth MOS tube, the grid electrode of the ninth MOS tube is connected with the drain electrode of the second MOS tube, and the source electrode of the ninth MOS tube is used for being grounded;

the tenth MOS tube is a PMOS tube, the source electrode of the tenth MOS tube is used for connecting a power supply, and the grid electrode of the tenth MOS tube is connected with the grid electrode of the eighth MOS tube;