CN117790504A

CN117790504A - Field effect transistor structure and method of manufacturing semiconductor device

Info

Publication number: CN117790504A
Application number: CN202311256020.0A
Authority: CN
Inventors: 李钟振; 洪元赫; 徐康一
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-09-28
Filing date: 2023-09-26
Publication date: 2024-03-29

Abstract

A field effect transistor structure and a method of manufacturing a semiconductor device are provided. The field effect transistor structure includes: a channel structure; a first source/drain region and a second source/drain region connected to each other through the channel structure; a first contact plug on a top surface of the first source/drain region connected to a first voltage source or a first circuit element through a back-end-of-line (BEOL) structure; and a second contact plug connected to the first voltage source or another circuit element through a back side power rail on a bottom surface of the second source/drain region, wherein the first source/drain region and the second source/drain region have substantially the same height.

Description

Field effect transistor structure and method of manufacturing semiconductor device

Technical Field

Apparatuses and methods consistent with example embodiments of the present disclosure relate to Field Effect Transistors (FETs) having uniformly sized source/drain regions on self-aligned direct backside contact structures of a backside power distribution network (BSPDN).

Background

The increasing demand for integrated circuits with high device density and performance has introduced Field Effect Transistors (FETs), such as fin field effect transistors (finfets) and nanoflake transistors. A FinFET has one or more horizontally arranged vertical fin structures as channel structures, at least three surfaces of which are surrounded by gate structures, and a nanoflake transistor is characterized by one or more nanoflake channel layers vertically stacked on a substrate as channel structures and gate structures surrounding all four surfaces of each nanoflake channel layer. The nanoplate transistor is known as a full wrap Gate (GAA) transistor, a multi-bridge channel field effect transistor (MBCFET).

In addition, a backside power distribution network (BSPDN) formed on the backside of the field effect transistor has been introduced to address wiring complexity at the back-end-of-line (BEOL) (i.e., the front side of the field effect transistor) and to prevent excessive IR drop at the front side in the field effect transistor. The BSPDN includes a back side power rail through which a positive or negative voltage may be provided to the source/drain regions of the field effect transistor.

The back side power rail may be connected to the top surface of the source/drain regions using a front via back side power rail (fkbp) structure as a contact plug. Alternatively, the backside power rail may also be directly connected to the bottom surface of the source/drain regions using a Direct Backside Contact (DBC) structure as a contact plug. However, forming a DBC structure in the back side of a field effect transistor with a BSPDN may affect the formation of other elements of the field effect transistor including source/drain regions. Accordingly, there is a need for improved semiconductor devices or cell structures including field effect transistors having both backside contact plugs and front side contact plugs and methods of fabricating the same.

The information disclosed in this background section is already known to the inventors prior to the implementation of the embodiments of the application or is technical information obtained during the implementation of the embodiments described herein. It may therefore contain information that does not constitute prior art known to the public.

Disclosure of Invention

Various example embodiments provide a semiconductor cell including at least one field effect transistor, wherein a front side contact plug and a back side contact plug are formed on respective source/drain regions having the same or substantially the same height or size.

Embodiments also provide a method of manufacturing a semiconductor unit including at least one field effect transistor, wherein a front side contact plug and a back side contact plug are formed on respective source/drain regions having the same or substantially the same height or size.

According to an embodiment, a field effect transistor structure is provided, which may include: a channel structure; a first source/drain region and a second source/drain region connected to each other by a channel structure; a first contact plug on a top surface of the first source/drain region connected to a first voltage source or a first circuit element through a back-end-of-line (BEOL) structure; and a second contact plug connected to the first voltage source or another circuit element through a back side power rail on a bottom surface of the second source/drain region, wherein the first source/drain region and the second source/drain region have substantially the same height.

According to an embodiment, a field effect transistor structure is provided, which may include: a channel structure; a first source/drain region and a second source/drain region connected to each other through the channel structure; a first contact plug on a top surface of the first source/drain region connected to a first voltage source or a first circuit element through a back-end-of-line (BEOL) structure; and a second contact plug connected to the first voltage source or the other circuit element through the back side power supply rail on a bottom surface of the second source/drain region, wherein the first source/drain region and the second source/drain region have substantially the same size and top surfaces of the first source/drain region and the second source/drain region are substantially at the same level in a cross-sectional view in a channel width direction or a channel length direction.

According to an embodiment, a method of manufacturing a field effect transistor structure is provided. The method may include: forming a channel structure on a substrate; forming a first recess and a second recess on the substrate such that the channel structure is vertically positioned on a portion of the substrate between the first recess and the second recess; forming a first placeholder structure and a second placeholder structure in the first groove and the second groove respectively; forming a first source/drain region and a second source/drain region on the first and second placeholder structures, respectively; removing the first and second placeholder structures from the first and second grooves; and forming a backside contact plug in the second recess from which the second placeholder structure is removed.

Drawings

Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1A to 1D illustrate a semiconductor cell after forming a dummy gate structure to surround a plurality of channel structures on a substrate according to an embodiment;

fig. 2A to 2D illustrate a semiconductor cell after forming a thin protective liner in side surfaces of a plurality of trenches formed between dummy gate structures according to an embodiment;

Fig. 3A to 3D illustrate a semiconductor unit after forming a first photoresist and a mask structure on the semiconductor unit obtained in the previous step according to an embodiment;

fig. 4A to 4D illustrate a semiconductor cell after a previously formed trench between dummy gate structures is re-exposed based on a first photoresist and a mask structure and a Base Diffusion Isolation (BDI) layer exposed through the trench is removed, according to an embodiment;

fig. 5A to 5D illustrate a semiconductor unit after recessing a portion of a substrate exposed by a removed BDI layer to form a plurality of grooves in the substrate, according to an embodiment;

fig. 6A to 6D illustrate a semiconductor unit after a portion of a first photoresist and a mask structure for forming grooves in a substrate is removed and the grooves are modified to have a first predetermined shape having a positive slope according to an embodiment;

fig. 7A-7D illustrate a semiconductor cell after a plurality of placeholder structures including a dummy placeholder structure are filled in a recess formed in a substrate, according to an embodiment;

fig. 8A-8D illustrate a semiconductor cell after forming a barrier layer on a top surface of each of the placeholder structures in the substrate, according to an embodiment;

Fig. 9A to 9D illustrate a semiconductor unit after removing a thin protective liner formed in a trench according to an embodiment;

10A-10D illustrate a semiconductor cell after forming source/drain regions of two nanoflake transistors, according to one embodiment;

fig. 11A-11D illustrate a semiconductor cell after a first interlayer dielectric (ILD) structure is formed thereon and a gate hard mask structure is removed to expose a dummy gate structure formed thereunder, in accordance with an embodiment;

fig. 12A to 12D illustrate a semiconductor cell after removing a dummy gate structure and a sacrificial layer included in a channel structure according to an embodiment;

fig. 13A to 13D illustrate a semiconductor cell after a dummy gate structure and a sacrificial layer in a channel structure are replaced with a plurality of gate structures according to an embodiment;

fig. 14A to 14D illustrate the semiconductor unit after forming a second photoresist and a mask structure on the semiconductor unit obtained in the previous step according to an embodiment;

fig. 15A to 15D illustrate a semiconductor unit after opening a second photoresist and a mask structure at a position corresponding to a gate cut structure to be formed in a subsequent step according to an embodiment;

Fig. 16A to 16D illustrate the semiconductor unit after forming a gate cutting trench in the semiconductor unit obtained in the previous step according to an embodiment;

17A-17D illustrate a semiconductor cell after filling a gate cut trench with a dielectric material, according to an embodiment;

fig. 18A-18D illustrate the semiconductor cell after a second ILD structure is formed thereon, in accordance with an embodiment;

fig. 19A to 19D illustrate a semiconductor unit after a plurality of MOL contact plugs are formed on source/drain regions and a gate structure according to an embodiment;

fig. 20A to 20D illustrate the semiconductor unit after forming a third ILD structure and a plurality of via structures therein on the semiconductor unit obtained in the previous step, according to an embodiment;

fig. 21A-21D illustrate a semiconductor cell after forming a fourth ILD structure and a plurality of first metal lines therein, according to an embodiment;

22A-22D illustrate a semiconductor unit after forming a plurality of back end of line (BEOL) layers, a bonding layer, and a carrier wafer on a first metal line according to one embodiment;

fig. 23A to 23D illustrate a semiconductor unit after etching a substrate to expose an etch stop layer formed at a predetermined level from the bottom of the substrate, according to an embodiment;

Fig. 24A to 24D illustrate a semiconductor unit after removing an etch stop layer according to an embodiment;

fig. 25A to 25D illustrate a semiconductor unit after removing a substrate according to an embodiment;

fig. 26A-26D illustrate the semiconductor cell after a fifth ILD structure is formed on a backside of the semiconductor cell to enclose the placeholder structure, according to an embodiment;

fig. 27A-27D illustrate a semiconductor cell after a backside mask structure is formed at the backside of the semiconductor cell to expose a dummy placeholder structure to be removed in a subsequent step, according to an embodiment;

fig. 28A-28D illustrate a semiconductor cell after removal of a dummy placeholder structure, according to an embodiment;

fig. 29A-29D illustrate a semiconductor cell after filling the space left by removing the dummy placeholder structure with a sixth ILD structure and planarizing the backside of the semiconductor cell to form a second predetermined shape of remaining placeholder structure having a positive slope, according to an embodiment;

FIGS. 30A-30D illustrate a semiconductor cell after removal of the remaining placeholder structures, according to an embodiment;

fig. 31A to 31D illustrate a semiconductor unit after removing a barrier layer according to an embodiment;

FIGS. 32A-32D illustrate a semiconductor cell after formation of a backside contact plug in a space left by removal of a remaining placeholder structure and a barrier layer thereon, according to an embodiment;

fig. 33A-33D illustrate the semiconductor cell after forming a seventh ILD structure and a backside power rail therein, in accordance with an embodiment;

figures 34A-34D illustrate a semiconductor cell according to an embodiment in which no barrier layer remains between the source/drain regions and the sixth ILD structure after the semiconductor cell is completed;

fig. 35A-35D illustrate a semiconductor cell according to an embodiment, wherein a barrier layer remains between the source/drain region and the sixth ILD structure and between the source/drain region and the backside contact plug when the semiconductor cell is completed;

36A-36D illustrate a semiconductor cell including two field effect transistors, each having two source/drain regions of different heights or sizes, according to an embodiment;

fig. 37 is a flowchart showing a method of manufacturing a semiconductor device including a field effect transistor, the source/drain regions of which are connected to a front-side contact plug and a back-side contact plug, respectively, according to an embodiment; and

Fig. 38 is a schematic block diagram illustrating an electronic device including a field effect transistor having both front and rear contact plugs as shown in fig. 33A to 33D, 34A to 34D, 35A to 35D, or 36A to 36D, according to an embodiment.

Detailed Description

The embodiments of the present disclosure described herein are example embodiments, and thus, the present disclosure is not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description does not preclude the association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with the present disclosure. For example, even if what is described in a particular example or embodiment is not described in a different example or embodiment thereof, such what is may be understood as being related to or combined with the different example or embodiment unless otherwise mentioned in the description thereof. Further, it is to be understood that all statements of the principles, aspects, examples, and embodiments of the present disclosure are intended to encompass both structural and functional equivalents thereof. Furthermore, it should be understood that such equivalents include not only currently known equivalents but also equivalents developed in the future, i.e., all devices invented to perform the same function, regardless of structure. For example, the channel layer, nanoplatelet sacrificial layer, sacrificial spacer layer, and channel spacer layer described herein may take different types or forms, so long as the disclosure may be applied thereto.

It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as "an element") of a semiconductor device is referred to as being "over", "on", "under", "below", "beneath", "connected to" or "coupled to" another element of the semiconductor device, it can be directly over, on, under, beneath, connected to or coupled to the other element or intervening elements may be present. In contrast, when an element of a semiconductor device is referred to as being "directly above," "over," "upper," "lower," "under," "beneath," "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements present. Like reference numerals refer to like elements throughout the present disclosure.

Spatially relative terms, such as "above," "over," "upper," "above," "below," "under," "lower," "left," "right," "lower left," "lower right," "upper left," "upper right," "center," "middle," and the like, may be used herein for ease of description to describe one element's relationship to another element as illustrated. It will be understood that the spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "below" may encompass both an orientation of above and below. The semiconductor device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As another example, when devices or structures comprising these elements are oriented differently, elements referred to as "left" and "right" elements may be "right" and "left" elements. Accordingly, in the following description, a "left" element and a "right" element may also be referred to as a "first" element or a "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" and "upper" may be referred to as "first" and "second" elements, respectively, and are described as necessary to distinguish between the two elements.

It will be understood that, although the terms "1 st", "2 nd", "3 rd", "4 th", "5 th", "6 th", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

As used herein, an expression such as "at least one of … …" modifies the entire list of elements before the list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b and c" is understood to include all of a alone, b alone, c alone, both a and b, both a and c, both b and c, or a, b and c. In this document, when the term "identical" is used to compare the dimensions of two or more elements, the term may cover "substantially identical" dimensions.

It will also be understood that even if a certain step or operation of a manufacturing apparatus or structure is described later than another step or operation, that step or operation may be performed earlier than another step or operation unless another step or operation is described as being performed before that step or operation.

Many embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments (and intermediate structures). Accordingly, variations from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The various regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

For the sake of brevity, conventional elements, structures, or layers of semiconductor devices including nano-sheet transistors and materials forming the same may or may not be described in detail herein. For example, when a certain isolation layer or structure of a semiconductor device is not relevant to the novel features of an embodiment, such layer or structure and the materials forming such layer or structure may be omitted herein.

Hereinafter, various embodiments of the present disclosure will be described with reference to fig. 1A-1D to 35A-35D, wherein fig. 1A-1D to 33A-33D illustrate a process of manufacturing a semiconductor unit including a nanoflake transistor according to an embodiment, wherein a source/drain region having a backside contact plug and a source/drain region having a front side contact plug have the same or substantially the same height or size.

Fig. 1D to 34D are top plan views of the semiconductor unit 10, and fig. 1A-1C to 34A-34C are cross-sectional views of the semiconductor unit 10 taken along lines I-I ', II-II ', and III-III ', respectively, shown in fig. 1D to 34D. It should be understood herein that fig. 1D-34D are provided only to aid in understanding the location of selected structural elements of the nano-sheet transistor including the fin (channel) structure and the dummy gate or gate structure in the semiconductor unit 10 for the sake of brevity, and thus, not all structural elements shown in fig. 1A-1C-34A-34C are shown in fig. 1D-34D.

Fig. 1A to 1D illustrate a semiconductor cell after a dummy gate structure is formed to surround a plurality of channel structures on a substrate.

Referring to fig. 1A to 1D, a first fin structure 110 and a second fin structure 120 may be formed on a substrate 105 and extend in a D1 direction, which is a channel length direction. The first fin structure 110 and the second fin structure 120 may be spaced apart from each other in a D2 direction, which is a channel width direction, by a Shallow Trench Isolation (STI) structure 116. The D1 and D2 directions may intersect each other or may be perpendicular to each other.

In addition, two trenches T1 and T2 may be formed on the substrate 105 to divide the dummy gate structures formed on the first fin structure 110 and the second fin structure 120 into first to third dummy gate structures 151 to 153 extending in the D2 direction, respectively. The two trenches T1 and T2, along with the STI structure 116, may also divide the first fin structure 110 and the second fin structure 120 into first through sixth channel structures CH1 through CH6. Accordingly, the first dummy gate structure 151 may surround the first and fourth channel structures CH1 and CH4, the second dummy gate structure 152 may surround the second and fifth channel structures CH2 and CH5, and the third dummy gate structure 153 may surround the third and sixth channel structures CH3 and CH6.

The dummy gate structures are so called because they will be replaced by Replacement Metal Gate (RMG) structures in a later step in the fabrication of the semiconductor cell 10. For example, the dummy gate structure may be formed of polysilicon (p-Si).

Each of the channel structures CH1 to CH6 may include a plurality of nano-sheets NC on a plurality of sacrificial layers NS, respectively. The nanoplatelet layer NC formed of, for example, silicon (Si) is referred to as a channel layer because when the semiconductor unit 10 is completed to include a plurality of nanoplatelet transistors formed of channel structures CH1 to CH6, they serve as a current path between source/drain regions. The sacrificial layer NS formed of, for example, silicon germanium (SiGe) is so called because after the source/drain regions of the two nano-sheet transistors are formed in the semiconductor unit 10 in a later step, they will be replaced with RMG structures together with the dummy gate structures 151 to 153.

A base diffusion isolation or Bottom Dielectric Isolation (BDI) layer 111 may be formed on the substrate 105 to isolate the substrate 105 from gate structures and source/drain regions to be formed in later steps so that current leakage from these structures may be prevented. The BDI layer 111 may include silicon nitride, silicon carbonitride (SiCN), or silicon boron carbonitride (SiBCN), but is not limited thereto.

In this step of manufacturing the semiconductor unit 10, the gate hard mask structure 160 for forming the dummy gate structures 151 to 153 may remain on each of the dummy gate structures 151 to 153.

Inner spacers 117 may be formed on both sides of each of the sacrificial layers NS in the D1 direction to isolate the sacrificial layers NS from source/drain regions to be formed in a later step. Gate spacers 170 may be formed at both sides of each of the dummy gate structures 151 to 153 to isolate RMG structures from other structural elements in the semiconductor cell 10 that will replace the dummy gate structures 151 to 153 in a later step. The gate spacers 170 may also extend in the D3 direction to form both sides of the gate hard mask structure 160 on each of the dummy gate structures 151 to 153. The D3 direction may be either transverse or perpendicular to the D1 and D2 directions. Further, the etch stop layer 113 may be formed in the substrate 105 at a predetermined level from the bottom surface of the substrate 105.

Fig. 1A through 1D illustrate that the semiconductor cell 10 includes two fin structures divided into six channel structures, each having three channel layers, and three dummy gate structures surrounding the six channel structures. However, these numbers of structural elements are merely examples. Thus, depending on the embodiment, more or less than those numbers of structural elements may form the semiconductor unit 10.

Fig. 2A to 2D illustrate the semiconductor cell after forming a thin protective liner on side surfaces of a plurality of trenches formed between the dummy gate structures.

Referring to fig. 2A, a thin protective pad 121 may be formed on side surfaces of the trenches T1 and T2. The side surface of each of the trenches T1 and T2 may be formed of the side surface of the inner spacer 117, the side surface of the nano-sheet NC, and the side surface of the gate spacer 170, which may be coplanar in the D3 direction. The thin protective liner 121 may be used to protect at least the inner spacer 117, the nanoplatelets NC, and the gate spacer 170 in a subsequent step of forming a plurality of placeholders in the substrate 105 under the two trenches T1 and T2 after removing the BDI layer 111 on the substrate 105. Thus, the thin protective liner 121 may need to be formed of a material that is etch selective to the BDI layer 111 and the substrate 105. The material forming the thin protective pad 121 may include at least one of silicon nitride, silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), other than the material included in the BDI layer 111, but is not limited thereto.

At least one of the above-described placeholders will be formed in the substrate 105 to reserve space for forming backside contact plugs of the BSPDN therein, as will be described later. The backside contact plugs will be connected to the bottom surfaces of the corresponding source/drain regions, which will also be described later. The backside contact plug may refer to a Direct Backside Contact (DBC) structure mentioned in the background section of the present specification. The formation of the thin protective liner 121 may be performed by, for example, atomic Layer Deposition (ALD).

Fig. 3A to 3D illustrate the semiconductor unit after forming a first photoresist and a mask structure on the semiconductor unit obtained in the previous step.

Referring to fig. 3A to 3C, a first photolithography and masking operation may be performed on the semiconductor unit 10. For example, the first photolithography and masking operation may include a tri-layer patterning operation that forms a plurality of photoresist patterns 131 on a silicon-containing anti-reflective coating (SiARC) layer 132 and an Organic Planarization Layer (OPL) 133, and the organic planarization layer 133 may fill in the trenches T1 and T2 and cover the fin structures 110 and 120.

A photoresist pattern 131 may be formed on the SiARC layer 132 and have 1 st to 4 th openings O1 to O4 to expose the SiARC layer 132 over the trenches T1 and T2, through which a spacer structure will be formed in a later step. For brevity, the third opening O3 is not shown in fig. 3A to 3C.

Fig. 4A to 4D illustrate the semiconductor cell after the previously formed trenches between the dummy gate structures are re-exposed based on the first photoresist and the mask structure, and the Base Diffusion Isolation (BDI) layer exposed through the trenches is removed to expose the substrate.

Referring to fig. 4A to 4C, portions of the SiARC layer 132 and the OPL 133 under the first to fourth openings O1 to O4 may be removed based on the photoresist pattern 131 by, for example, dry etching and/or wet etching. At this time, the BDI layer 111 exposed through the trenches T1 and T2 from which the OPL 133 is removed may also be removed.

Fig. 5A to 5D illustrate the semiconductor unit after a portion of the substrate exposed by the removed BDI layer 111 is recessed to form a plurality of grooves in the substrate.

Referring to fig. 5A to 5C, first to fourth grooves R1 to R4 may be formed in the substrate 105 to provide a space for forming a spacer structure in a later step. These recesses R1 to R4 may be formed in the substrate 105 below the level of the BDI layer 111 (now removed). The formation of the grooves R1 to R4 may be performed by, for example, dry etching, but is not limited thereto.

According to an embodiment, the grooves R1 to R4 may have a depth from the top surface of the substrate 105 to a level above a predetermined level at which the etch stop layer 113 is formed.

Fig. 6A to 6D illustrate the semiconductor unit after a portion of the first photoresist and the mask structure for forming grooves in the substrate is removed and the grooves are modified to have a first predetermined shape having a positive slope.

Referring to fig. 6A and 6C, the OPL 133 for forming the first to fourth recesses R1 to R4 may be removed by, for example, an ashing operation to expose the gate hard mask structure 160. Further, additional etching may be performed on the first to fourth grooves R1 to R4 so that the grooves may have a first predetermined shape having at least a positive slope portion. For example, the grooves R1 to R4 after the additional etching may take the form of hexagons (or trapezoids) in a sectional view (fig. 6A) in the channel length direction, and they may take the form of rectangles in a sectional view (fig. 6C) in the channel width direction. As another example, the grooves R1 to R4 after the additional etching may take the form of a first predetermined shape in at least one of a cross-sectional view in the channel width direction and a cross-sectional view in the channel length direction. According to an embodiment, the additional etching performed in this step may include sigma etching.

The hexagonal (or trapezoidal) shape has a positive slope, and thus, the upper width W1 of each of the grooves R1 to R4 is smaller than the lower width W2 thereof. By forming the grooves R1 to R4 in such a shape, formation of backside contact plugs therein in the substrate 105 will be facilitated, as will be described later.

Fig. 7A to 7D illustrate a semiconductor cell after a plurality of placeholder structures including a dummy placeholder structure are filled in a recess formed in a substrate.

Referring to fig. 7A and 7C, the first to fourth spacer structures P1 to P4 may be formed in the first to fourth grooves R1 to R4, respectively, by, for example, chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or a combination thereof, but are not limited thereto.

As will be described later, the second and third placeholder structures P2, P3 may be formed to provide respective spaces for forming back-side contact plugs connected to bottom surfaces of corresponding source/drain regions in the semiconductor unit 10 in a later step. In contrast, the first and fourth placeholder structures P1, P4 may be used to facilitate formation of source/drain regions having the same or substantially the same height or size as corresponding source/drain regions, which may then be replaced by an interlayer dielectric (ILD) structure in a later step. Thus, the first and fourth placeholder structures P1, P4 may be referred to herein as dummy or sacrificial placeholder structures.

The spacer structures P1 to P4 may be formed of, for example, silicon germanium (SiGe), but are not limited thereto.

Fig. 8A to 8D illustrate the semiconductor unit after forming a barrier layer on the top surface of each of the placeholder structures in the substrate.

Referring to fig. 8A and 8C, a barrier layer 181 may be formed on a top surface of each of the first to fourth placeholder structures P1 to P4 in the substrate 105. The barrier layer 181 may be formed by, for example, epitaxial growth of silicon (Si) from the placeholders P1 to P4 or by Atomic Layer Deposition (ALD) of a dielectric material such as silicon oxide or silicon nitride, but is not limited thereto.

As will be described later, the barrier layer 181 may serve at least to prevent loss of an epitaxial structure formed thereabove, which forms source/drain regions, when the placeholder structure therebelow is removed in a later step. In addition, the barrier layer 181 may be used to protect the placeholder structures P1 to P4 when the thin protective liner 121 is removed in a next step.

Fig. 9A to 9D illustrate the semiconductor unit after removing the thin protective liner formed in the trench.

Referring to fig. 9A, the thin protective liner 121 formed at the side surfaces of the trenches T1 and T2 may be removed by, for example, atomic Layer Etching (ALE). By removing the thin protective pad 121, the side surfaces of the nano-sheet NC, the side surfaces of the inner spacers 117, and the side surfaces of the gate spacers 170 may be exposed again through the trenches T1 and T2.

Fig. 10A to 10D illustrate the semiconductor cell after forming source/drain regions for two nanoflake transistors.

Referring to fig. 10A and 10C, the first to fourth source/drain regions SD1 to SD4 may be epitaxially grown based on the first to sixth channel structures CH1 to CH6 and the barrier layer 181, with a corresponding spacer structure under the barrier layer 181.

According to an embodiment, each of the first to fourth source/drain regions SD1 to SD4 may be a P-type source/drain region including silicon germanium (SiGe), which may be the same material as that forming the placeholder structures P1 to P4. The p-type source/drain region may be doped with p-type impurities such as boron (B), gallium (Ga), etc.

Since each of the first to fourth source/drain regions SD1 to SD4 is formed based on the same structural element (i.e., two channel structures on both sides of the source/drain region and the barrier layer 181 having a corresponding spacer structure thereunder), the first to fourth source/drain regions SD1 to SD4 may have the same or substantially the same height or size, and furthermore, top surfaces of the first to fourth source/drain regions SD1 to SD4 may be at substantially the same level. According to an embodiment, the first to fourth source/drain regions SD1 to SD4 may have the same or substantially the same height or size in at least one of a cross-sectional view in the channel width direction and a cross-sectional view in the channel length direction.

Accordingly, the first nano-sheet transistor TR1 including the first and second source/drain regions SD1 and SD2 and the second nano-sheet transistor TR2 including the third and fourth source/drain regions SD3 and SD4 completed in the semiconductor unit 10 in a later step may have stable and uniform device performance.

As previously described with reference to fig. 7A-7D and as will be further described, the second and third source/drain regions SD2 and SD3 will be connected to backside contact plugs, which will replace the placeholder structures P2 and P3, while the first and fourth source/drain regions SD1 and SD4 may be connected to front side contact plugs in a later step. Accordingly, when the semiconductor unit 10 is formed by the related art method, only the placeholder structures P2 and P3 may be formed to provide space for the backside contact plugs for the second and third source/drain regions SD2 and SD 3. In this case, the dimensions or heights of the second and third source/drain regions SD2 and SD3 formed on the spacer structures P2 and P3 having the barrier layer 181 may be different from those of the first and fourth source/drain regions SD1 and SD4 formed on the substrate 105 without the spacer structures P1 and P4 having the barrier layer 181 thereon. However, in the present embodiment, the spacer structures P1 and P4 having the barrier layer 181 may also be formed in the substrate 105, so that the first and fourth source/drain regions SD1 and SD4 may be formed based on the same conditions as the second and third source/drain regions (i.e., based on the same spacer structure having the barrier layer thereon). Thus, embodiments may enable the formation of the same or substantially the same size source/drain regions for the first and second nanoflake transistors TR1 and TR2, the first and second nanoflake transistors TR1 and TR2 having both backside contact plugs and front side contact plugs for their source/drain regions.

Fig. 11A-11D illustrate the semiconductor cell after a first interlayer dielectric (ILD) structure is formed thereon and the gate hard mask structure is removed to expose the dummy gate structure formed thereunder.

Referring to fig. 11A through 11C, a first ILD structure 171 may be formed to isolate the first through fourth source/drain regions SD1 through SD4 from each other and from other structural elements in the semiconductor unit 10. Formation of the first ILD structure 171 may be performed by, for example, CVD, PECVD, PVD, ALD or a combination thereof, and then an ashing or planarization operation, such as Chemical Mechanical Polishing (CMP), is performed to remove the gate hard mask structure 160, thereby exposing the dummy gate structures 151 through 153 upward.

The material forming the first ILD structure 171 may be a low-k material such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like. Here, it should be understood that the additional ILD structures 172 to 177 to be formed in the semiconductor unit 10 in a later step may also be formed of the same low-k material or a different low-k material forming the first ILD structure 171.

Fig. 12A to 12D illustrate the semiconductor cell after removing the dummy gate structure and the sacrificial layer included in the channel structure.

Referring to fig. 12A to 12C, the dummy gate structures 151 to 153 may be removed together with the sacrificial layers NS included in the first to sixth channel structures CH1 to CH 6. The removal operation in this step may include, but is not limited to, isotropic and/or anisotropic Reactive Ion Etching (RIE), wet etching, and/or Chemical Oxide Removal (COR) processes. Accordingly, in the semiconductor unit 10, the nano-sheet layer NC may be released from the sacrificial layer NS to form a plurality of channel layers for the nano-sheet transistors TR1 and TR 2. By this channel release operation, the nanoplatelet NC may be exposed through an open space where a gate structure will be formed in a subsequent step.

Fig. 13A to 13D illustrate the semiconductor cell after a plurality of gate structures replace the dummy gate structure and the sacrificial layer in the channel structure.

Referring to fig. 13A and 13B, first to third Replacement Metal Gate (RMG) structures 151 'to 153' are formed on spaces where the dummy gate structures 151 to 153 and the sacrificial layer NS are removed in the previous step. Through this replacement operation, the first to third RMG structures 151 'to 153' may surround the first to sixth channel structures CH1 to CH6, respectively, to control the current flowing through the channel structures. RMG structures 151 'through 153' are so called because these structures have replaced dummy gate structures 151 through 153 in semiconductor cell 10.

Each of the RMG structures 151 'to 153' may include a gate dielectric layer, a work function layer, and a gate electrode. The gate dielectric layer may be formed of an oxide material and a high-k material, and the work function layer may be formed of titanium (Ti), tantalum (Ta), or a compound thereof. The gate electrode may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or a compound thereof, but is not limited thereto.

Fig. 14A to 14D illustrate the semiconductor unit after forming a second photoresist and a mask structure on the semiconductor unit obtained in the previous step.

Referring to fig. 14A to 14C, a second photolithography and masking operation may be performed on the semiconductor unit 10. For example, the second photolithography and masking operation may further include a triple patterning operation of forming a plurality of photoresist patterns 231 on the silicon-containing anti-reflective coating (SiARC) layer 232 and the Organic Planarization Layer (OPL) 233.

Here, a photoresist pattern 231 may be formed on the SiARC layer 232 and have a fifth opening O5 exposing the SiARC layer 232 over a location between the first fin structure 110 and the second fin structure 120 where a gate cut structure will be formed in a later step.

Fig. 15A to 15D illustrate the semiconductor unit after opening the second photoresist and the mask structure at a position corresponding to the gate cut structure to be formed in a subsequent step.

Referring to fig. 15A to 15C, the SiARC layer 232 and the OPL 233 are opened to form a sixth opening O6 at a position where a gate cutting structure is to be formed based on the photoresist pattern 231 having the fifth opening O5. The formation of the sixth opening O6 in this step may be performed by dry etching based on the photoresist pattern 231 having the fifth opening O5, for example.

After forming the SiARC layer 232 and the OPL 233 having the sixth opening O6, the photoresist pattern 231 may be removed by, for example, an ashing operation.

Fig. 16A to 16D illustrate the semiconductor cells obtained in the previous step after forming the gate cutting trench therein.

Referring to fig. 16A to 16C, a third trench T3, which is a gate cutting trench, may be formed to divide the semiconductor unit 10 into a first semiconductor unit 10-1 and a second semiconductor unit 10-2. The gate cutting trench T3 may further divide the first to third RMG structures 151 'to 153' into first to third gate structures G1 to G3 in the first semiconductor unit 10-1 and fourth to sixth gate structures G4 to G6 in the second semiconductor unit 10-2.

The formation of the third trench T3 may be performed by dry etching, for example, based on the SiARC layer 232 and OPL 233 having the sixth opening O6 in the semiconductor unit 10 of the previous step. By the gate cutting operation in this step, the first to sixth gate structures G1 to G6 may take the form of surrounding the first to sixth channel structures CH1 to CH6 in the semiconductor unit 10, respectively. Trench T3 may extend down to STI structure 116.

After forming the third trench T3, the SiARC layer 232 may be stripped, leaving the OPL 233 on the semiconductor unit 10.

Fig. 17A to 17D illustrate the semiconductor unit after filling the gate cutting trench with a dielectric material.

Referring to fig. 17A to 17C, the third trench T3 may be filled with a gate cutting structure 180 formed of a dielectric material such as silicon oxide or silicon nitride by, for example, CVD, PVD, PECVD, ALD and combinations thereof, but is not limited thereto.

After forming the gate cutting structure 180 in the third trench T3, the OPL 233 may be removed by, for example, ashing or dry etching operation.

Fig. 18A-18D illustrate the semiconductor cell after a second ILD structure is formed thereon.

Referring to fig. 18A through 18C, a second ILD structure 172 (which may be referred to as an intermediate process (MOL) ILD structure) may be formed on the first semiconductor cell 10-1 and the second semiconductor cell 10-2 by, for example, CVD, PVD, PECVD, ALD and combinations thereof, but is not limited thereto.

Fig. 19A to 19D illustrate the semiconductor unit after a plurality of MOL contact plugs are formed on the source/drain regions and the gate structure.

Referring to fig. 19A through 19C, the first and second ILD structures 171 and 172 may be patterned by, for example, photolithography and masking operations to provide a plurality of openings exposing top surfaces of the first and fourth source/drain regions SD1 and SD4 and top surfaces of the second and fifth gate structures, respectively. Further, these openings may be filled with the first to fourth MOL contact plugs CA1, CB2 and CA2 by, for example, CVD, PVD, PECVD, ALD or a combination thereof, so that the first to fourth MOL contact plugs CA1, CB2 and CA2 may be connected to the top surfaces of the first source/drain region SD1, the second and fifth gate structures G2 and G5 and the fourth source/drain region SD4, respectively.

The first to fourth MOL contact plugs CA1, CB2 and CA2 may be formed of one or more metals or metal compounds, such as copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), and the like.

Fig. 20A to 20D illustrate the semiconductor cell after forming a third ILD structure and a plurality of via structures therein on the semiconductor cell obtained in the previous step.

Referring to fig. 20A to 20C, a third ILD structure 173 may be formed on the second ILD structure 172 having the first to fourth MOL contact plugs CA1, CA2, CB1 and CB2 therein, and the third ILD structure 173 may be patterned to provide a plurality of openings exposing top surfaces of the first to fourth MOL contact plugs CA1, CB2 and CA 2. The openings may be filled with first to fourth via structures V0 to V3 to be connected to top surfaces of the first to fourth MOL contact plugs CA1, CB2, and CA2, respectively.

The third ILD structure 173 and the first to fourth via structures V0 to V3 may be formed by a similar process for forming the second ILD structure 172 and the first to fourth MOL contact plugs CA1, CB2 and CA2 in the previous step. The first to fourth via structures V0 to V3 may include the same or similar materials as those of the first to fourth MOL contact plugs CA1, CB2, and CA 2.

Fig. 21A through 21D illustrate the semiconductor cell after a fourth ILD structure and a plurality of first metal lines are formed therein.

Referring to fig. 21A through 21C, a fourth ILD structure 174 may be formed on the third ILD structure 173 having the first through fourth via structures V0 through V3 therein, and the fourth ILD structure 174 may be patterned to provide a plurality of trenches and/or openings exposing top surfaces of the first through fourth via structures V0 through V3. These trenches and/or openings may be filled with a plurality of first metal lines M1 to be connected to top surfaces of the first to fourth structures V0 to V3, respectively.

The fourth ILD structure 174 and the first metal line M1 may be formed through a similar process for forming the third ILD structure 173 and the first through fourth via structures V0 through V3 in the previous step. The first metal line M1 may include the same or similar material as that of the first to fourth MOL contact plugs CA1, CB2 and CA 2.

Fig. 22A-22D illustrate the semiconductor unit after a plurality of back end of line (BEOL) layers, bonding layers, and carrier wafers are formed on the first metal line.

Referring to fig. 22A-22C, a plurality of BEOL layers M2 may be formed on the first metal line M1 by a similar process used to form the fourth ILD structure 173 and the first metal line M1 in the previous step. Accordingly, the BEOL layer M2 may connect the first and fourth source/drain regions to a voltage source or another circuit element inside or outside the semiconductor unit 10 through the first and fourth MOL contact plugs CA1 and CA 2. BEOL layer M2 may include one or more metal lines and via structures formed at one or more levels.

Simultaneously or subsequently, the carrier wafer 107 may be formed on the BEOL layer M2 with the bonding layer 106 therebetween, for example, CVD, PVD, PECVD, ALD or a combination thereof, but is not limited thereto. The carrier wafer 107 may include a material (e.g., silicon) that forms the substrate 105.

Fig. 23A to 23D illustrate the semiconductor unit after etching the substrate to expose the etch stop layer formed at a predetermined level from the bottom surface of the substrate.

Referring to fig. 23A to 23D, a portion of the substrate 105 may be removed by, for example, dry etching and/or planarization to expose the etch stop layer 113. It should be appreciated herein that dry etching and/or planarization may be excessive, even removing the placeholder structures P1-P4 in the substrate 105, without the presence of the etch stop layer 113 at a predetermined level from the bottom surface of the substrate 105. Accordingly, the etch stop layer 113, which may be formed of aluminum nitride (AlN) or silicon carbon nitride (SiCN) (but is not limited thereto), may prevent such overetching and/or planarization of the substrate 105.

Although not shown in the drawings, the substrate removing operation in the previous step may be performed after the semiconductor unit 10 obtained in the step is inverted based on the carrier wafer 107 to facilitate the immediate removing operation and the subsequent etching/deposition operation.

Fig. 24A to 24D show the semiconductor unit after the etching stop layer is removed.

Referring to fig. 24A to 24D, the etch stop layer 113 may be removed by, for example, wet etching to expose the substrate 105 above the etch stop layer.

Fig. 25A to 25D show the semiconductor unit after the substrate is removed.

Referring to fig. 25A-25C, the entirety of the substrate 105 may be removed, for example, from the backside of the semiconductor unit 10, leaving the placeholder structures P1-P4 with the STI structures 116. When the substrate 105 is removed, the placeholder structures P1 to P4, the STI structure 116, and the BDI layer 111 may be exposed to the outside. The substrate removing operation in this step may be performed by, for example, wet etching, but is not limited thereto.

Fig. 26A-26D illustrate the semiconductor cell after a fifth ILD structure is formed on the backside of the semiconductor cell to enclose the placeholder structure.

Referring to fig. 26A to 26C, a fifth ILD structure 175 may be formed at the back side of the semiconductor cell 10 obtained in the previous step to fill the space created by removing the substrate 105 and enclose therein the placeholder structures P1 to P4. In addition, the fifth ILD structure 175 may be planarized to expose bottom surfaces of the placeholder structures P1 to P4, i.e., top surfaces thereof in a state in which the semiconductor cell 10 is inverted. The fifth ILD structure 175 may be referred to as a backside ILD structure.

The planarization operation in this step may be performed by Chemical Mechanical Polishing (CMP), for example.

Fig. 27A-27D illustrate the semiconductor cell after a backside mask structure is formed at the backside of the semiconductor cell to expose a dummy placeholder structure that is to be removed in a subsequent step.

Referring to fig. 27A to 27C, a backside mask structure 333 may be formed on the backside of the semiconductor unit 10 to expose at least bottom surfaces of the first and fourth placeholder structures P1 and P4, the first and fourth placeholder structures P1 and P4 being formed under first and fourth source/drain regions connected to the first and fourth MOL contact plugs CA1 and CA 2. The backside mask structure 333 may expose the first and fourth placeholder structures P1 and P4 through the seventh and eighth openings O7 and O8, respectively.

As previously described, each of the first and fourth MOL contact plugs CA1 and CA2 is not connected to a back side power supply rail (BPR), but is connected to a BEOL structure at the front side of the semiconductor unit 10.

Fig. 28A-28D illustrate the semiconductor cell after the dummy placeholder structure and the mask structure are removed.

Referring to fig. 28A through 28C, the first and fourth placeholder structures P1 and P4 may be removed by, for example, wet etching for the fifth ILD structure 175 and the backside mask pattern 333.

At this time, according to the embodiment, unlike fig. 28A to 28D, the barrier layers 181 on the first and fourth placeholder structures P1 and P4 and under the first and fourth source/drain regions SD1 and SD4 may also be removed to prevent or reduce unnecessary interference of these barrier layers 181 on other structural elements including the first and fourth source/drain regions SD1 and SD4 or the ILD structure to be formed thereunder. However, even in this embodiment, the blocking layer 181 on the second and third placeholder structures P2 and P3 and under the second and third source/drain regions SD2 and SD3 may not be removed to remain thereon to protect at least the second and third source/drain regions SD2 and SD3 formed thereon in a later step of replacing the second and third placeholder structures P2 and P3 with backside contact plugs.

Fig. 29A-29D illustrate the semiconductor cell after filling the space left by the removal of the dummy placeholder structure with the sixth ILD structure, and the back side of the semiconductor cell is planarized to form a remaining placeholder structure of a second predetermined shape having a positive slope.

Referring to fig. 29A and 29C, the space left by the removal of the first and fourth placeholder structures P1 and P4 may be filled with the sixth ILD structure 176, which is another backside ILD structure, and the backside of the semiconductor cell 10 may be planarized by, for example, a CMP operation, so that the second and third placeholder structures P2 and P3 may take a second predetermined shape, such as a trapezoid having a positive slope, in at least one of a cross-sectional view in the channel length direction and a cross-sectional view in the channel width direction. The planarization operation in this step may be performed to obtain the second and third placeholder structures P2 and P3 having a predetermined shape having a positive slope, so as to deposit backside contact plugs in a space obtained by removing the second and third placeholder structures P2 and P3 in a later step, as will be described later.

Fig. 30A to 30D illustrate the semiconductor unit after the removal of the remaining placeholder structures.

Referring to fig. 30A and 30C, the second and third placeholder structures may be removed by, for example, wet etching for the barrier layer 181 and the fifth and sixth ILD structures 175 and 176 and the STI structure 116. According to an embodiment, the wet etching may selectively remove the second and third spacer structures P2 and P3 formed of silicon germanium (SiGe) without affecting the second and third source/drain regions SD2 and SD3 also formed of silicon germanium (SiGe) through the underlying barrier layer 181 formed of silicon or a dielectric material (silicon oxide or silicon nitride). In other words, the barrier layer 181 may prevent material loss of the second and third source/drain regions SD2 and SD3 when the second and third placeholder structures are removed in this step.

However, unlike in fig. 8A to 8D, when the first to fourth source/drain regions SD1 to SD4 are not formed of silicon germanium (SiGe) but of silicon (Si), the barrier layer 181 may not be formed on the first to fourth placeholder structures P1 to P4, so that the two nano-sheet transistors TR1 and TR2 including the first to fourth source/drain regions SD1 to SD4, respectively, will become n-type field effect transistors. This is because, when the first to fourth placeholder structures P1 to P4 formed of silicon germanium (SiGe) are wet etched, loss of silicon (Si) forming the first to fourth source/drain regions SD1 to SD4 can be avoided or minimized even without the barrier layer 181 due to the etching selectivity between the two materials.

Fig. 31A to 31D illustrate the semiconductor unit after the barrier layer is removed.

Referring to fig. 31A to 31C, the barrier layer 181 formed under the second and third source/drain regions SD2 and SD3 may be removed by, for example, dry etching or wet etching that selectively affects silicon or a dielectric material such as silicon oxide or silicon nitride forming the barrier layer 181 with respect to a material forming the second and third source/drain regions SD2 and SD3, that is, silicon germanium (SiGe). However, according to an embodiment, unlike fig. 31A to 31D, the barrier layer 181 under the second and third source/drain regions SD2 and SD3 may remain as the barrier layer 181 under the first and fourth source/drain regions SD1 and SD4 without being removed, to simplify the manufacturing process and control contact resistance between each of the second and third source/drain regions and the backside contact plug formed thereunder in the next step.

Fig. 32A-32D illustrate the semiconductor cell after formation of a backside contact plug in the space left by removal of the remaining placeholder structure and the barrier layer thereon.

Referring to fig. 32A and 32C, the first and second backside contact plugs BCA1 and BCA2 may be formed in spaces left by removal of the second and third placeholder structures P2 and P3, respectively, and the barrier layer 181 thereon. The formation of the backside contact plugs BCA1 and BCA2 may be performed by, for example, CVD, PVD, PECVD, ALD and combinations thereof, but is not limited thereto. Here, since the spaces left by the removal of the second and third placeholder structures P2 and P3 may have a second predetermined shape, such as a trapezoid having a positive slope, the deposition of the backside contact plugs in these spaces may be completely self-aligned with the predetermined shape when the semiconductor unit 10 is inverted.

The first and second backside contact plugs BCA1 and BCA2 may be connected to bottom surfaces of the second and third source/drain regions SD2 and SD3, respectively. For brevity, the connection of the third source/drain region SD3 to the second backside contact plug BCA2 of the placeholder structure P3 is not shown in fig. 32A to 32C.

Fig. 33A-33D illustrate the semiconductor cell after forming a seventh ILD structure and a backside power rail therein.

Referring to fig. 33A to 33D, a seventh ILD structure 177 and a backside power supply rail BPR may be formed on the backside of the semiconductor cell 10 obtained in the previous step to complete the semiconductor chip 10.

Accordingly, the second source/drain region SD2 forming the first nanoflake transistor TR1 and the third source/drain region SD3 forming the second nanoflake transistor TR2 may be supplied with power through the first and second backside contact plugs BCA1 and BCA2, respectively. Meanwhile, according to the embodiment, the semiconductor chip 10 shown in fig. 33A to 33D may take a slightly different structural form as shown in fig. 34A to 34D and 35A to 35D.

Fig. 34A through 34D illustrate a semiconductor cell according to an embodiment, wherein no barrier layer remains between the source/drain regions and the sixth ILD structure after the semiconductor cell is completed.

As described above with reference to fig. 28A to 28D, according to an embodiment, the barrier layer 181 on the first and fourth placeholder structures P1 and P4 and under the first and fourth source/drain regions SD1 and SD4 may also be removed. Accordingly, in this embodiment as shown in fig. 34A and 34C, in addition to the barrier layer 181 not remaining under each of the second and third source/drain regions SD2 and SD3 connected to the backside contact plugs BCA1 and BCA2, respectively, the barrier layer 181 is not remaining under each of the first and fourth source/drain regions SD1 and SD4 connected to the first and fourth MOL contact plugs CA1 and CA4, respectively. The present embodiment may enable preventing or reducing unnecessary interference of these barrier layers 181 to other structural elements including the first and fourth source/drain regions SD1 and SD4 or the sixth ILD structure formed thereunder.

Fig. 35A-35D illustrate a semiconductor cell according to an embodiment, wherein a barrier layer remains between the source/drain region and the sixth ILD structure and between the source/drain region and the backside contact plug when the semiconductor cell is completed.

As described above with reference to fig. 31A to 31D, according to an embodiment, the barrier layer 181 under the second and third source/drain regions SD2 and SD3 may remain as the barrier layer 181 under the first and fourth source/drain regions SD1 and SD4 without being removed. Accordingly, in this embodiment as shown in fig. 35A and 35C, in addition to the barrier layer 181 remaining under the first and fourth source/drain regions SD1 and SD4 connected to the first and fourth MOL contact plugs CA1 and CA4, respectively, the barrier layer 181 remains under the second and third source/drain regions SD2 and SD3 connected to the first and second backside contact plugs BCA1 and BCA2, respectively. In the present embodiment, a process of manufacturing the semiconductor unit 10 may be simplified, and contact resistance between the second and third source/drain regions and the first and second back side contact plugs may be controlled by the barrier layer 181.

Up to now, a method of manufacturing a semiconductor cell has been described in which the source/drain regions of two nanoflake transistors are connected to a front side contact plug and a back side contact plug, respectively. In the semiconductor unit, the source/drain regions connected to the front-side contact plugs may have the same or substantially the same height or size as the source/drain regions connected to the back-side contact plugs. As an example, a process of manufacturing the semiconductor unit 10 is described, by which the first nanoflake transistor TR1 may be formed to include the first source/drain region SD1 and the second source/drain region SD2 having the same or substantially the same height or size even when the front-side contact plug (i.e., the first MOL contact plug CA 1) is formed on the first source/drain region SD1 and the back-side contact plug (i.e., the first back-side contact plug BCA 1) is formed on the second source/drain region SD2. Further, in the semiconductor unit 10, even when the front side contact plug (i.e., the fourth MOL contact plug CA 2) is formed on the fourth source/drain region SD4 and the back side contact plug (i.e., the second back side contact plug BCA 2) is formed on the third source/drain region SD3, the second nanoflake transistor TR2 may be formed to include the third and fourth source/drain regions SD3 and SD4 having the same or substantially the same height or size. Accordingly, each of the first and second nano-sheet transistors TR1 and TR2 may have stable and uniform device performance. Here, the dimensions of the source/drain regions may refer to the height and width in the channel width direction.

According to this embodiment, the method of manufacturing the semiconductor unit 10 is characterized in that a dummy spacer structure is formed in the substrate, i.e., the first and fourth spacer structures P1 and P4 (dummy spacer structures) for the first and fourth source/drain regions SD1 and SD4 and the second and third spacer structures P2 and P3 for the second and third source/drain regions SD2 and SD3 are formed in the substrate 105 such that the epitaxial growth rate may be the same or substantially the same between the first and second source/drain regions SD1 and SD2 for the first nanoflake transistor TR1 and between the third and fourth source/drain regions SD3 and SD4 for the second nanoflake transistor TR 2.

Otherwise, when the first and fourth spacer structures P1 and P4 (dummy spacer structures) are not formed in the substrate 105 and the second and third spacer structures P2 and P3 are formed in the substrate 105, the first and fourth source/drain regions SD1 and SD4 may be epitaxially grown only from the channel structure, and the second and third source/drain regions SD1 and SD4 may be epitaxially grown not only based on the channel structure but also on the second and third spacer structures P2 and P3 having the barrier layer 181 thereon, and the second and third source/drain regions may have a greater height or size than the first and fourth source/drain regions, as shown in fig. 36A to 36D. Fig. 36A to 36D illustrate a semiconductor unit including two field effect transistors each having two source/drain regions having different heights or sizes according to an embodiment.

Therefore, according to the embodiment, when the nano-sheet transistors having the source/drain regions of different sizes connected to the front-side contact plug and the rear-side contact plug, respectively, are required in the above-described semiconductor unit 10, the first and fourth placeholder structures P1 and P4 may not be formed when the semiconductor unit 10 including the first to fourth nano-sheet transistors TR1 to TR4 is manufactured. In this case, however, each of the first and second nano-sheet transistors TR1 and TR2 may have different device performance due to the different sizes of the source/drain regions.

Meanwhile, the above-described embodiments for manufacturing a semiconductor unit including two nano-sheet transistors are described. However, the present disclosure may not be limited thereto, but may also be applied to semiconductor cells including different types of field effect transistors (such as finfets).

Fig. 37 is a flowchart showing a method of manufacturing a semiconductor device including a field effect transistor according to an embodiment, source/drain regions of the field effect transistor being connected to a front side contact plug and a back side contact plug, respectively.

In operation S110, a field effect transistor structure including a channel structure surrounded by a dummy gate structure may be provided on a substrate.

The channel structure may include multiple nanoplatelets for a nanoplatelet transistor or a vertical fin structure for a FinFET. The channel structure may further include a sacrificial layer formed under or over the nanoplatelets, respectively.

A base diffusion isolation or Bottom Dielectric Isolation (BDI) layer may be formed on the substrate to isolate the substrate from at least the sacrificial layer included in the channel structure. After this operation S110, the semiconductor unit 10 shown in fig. 1A to 1D may be provided.

In operation S120, first and second trenches extending in a channel width direction may be formed to divide a channel structure into first to third channel structures in a channel length direction and to divide a dummy gate structure into first to third dummy gate structures.

When two trenches are formed, the BDI layer formed on the substrate may be exposed through the two trenches as shown in fig. 1A to 1D.

In operation S130, a first groove and a second groove may be formed under the first groove and the second groove in the substrate such that the second channel structure is vertically positioned on a portion of the substrate between the first groove and the second groove. The first groove and the second groove may be formed to have a predetermined shape having a positive slope in this operation, as shown in fig. 6A to 6D.

In operation S140, a first and second placeholder structures may be formed in the first and second grooves, respectively, and then a first and second barrier layer may be formed thereon, respectively, as shown in fig. 8A to 8D.

In operation S150, first and second source/drain regions may be formed on the first and second spacer structures, respectively, for example, by epitaxially growing silicon based on the first and second spacer structures having the first and second barrier layers thereon and at least the second channel structure, as shown in fig. 10A to 10D.

Here, the first source/drain region may also be epitaxially grown from the first channel structure, and the second source/drain region may also be epitaxially grown from the third channel structure.

In operation S160, the first to third dummy gate structures and the sacrificial layers included in the first to third channel structures may be replaced with Replacement Metal Gate (RMG) structures, as shown in fig. 13A to 13D.

In operation S170, a front side contact plug may be formed on the top surface of the first source/drain region, as shown in fig. 19A to 19D.

The front side contact plugs may connect the first source/drain regions to BEOL structures, such as metal lines connected to a voltage source or another circuit element.

In operation S180, the first placeholder structure may be removed from the first groove, as shown in fig. 28A-28D.

According to an embodiment, the first barrier layer may also be removed after the removal of the first placeholder structure.

According to an embodiment, the removing operation and the subsequent operation may be performed by inverting the semiconductor device obtained in the previous operation to facilitate various etching and deposition operations.

After the first source/drain regions are formed using the first placeholder structure and the first barrier layer, both structures may not need to remain in the semiconductor device and thus may be removed from the semiconductor device.

The space left by the removal of the first spacer structure and the first barrier layer may be filled with ILD structures, as shown in fig. 29A-29D.

In operation S190, the second placeholder structure may be removed, and then the second barrier layer thereon may also be removed, as shown in fig. 31A-31D. The second barrier layer may be used to prevent loss of epitaxially grown second source/drain regions when the second spacer structure is removed.

In operation S200, a backside contact plug formed on the bottom surface of the second source/drain region may be formed in the second recess from which the second spacer structure and the second barrier layer are removed, as shown in fig. 34A to 34D.

The backside contact plug may connect the second source/drain region to a backside power rail to implement a BSPDN for the semiconductor device.

Fig. 38 is a schematic block diagram illustrating an electronic device including a field effect transistor having front and rear contact plugs as shown in fig. 33A to 33D, 34A to 34D, 35A to 35D, or 36A to 36D, according to an example embodiment.

Referring to fig. 38, the electronic device 4000 may include at least one application processor 4100, a communication module 4200, a display/touch module 4300, a storage 4400, and a buffer Random Access Memory (RAM) 4500. According to an embodiment, the electronic device 4000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

The application processor 4100 may control the operation of the electronic device 4000. The communication module 4200 is implemented to perform wireless or wired communication with external devices. The display/touch module 4300 is implemented to display data processed by the application processor 4100 and/or receive data through a touch panel. The storage 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a Solid State Drive (SSD), a Universal Flash Storage (UFS) device, or the like. The storage 4400 may perform the caching of the mapping data and the user data as described above.

The buffer RAM 4500 may temporarily store data for the processing operation of the electronic device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), a Low Power Double Data Rate (LPDDR) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, rambus Dynamic Random Access Memory (RDRAM), etc.

Although not shown in fig. 38, the electronic device 4000 may further include at least one sensor, such as an image sensor.

At least one component in the electronic device 4000 may include a field effect transistor, such as the first nanoflake transistor TR1 or the first nanoflake transistor TR2 shown in fig. 33A to 33D, 34A to 34D, 35A to 35D, or 36A to 36D.

The foregoing is illustrative of example embodiments and is not to be construed as limiting the present disclosure. Although a few example embodiments have been described above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the present disclosure.

Claims

1. A field effect transistor structure comprising:

a channel structure;

a first source/drain region and a second source/drain region connected to each other through the channel structure;

A first contact plug on a top surface of the first source/drain region connected to a first voltage source or circuit element through a back-end-of-line (BEOL) structure; and

a second contact plug connected to the first voltage source or another circuit element through a back side power supply rail on a bottom surface of the second source/drain region,

wherein the first source/drain region and the second source/drain region have substantially the same height.

2. The field effect transistor structure of claim 1, further comprising a backside interlayer dielectric structure connected to a bottom surface of the first source/drain region.

3. The field effect transistor structure of claim 2, further comprising a barrier layer between the backside interlayer dielectric structure and the first source/drain region,

wherein the barrier layer comprises silicon or a dielectric material.

4. The field effect transistor structure of claim 3, wherein each of the first and second source/drain regions comprises a p-type impurity.

5. The field effect transistor structure of claim 4, wherein a side surface of the second contact plug has a positive slope such that a width of a top surface of the second contact plug facing the bottom surface of the second source/drain region is less than a width of a bottom surface of the second contact plug facing the backside power rail.

6. The field effect transistor structure of claim 5, wherein no silicon substrate is formed under the first source/drain region and the second source/drain region.

7. The field effect transistor structure of claim 2, wherein each of the first and second source/drain regions comprises a p-type impurity.

8. The field effect transistor structure of claim 2, wherein a side surface of the second contact plug has a positive slope such that a width of a top surface of the second contact plug facing the bottom surface of the second source/drain region is less than a width of a bottom surface of the second contact plug facing the backside power rail.

9. The field effect transistor structure of claim 2, wherein no silicon substrate is formed under the first source/drain region and the second source/drain region.

10. The field effect transistor structure of claim 1, further comprising a barrier layer between the second source/drain region and the second contact plug,

wherein the barrier layer comprises silicon or a dielectric material.

11. The field effect transistor structure of claim 1, wherein the channel structure comprises a plurality of nanoplatelets.

12. A field effect transistor structure comprising:

a channel structure;

wherein the first source/drain region and the second source/drain region have substantially the same size in a cross-sectional view in a channel width direction or a channel length direction, and a top surface of the first source/drain region and a top surface of the second source/drain region are substantially at the same level.

13. The field effect transistor structure of claim 12, further comprising a backside interlayer dielectric structure connected to a bottom surface of the first source/drain region.

14. The field effect transistor structure of claim 13, further comprising a barrier layer between the backside interlayer dielectric structure and the first source/drain region,

Wherein the barrier layer comprises silicon or a dielectric material.

15. The field effect transistor structure of claim 13, wherein each of the first and second source/drain regions comprises a p-type impurity.

16. The field effect transistor structure of claim 13, wherein a side surface of the second contact plug has a positive slope such that a width of a top surface of the second contact plug facing the bottom surface of the second source/drain region is less than a width of a bottom surface of the second contact plug facing the backside power rail.

17. The field effect transistor structure of claim 12, further comprising a barrier layer between the second source/drain region and the second contact plug,

wherein the barrier layer comprises silicon or a dielectric material.

18. A method of manufacturing a semiconductor device comprising a field effect transistor, the method comprising:

forming a channel structure on a substrate;

forming a first recess and a second recess on the substrate such that the channel structure is vertically positioned on a portion of the substrate between the first recess and the second recess;

forming a first and a second placeholder structure in the first and the second recess, respectively;

Forming first and second source/drain regions on the first and second placeholder structures, respectively;

removing the first and second placeholder structures from the first and second grooves; and

a backside contact plug is formed in the second recess from which the second placeholder structure is removed.

19. The method of claim 18, further comprising:

a front side contact plug is formed on a top surface of the first source/drain region.

20. The method of claim 18, further comprising:

forming a first barrier layer and a second barrier layer on the first and second placeholder structures, respectively;

wherein each of the first and second barrier layers comprises silicon or a dielectric material.