CN117790350A - Chemical unsealing method for back surface of subsequent solderable chip - Google Patents
Chemical unsealing method for back surface of subsequent solderable chip Download PDFInfo
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- CN117790350A CN117790350A CN202311831830.4A CN202311831830A CN117790350A CN 117790350 A CN117790350 A CN 117790350A CN 202311831830 A CN202311831830 A CN 202311831830A CN 117790350 A CN117790350 A CN 117790350A
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000000126 substance Substances 0.000 title claims abstract description 30
- 239000013078 crystal Substances 0.000 claims abstract description 70
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 66
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 66
- 239000011888 foil Substances 0.000 claims abstract description 56
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052802 copper Inorganic materials 0.000 claims abstract description 43
- 239000010949 copper Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000000853 adhesive Substances 0.000 claims abstract description 21
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- 239000002344 surface layer Substances 0.000 claims abstract description 13
- 239000005022 packaging material Substances 0.000 claims abstract description 8
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical group CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 28
- 239000010410 layer Substances 0.000 claims description 25
- 238000004806 packaging method and process Methods 0.000 claims description 23
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical group O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 15
- 229910017604 nitric acid Inorganic materials 0.000 claims description 15
- 150000002576 ketones Chemical class 0.000 claims description 13
- 239000002904 solvent Substances 0.000 claims description 13
- 238000002791 soaking Methods 0.000 claims description 9
- 238000009210 therapy by ultrasound Methods 0.000 claims description 9
- 239000012445 acidic reagent Substances 0.000 claims description 8
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- 238000001035 drying Methods 0.000 claims description 4
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- 238000004458 analytical method Methods 0.000 abstract description 25
- 238000005516 engineering process Methods 0.000 abstract description 10
- 238000012360 testing method Methods 0.000 description 18
- 238000000227 grinding Methods 0.000 description 17
- 239000003292 glue Substances 0.000 description 15
- 239000002253 acid Substances 0.000 description 10
- 238000003466 welding Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- 238000004140 cleaning Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 229920000742 Cotton Polymers 0.000 description 7
- 239000003513 alkali Substances 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 7
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229920006222 acrylic ester polymer Polymers 0.000 description 1
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Abstract
The invention provides a chemical unsealing method for the back surface of a subsequent solderable chip. The chemical unsealing method comprises the following steps: determining a target area of a crystal back to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area; removing plastic packaging materials on the surface layer of the frame of the crystal back target area through laser treatment; the chip package body is integrally wrapped by using an aluminum foil tape; removing the aluminum foil tape wrapped in the target area by cutting to obtain a sample to be corroded; and sequentially removing the copper substrate, the aluminum foil tape and the patch adhesive from the sample to be corroded by a chemical method to obtain the subsequent solderable chip. The invention adopts the technology of chemically unsealing the wafer back, effectively protects the integrity of the package main body frame and the chip pins, and solves the problem of hot spot positioning analysis that the wafer back cannot be welded on the PCB after the back is unsealed.
Description
Technical Field
The invention relates to the technical field of back surface unsealing of chips, in particular to a subsequent chemical unsealing method for the back surface of a weldable chip.
Background
With the development of chip technology, the integration level of the chip is higher and higher, the level of the chip is more and more, and the specific position of failure is difficult to accurately find due to the shielding of the metal on the front side of the chip in the FA failure positioning process, so that a researcher cannot improve the chip, the back side of the chip is unsealed, the position of the chip failure is found on the back side of the chip more quickly and accurately, the time period of failure analysis is also greatly shortened, and most of the current failure analysis needs to be performed by welding the chip on a PCB (the PCB is a carrier board carrying various chips).
At present, a packaging structure of a physical back surface unsealing chip of a failure analysis laboratory can be damaged, so that the chip cannot be welded on a board later, and back surface hot spot analysis cannot be performed.
In the prior art, a physical method is adopted to grind and unseal the chip wafer back, sand paper is used to grind the package body until the chip wafer back is exposed, the grinding can lead to the chip not to keep a basic frame structure and welding metal pins outside the chip, the chip cannot be welded on a PCB (printed circuit board) again, and a failure sample cannot be subjected to positioning analysis by a band plate. Physical stress is also introduced during the lapping process, risking chip damage.
As CN110618004a, a back unsealing method of a semiconductor device is disclosed, comprising the steps of: laser unsealing: processing the back of the semiconductor device by using laser to remove the die-sealing body at the back of the semiconductor device until the lead frame encapsulated in the semiconductor device is exposed; acid reaction step: removing the lead frame by nitric acid with the concentration of a first preset value; a first grinding step: grinding the chip by adopting sand paper with the granularity number of a second preset value to thin the silicon substrate in the chip to a preset height; a first cleaning step: and cleaning the back of the thinned chip by adopting clear water or alcohol. In the method, the chip cannot retain a basic frame structure and welding metal pins outside the chip in the acid reaction step and the grinding step, and the chip cannot be welded on the PCB again.
In view of this, the present invention has been made.
Disclosure of Invention
One of the purposes of the present invention is to provide a method for chemical unsealing of the backside of a subsequent solderable chip. The invention adopts the technology of chemically unsealing the wafer back, effectively protects the integrity of the package main body frame and the chip pins, solves the problem of hot spot positioning analysis that the package main body frame cannot be welded on the PCB after the back is unsealed, reduces the introduction of physical stress to a greater extent in the process of unsealing the wafer back, and ensures the effectiveness in the process of unsealing the wafer back.
In order to achieve the above object of the present invention, the following technical solutions are specifically adopted:
in a first aspect, the present invention provides a method of chemical unsealing of a backside of a subsequently solderable die, the method comprising the steps of:
determining a target area of a crystal back to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area;
removing plastic packaging materials on the surface layer of the frame of the crystal back target area through laser treatment;
the chip package body is integrally wrapped by using an aluminum foil tape;
removing the aluminum foil tape wrapped in the target area by cutting to obtain a sample to be corroded;
and sequentially removing the copper substrate, the aluminum foil tape and the patch adhesive from the sample to be corroded by a chemical method to obtain the subsequent solderable chip.
In the invention, the technology of chemically unsealing the wafer back is adopted, the integrity of the package main body frame and the chip pins are effectively protected, the problem of hot spot positioning analysis that the package main body frame cannot be welded on a PCB after back opening is solved, the introduction of physical stress is reduced to a greater extent in the process of unsealing the wafer back, and the effectiveness of the process of unsealing the wafer back is ensured.
As a preferred embodiment of the invention, the device used for determining the position of the copper substrate where the crystal grain is located in the chip package is an X-ray device.
Preferably, the back of the crystal target area that needs to unseal is the area between the position of the copper substrate that the crystal grain is located on and the edge of the external packaging body.
In the preparation process of the sample to be corroded, the first step is to determine the position of the copper substrate where the crystal grains in the chip package body are located through X-ray equipment so as to determine a target area of the crystal back which needs to be unsealed, and record the target area.
It should be noted that the whole packaging condition is observed by using the X-ray equipment, the positions of the copper substrate where the crystal grains are positioned and the patch positions of the crystal grains in the packaging body are mainly observed, the distances between the upper part, the lower part, the left part and the right part of the crystal grains and the edge of the external packaging body are measured by using the measuring software of the X-ray equipment, and recorded, so that the accurate back position of the crystal needing to be unsealed can be measured again according to the upper part, the lower part, the left part and the right part which are measured on the X-ray equipment by using the software picture frame function of the laser machine when the plastic package material at the position where the crystal grains are positioned is removed later.
In the preparation process of the sample to be corroded, the second step is to remove the plastic package material on the surface layer of the frame of the crystal back target area through laser treatment, namely, the experimental sample can be placed on a carrying table of a laser area of a laser machine in parallel, and the laser machine is used for carrying out laser removal on the black plastic package material on the surface layer of the frame of the target area observed and measured by the original X-ray equipment.
It should be noted that since the frame is metallic copper and the thickness of the frame is 100-150 μm, the laser process can stop the laser by only observing the exposed frame on the display screen of the laser machine.
Preferably, the power of the laser processing is 10 to 20W, for example, 10W, 11W, 12W, 13W, 14W, 15W, 16W, 17W, 18W, 19W, 20W, etc.
Preferably, the frequency of the laser treatment is 30-35 kHz, and can be 30kHz, 31kHz, 32kHz, 33kHz, 34kHz, 35kHz, and the like.
Preferably, the laser pulse width of the laser treatment is 80-120, for example 80, 85, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 115, 120, etc.
Preferably, the laser speed of the laser treatment is 700-900 mm/s, for example, 700mm/s, 720mm/s, 740mm/s, 760mm/s, 780mm/s, 800mm/s, 820mm/s, 840mm/s, 860mm/s, 880mm/s, 900mm/s, etc.
Preferably, the ratio of the area of the laser treatment to the area of the chip is (1-1.1): 1, for example, 1:1, 1.02:1, 1.04:1, 1.06:1, 1.08:1, 1.1:1, etc.
It should be noted that the ratio of the laser processed area to the chip area is (1-1.1): 1, because the laser area can be larger than the actual position of the chip, the laser area needs to be controlled within 10% of the chip area in order to ensure that the complete wafer back can be completely opened but more frames cannot be damaged, the laser area needs to cover the chip area, and the laser process cannot damage the chip.
In the preparation process of the sample to be corroded, the third step is to use an aluminum foil tape to integrally wrap the chip package.
It should be noted that the chip package is of a hexahedral structure, and preferably the package is wrapped by an acid and alkali resistant aluminum foil tape. And the process of wrapping the package body needs to ensure that the aluminum foil tape is completely adhered to the sample, for example, a cotton swab is used for lightly pressing the aluminum foil tape to completely adhere the adhesive tape to the sample.
Preferably, the aluminum foil tape comprises an aluminum layer and a glue material layer.
The thickness of the aluminum layer is preferably 120 to 130. Mu.m, and may be 120 μm, 121 μm, 122 μm, 123 μm, 124 μm, 125 μm, 126 μm, 127 μm, 128 μm, 129 μm, 130 μm, or the like, for example.
Preferably, the thickness of the adhesive material layer is 20 to 30 μm, and may be, for example, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, 26 μm, 27 μm, 28 μm, 29 μm, 30 μm, or the like.
Preferably, the material of the adhesive material layer comprises acrylic ester and/or acrylic ester copolymer.
In the preparation process of the sample to be corroded, the fourth step is to remove the aluminum foil tape wrapped in the target area through cutting, and the sample to be corroded is obtained.
It should be noted that the aluminum foil tape at the target position of the wafer back of the chip after bonding is cut off, and the edge of the black glue of the laser window is required during cutting, and whether the colloid of the aluminum foil tape at the cut surface of the cut target area is tightly combined with the edge of the groove after the laser of the target can be observed under a microscope, so that the aluminum foil tape is ensured to be fully bonded with the packaging body (except the target area of the laser groove), and the area to be protected is prevented from being corroded during subsequent acid corrosion of the target frame.
As a preferable technical scheme of the invention, the copper substrate removing method specifically comprises the following steps:
and (3) dripping an acid reagent into the position of the copper substrate of the sample to be corroded until the copper substrate is completely corroded, and exposing the adhesive tape.
Preferably, the acid reagent is a nitric acid solution.
Preferably, the mass percentage of the nitric acid solution is 65-70%, for example, 65%, 66%, 67%, 68%, 69%, 70%, etc.
The temperature of the nitric acid solution is preferably 145 to 155 ℃, and may be 145 ℃, 146 ℃, 147 ℃, 148 ℃, 149 ℃, 150 ℃, 151 ℃, 152 ℃, 153 ℃, 154 ℃, 155 ℃, or the like, for example.
Preferably, the aluminum foil removing adhesive tape specifically comprises the following steps:
and (3) soaking the chip sample with the copper substrate removed in a ketone solvent, and then tearing off all the aluminum foil adhesive tapes which are used for integrally wrapping the chip package.
Preferably, the ketone solvent is acetone.
Preferably, the soaking temperature is 20 to 40 ℃, for example, 20 ℃, 22 ℃, 24 ℃, 26 ℃, 28 ℃, 30 ℃, 32 ℃, 34 ℃, 36 ℃, 38 ℃, 40 ℃ and the like, and the soaking time is 1 to 2 minutes, for example, 1min, 1.2min, 1.4min, 1.6min, 1.8min, 2min and the like.
Preferably, the removing the patch adhesive specifically includes the following steps:
firstly dipping a ketone solvent to wipe off the surface mount adhesive on the back surface of the crystal grain until the back surface of the complete crystal grain is exposed; and placing the chip in a ketone solvent, performing ultrasonic treatment, and drying to obtain the subsequent solderable chip.
Preferably, the ketone solvent is acetone.
Preferably, the power of the ultrasonic treatment is 40 to 45W, for example, 40W, 41W, 42W, 43W, 44W, 45W, etc., the temperature of the ultrasonic treatment is 20 to 30 ℃, for example, 20 ℃, 22 ℃, 24 ℃, 26 ℃, 28 ℃, 30 ℃, etc., and the time of the ultrasonic treatment is 10 to 30s, for example, 10s, 12s, 14s, 16s, 18s, 20s, 22s, 24s, 26s, 28s, 30s, etc.
As a preferable embodiment of the present invention, the chemical unsealing method includes the steps of:
s1, determining a crystal back target area needing to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area;
s2, removing plastic packaging materials on the surface layer of the frame of the crystal back target area through laser treatment;
s3, integrally wrapping the chip package body by using an aluminum foil tape, and removing the aluminum foil tape wrapped in the target area by cutting to obtain a sample to be corroded;
s4, dripping an acid reagent into the position of the copper substrate of the sample to be corroded until the copper substrate is completely corroded, and exposing the adhesive tape;
s5, soaking the chip sample with the copper substrate removed in a ketone solvent, and then tearing off all the aluminum foil adhesive tapes which are used for integrally wrapping the chip package;
s6, firstly dipping a ketone solvent to wipe off the surface mount adhesive on the back surface of the crystal grain until the back surface of the complete crystal grain is exposed; and placing the chip in a ketone solvent, performing ultrasonic treatment, and drying to obtain the subsequent solderable chip.
Further, the invention provides a chemical unsealing method for the back surface of a subsequent solderable chip, which specifically comprises the following steps:
s1, determining a crystal back target area needing to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area; the back of crystal target area that needs unsealing is the area between the copper substrate position of the crystal grain and the edge of the external packaging body;
specifically, the position of the copper substrate where the crystal grain is located is observed by using an X-ray device, the red frame area is the patch position of the crystal grain in the package body, the distance between the upper part, the lower part, the left part and the right part of the crystal grain and the edge of the external package body is measured by using measurement software of the X-ray device, and recorded, so that the accurate back position of the crystal grain to be unsealed can be measured again according to the upper part, the lower part, the left part and the right part, which are measured on the X-ray device, by using a software frame function of the laser machine when the plastic package material at the position where the crystal grain is located is removed later.
S2, removing plastic packaging materials on the surface layer of the frame of the crystal back target area through laser treatment;
specifically, placing an experimental sample in parallel on a carrying table of a laser area of a laser machine, and carrying out laser removal on a black plastic package material on a frame surface layer of a target area measured by initial X-ray observation by using laser parameters of 70% of power, 14W of electric power, 33kHz of frequency, 100 laser pulse width and 800mm/s of laser parameters of a Smart Etch II laser machine produced by Suzhou Fu as technology; the laser process only needs to observe the exposed frame on the display screen of the laser machine to stop laser; the ratio of the laser treatment area to the chip area is 1.1:1.
S3, firstly, integrally wrapping the chip package body by using an aluminum foil tape, and then cutting to remove the aluminum foil tape wrapped in the target area to obtain a sample to be corroded;
the aluminum foil tape comprises an aluminum layer and a glue material layer, wherein the thickness of the aluminum layer is 120-130 mu m, the thickness of the glue material layer is 20-30 mu m, and the glue material layer is made of acrylic ester and/or acrylic ester copolymer;
specifically, six sides of the acid and alkali resistant aluminum foil tape are used for wrapping the packaging body, and a cotton swab is required to lightly press the aluminum foil tape in the packaging body wrapping process so that the tape and a sample are completely adhered; and cutting off the aluminum foil tape at the target position of the chip crystal back after bonding by using an art designer knife, and observing whether the colloid of the aluminum foil tape at the notch surface of the cut target area is tightly combined with the edge of the target laser groove or not under a microscope along the black glue edge of the laser window when cutting, so as to ensure that the aluminum foil tape is completely bonded with the packaging body.
S4, heating the 65-70% nitric acid solution to 150 ℃ by using a heating device, dripping the heated nitric acid reagent into the laser groove by using a dropper, and repeatedly treating until the copper frame which is partially exposed is corroded to clean and expose the adhesive.
S5, soaking the sample for 1-2 min at 20-30 ℃ by using acetone, and slowly tearing off the acid and alkali resistant aluminum foil tape wrapping the surface of the packaging body to take out the complete packaging body.
S6, dipping an acetone reagent by using a purified cotton swab, wiping off the surface mount adhesive on the back surface of the crystal grain under a low power microscope to expose the whole back surface of the crystal grain, putting the chip into a plastic cup, adding acetone, ultrasonically cleaning for 20S at the temperature of 20-30 ℃ and the power of 40-45W, and naturally airing to obtain the subsequent weldable chip.
In a second aspect, the present invention provides a subsequent solderable die treated by the chemical unsealing method as described in the first aspect.
It should be noted that the chip obtained by the chemical unsealing method of the present invention still has a complete frame for protecting the package body and chip leads.
In a third aspect, the present invention provides a failure analysis positioning analysis method, which specifically includes the following steps:
and (3) welding the chip obtained by the chemical unsealing method in the first aspect on a PCB (printed circuit board) with holes at the positions of the back of the chip, and carrying out subsequent failure analysis and positioning.
Further, the subsequent failure analysis positioning specifically includes: optical microscopy and/or electrical testing.
As a preferable technical scheme of the invention, the failure analysis positioning analysis method comprises the following steps:
s1, welding the chip obtained by the processing of the embodiment 2 on a PCB with holes at the back of the wafer, and carrying out subsequent failure analysis and positioning.
S2, cleaning the sample and observing the sample by an optical microscope.
S3, performing an electrical test on the sample; the test condition of the electrical test is that the customer tests according to the product specification and the passage to be tested.
Compared with the prior art, the invention has the following beneficial effects:
the invention adopts the technology of chemically unsealing the wafer back, effectively protects the integrity of the package main body frame and the chip pins, and solves the problem of hot spot positioning analysis that the wafer back cannot be welded on the PCB after the back is unsealed. The introduction of physical stress is reduced to a greater extent in the process of unsealing the wafer back, so that the effectiveness of the process of unsealing the wafer back is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for chemical unsealing of the backside of a subsequent solderable die according to the present invention.
Fig. 2 is a schematic structural diagram of a chip package according to the present invention.
Wherein, 1 is the encapsulation material, 2 is the crystal grain, 3 is the paster glue, 4 is the copper substrate, 5 is the outer pin, 6 is the bonding wire.
Fig. 3 is a schematic diagram of the process of processing a sample of an actual chip by the chemical unsealing method for the back surface of the subsequent solderable chip provided in example 1.
Fig. 4 is a schematic diagram of the process of processing a sample of an actual chip by the chemical unsealing method for the back surface of the subsequent solderable chip provided in example 2.
Fig. 5 is a graph showing the result of the abrasion method provided in comparative example 1 that the basic frame cannot be maintained after unsealing.
Fig. 6 is a graph showing the result of the abrasion method provided in comparative example 2 that the basic frame cannot be maintained after unsealing.
Fig. 7 is a view of the observation result of the optical microscope provided in application example 1.
Fig. 8 is a graph of electrical test results provided in application example 1.
Fig. 9 is a view of the observation result of the optical microscope provided in application example 2.
Fig. 10 is a graph of electrical test results provided in application example 2.
Detailed Description
Unless defined otherwise herein, scientific and technical terms used in connection with the present invention shall have the meanings commonly understood by one of ordinary skill in the art. The meaning and scope of terms should be clear, however, in the event of any potential ambiguity, the definitions provided herein take precedence over any dictionary or extraneous definition. In this application, the use of "or" means "and/or" unless stated otherwise. Furthermore, the use of the term "include" and other forms is not limiting.
It is noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than those herein described, and those skilled in the art may readily devise numerous other arrangements that do not depart from the spirit of the invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.
Fig. 1 is a flow chart of a method for chemical unsealing of the backside of a subsequent solderable die according to the present invention. As shown in fig. 1, the chemical unsealing method includes the steps of: determining a target area of a crystal back to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area; removing plastic packaging materials on the surface layer of the frame of the crystal back target area through laser treatment; the chip package body is integrally wrapped by using an aluminum foil tape; removing the aluminum foil tape wrapped in the target area by cutting to obtain a sample to be corroded; and sequentially removing the copper substrate, the aluminum foil tape and the patch adhesive from the sample to be corroded by a chemical method to obtain the subsequent solderable chip.
Fig. 2 is a schematic structural diagram of a chip package according to the present invention. As shown in fig. 2, a copper substrate 4 is placed in the center of the main body frame of the chip package, a chip adhesive 3 is disposed on the copper substrate 4, and a die 2 of a semiconductor wafer is disposed on the chip adhesive 3; the chip package further comprises a plurality of outer pins 5 connected with the main body frame, and the outer pins 5 are connected with the die 2 through bonding wires 6; and the body frame is encapsulated by an encapsulation 1.
The invention is further illustrated by the following examples. The materials in the examples were prepared according to the existing methods or were directly commercially available unless otherwise specified.
Example 1
The embodiment provides a chemical unsealing method for the back surface of a subsequent solderable chip, which specifically comprises the following steps:
s1, determining a crystal back target area needing to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area; the back target area to be unsealed is an area between the copper substrate where the die is located and the edge of the external package (as shown in fig. 3-a, an area sandwiched between two red frames, i.e. a patch position of the die inside the package);
specifically, the position of the copper substrate where the crystal grain is located is observed by using an X-ray device, the red frame area is the patch position of the crystal grain in the package body, the distance between the upper part, the lower part, the left part and the right part of the crystal grain and the edge of the external package body is measured by using measurement software of the X-ray device, and recorded, so that the accurate back position of the crystal grain to be unsealed can be measured again according to the upper part, the lower part, the left part and the right part, which are measured on the X-ray device, by using a software frame function of the laser machine when the plastic package material at the position where the crystal grain is located is removed later.
S2, removing plastic packaging materials on the surface layer of the frame of the wafer back target area through laser treatment (shown in a figure 3-B);
specifically, placing an experimental sample in parallel on a carrying table of a laser area of a laser machine, and carrying out laser removal on a black plastic package material on a frame surface layer of a target area measured by initial X-ray observation by using laser parameters of 70% power, 14W electric power, 33kHz frequency, laser pulse width 100 and laser speed 800mm/s for a Smart Etch II laser machine produced by Suzhou Fu as technology; the laser process only needs to observe the exposed frame on the display screen of the laser machine to stop laser; the ratio of the laser treatment area to the chip area is 1.1:1.
S3, firstly, integrally wrapping the chip package body by using an aluminum foil tape, and then cutting to remove the aluminum foil tape wrapped in the target area to obtain a sample to be corroded (shown in fig. 3-C);
the aluminum foil tape comprises an aluminum layer and a glue material layer, wherein the thickness of the aluminum layer is 120 mu m, the thickness of the glue material layer is 20 mu m, and the glue material layer is made of acrylic ester;
specifically, six sides of the acid and alkali resistant aluminum foil tape are used for wrapping the packaging body, and a cotton swab is required to lightly press the aluminum foil tape in the packaging body wrapping process so that the tape and a sample are completely adhered; and cutting off the aluminum foil tape at the target position of the chip crystal back after bonding by using an art designer knife, and observing whether the colloid of the aluminum foil tape at the notch surface of the cut target area is tightly combined with the edge of the target laser groove or not under a microscope along the black glue edge of the laser window when cutting, so as to ensure that the aluminum foil tape is completely bonded with the packaging body.
And S4, heating the 65wt% nitric acid solution to 150 ℃ by using a heating device, dripping the heated nitric acid reagent into the laser groove by using a dropper, and repeatedly treating until the copper frame which is partially exposed is corroded to clean and expose the surface mount adhesive.
S5, atRoom temperatureAfter the sample is soaked in acetone for 1min, the acid and alkali resistant aluminum foil tape wrapping the surface of the packaging body is slowly torn off, and the complete packaging body is taken out (as shown in fig. 3-D).
S6, firstly dipping an acetone reagent by using a purified cotton swab, wiping off the surface mount adhesive on the back surface of the crystal grain under a low power microscope to expose the whole back surface of the crystal grain, putting the chip into a plastic cup, adding acetone, and putting the chip into a plastic cupRoom temperatureAnd (3) ultrasonic cleaning for 20s under the power of 40W, and naturally airing to obtain a subsequent solderable chip (shown in fig. 3-E).
Example 2
The embodiment provides a chemical unsealing method for the back surface of a subsequent solderable chip, which specifically comprises the following steps:
s1, determining a crystal back target area needing to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area; the back target area to be unsealed is an area between the copper substrate where the die is located and the edge of the external package (as shown in fig. 4-a, an area sandwiched between two red frames, i.e. a patch position of the die inside the package);
specifically, the position of the copper substrate where the crystal grain is located is observed by using an X-ray device, the red frame area is the patch position of the crystal grain in the package body, the distance between the upper part, the lower part, the left part and the right part of the crystal grain and the edge of the external package body is measured by using measurement software of the X-ray device, and recorded, so that the accurate back position of the crystal grain to be unsealed can be measured again according to the upper part, the lower part, the left part and the right part, which are measured on the X-ray device, by using a software frame function of the laser machine when the plastic package material at the position where the crystal grain is located is removed later.
S2, removing plastic packaging materials on the surface layer of the frame of the wafer back target area through laser treatment (shown in fig. 4-B);
specifically, placing an experimental sample in parallel on a carrying table of a laser area of a laser machine, and carrying out laser removal on a black plastic package material on a frame surface layer of a target area measured by initial X-ray observation by using laser parameters of 70% power, 14W electric power, 33kHz frequency, laser pulse width 100 and laser speed 800mm/s for a Smart Etch II laser machine produced by Suzhou Fu as technology; the laser process only needs to observe the exposed frame on the display screen of the laser machine to stop laser; the ratio of the laser treatment area to the chip area is 1.05:1.
S3, firstly, integrally wrapping the chip package body by using an aluminum foil tape, and then cutting to remove the aluminum foil tape wrapped in the target area to obtain a sample to be corroded (shown in fig. 4-C);
the aluminum foil tape comprises an aluminum layer and a glue material layer, wherein the thickness of the aluminum layer is 130 mu m, the thickness of the glue material layer is 30 mu m, and the glue material layer is made of acrylic ester polymer;
specifically, six sides of the acid and alkali resistant aluminum foil tape are used for wrapping the packaging body, and a cotton swab is required to lightly press the aluminum foil tape in the packaging body wrapping process so that the tape and a sample are completely adhered; and cutting off the aluminum foil tape at the target position of the chip crystal back after bonding by using an art designer knife, and observing whether the colloid of the aluminum foil tape at the notch surface of the cut target area is tightly combined with the edge of the target laser groove or not under a microscope along the black glue edge of the laser window when cutting, so as to ensure that the aluminum foil tape is completely bonded with the packaging body.
And S4, heating the 70wt% nitric acid solution to 150 ℃ by using a heating device, dripping the heated nitric acid reagent into the laser groove by using a dropper, and repeatedly treating until the copper frame which is partially exposed is corroded to clean and expose the surface mount adhesive.
S5, soaking the sample in acetone at room temperature for 2min, and slowly tearing off the acid and alkali resistant aluminum foil tape wrapping the surface of the packaging body to take out the complete packaging body (shown in fig. 4-D).
S6, firstly dipping an acetone reagent by using a purified cotton swab, wiping off the surface mount adhesive on the back surface of the crystal grain under a low power microscope to expose the whole back surface of the crystal grain, then placing the chip into a plastic cup, adding acetone, ultrasonically cleaning for 30S at room temperature and 45W power, and naturally airing to obtain a subsequent solderable chip (shown in figure 4-E).
Comparative example 1
The present comparative example provides a method for grinding and unsealing a back surface of a chip, specifically comprising the steps of:
s1, processing the back of a semiconductor device by using laser to remove a mold package on the back of the semiconductor device until a lead frame packaged in the semiconductor device is exposed;
s2, heating a 70wt% nitric acid solution to 150 ℃ by using a heating device, and removing the lead frame, wherein the nitric acid is used for reacting with the lead frame.
S3: the semiconductor device is cleaned using acetone.
S4: the chip is thinned by adopting a precise grinding machine, the rotating speed of a chassis of the precise grinding machine is set to be 150r/min, the rotating speed of a grinding head is set to be 10r/min, the horizontal rotating speed of the grinding head is set to be 0.625cm/s, and the grinding time is set to be 4min.
As shown in fig. 5, the conventional grinding method would not be able to retain the base frame, resulting in a failure to solder it to the PCB again.
Comparative example 2
The present comparative example provides a method for grinding and unsealing a back surface of a chip, specifically comprising the steps of:
s1, using 200-mesh sand paper, setting the rotating speed at 100r/min, and grinding the back of a sample until the back of a copper bottom plate is exposed and stopping;
s2, replacing 800-mesh sand paper, setting the rotating speed at 200r/min, and grinding the back of the sample until the back of the chip is exposed and stopping;
s3, polishing and grinding on polishing flannelette by adopting silica particle suspension colloid grinding liquid with the granularity model of 0.05 mu m, wherein the rotating speed range is set to be 300r/min, and the polishing time is set to be 8min;
s4, after unsealing, cleaning the sample by using an ultrasonic cleaner, removing residues remained on the back of the chip, and naturally drying to obtain a clean sample.
As shown in fig. 6, the conventional grinding method cannot retain the external pins, so that it cannot be soldered to the PCB again.
Application example 1
The application example provides a failure analysis positioning analysis method, which specifically comprises the following steps:
s1, welding the chip obtained by the processing of the embodiment 1 on a PCB with holes at the back of the wafer, and carrying out subsequent failure analysis and positioning.
S2, cleaning the sample and observing the sample by an optical microscope;
as shown in fig. 7, the observation result of the optical microscope shows that: the complete crystal back is exposed, the frame is not corroded, and the welding effect is good.
S3, performing an electrical test on the sample; the test condition of the electrical test is VSS-U10 voltage + -3V, and the current limit is 0.1mA.
As shown in fig. 8, the electrical test results show that: the failed product (# 11) was back-opened and soldered to the PCB without any difference in the test before and after back-opening, and was back-opened successfully.
Application example 2
The application example provides a failure analysis positioning analysis method, which specifically comprises the following steps:
s1, welding the chip obtained by the processing of the embodiment 2 on a PCB with holes at the back of the wafer, and carrying out subsequent failure analysis and positioning.
S2, cleaning the sample and observing the sample by an optical microscope;
as shown in fig. 9, the observation result of the optical microscope shows that: the complete crystal back is exposed, the frame and the welding pins are not corroded, and the welding effect is good.
S3, performing an electrical test on the sample; the test condition of the electrical test is a W-N IV curve test;
as shown in fig. 10, the electrical test results show that: the failed product (# 21) has no obvious difference in back-opening soldering PCB front and back tests, and the back-opening is successful.
In summary, the technology of chemically unsealing the wafer back is adopted, so that the integrity of the package main body frame and the chip pins are effectively protected, and the problem of difficult hot spot positioning analysis that the wafer back cannot be welded on the PCB after the back is unsealed is solved. The introduction of physical stress is reduced to a greater extent in the process of unsealing the wafer back, so that the effectiveness of the process of unsealing the wafer back is ensured. The invention effectively ensures the whole framework of the package while completing the experimental purpose, solves the problem of searching anomalies on the back of failure analysis of most board-level chips by improving the technology of locally chemically unsealing the wafer back, helps customers to successfully search the anomalies, and saves the time and investment of failure analysis of the customers FA.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A method of chemical unsealing of a subsequent solderable die backside, the method comprising the steps of:
determining a target area of a crystal back to be unsealed by determining the position of a copper substrate where a crystal grain in a chip package body is located, and recording the target area;
removing plastic packaging materials on the surface layer of the frame of the crystal back target area through laser treatment;
the chip package body is integrally wrapped by using an aluminum foil tape;
removing the aluminum foil tape wrapped in the target area by cutting to obtain a sample to be corroded;
and sequentially removing the copper substrate, the aluminum foil tape and the patch adhesive from the sample to be corroded by a chemical method to obtain the subsequent solderable chip.
2. The method for chemically unsealing the back surface of a subsequent solderable die of claim 1 wherein the means for locating the copper substrate on which the die is located in the die package is an X-ray device;
preferably, the back of the crystal target area that needs to unseal is the area between the position of the copper substrate that the crystal grain is located on and the edge of the external packaging body.
3. The method for chemically unsealing the back of the subsequent solderable chip according to claim 1, wherein the power of the laser treatment is 10-20W, the frequency of the laser treatment is 30-35 kHz, the pulse width of the laser treatment is 80-120, and the laser speed of the laser treatment is 700-900 mm/s;
preferably, the ratio of the laser treated area to the chip area is (1-1.1): 1.
4. The method of chemical unsealing of the backside of a subsequent solderable die of claim 1 wherein the aluminum foil tape comprises a layer of aluminum and a layer of adhesive material;
preferably, the thickness of the aluminum layer is 120-130 μm;
preferably, the thickness of the adhesive material layer is 20-30 μm;
preferably, the material of the adhesive material layer comprises acrylic ester and/or acrylic ester copolymer.
5. The method of chemical unsealing of the backside of a subsequent solderable die of claim 1 wherein said removing of the copper substrate specifically comprises the steps of:
and (3) dripping an acid reagent into the position of the copper substrate of the sample to be corroded until the copper substrate is completely corroded, and exposing the adhesive tape.
6. The method of chemically unsealing the backside of a subsequent solderable die of claim 5 wherein the acid reagent is a nitric acid solution;
preferably, the mass percentage of the nitric acid solution is 65-70%;
preferably, the temperature of the nitric acid solution is 145-155 ℃.
7. The method of chemical unsealing of the back side of a subsequent solderable die according to claim 1 or 5, wherein said removing of the aluminum foil tape comprises in particular the steps of:
and (3) soaking the chip sample with the copper substrate removed in a ketone solvent, and then tearing off all the aluminum foil adhesive tapes which are used for integrally wrapping the chip package.
8. The method of chemical opening of the backside of a subsequent solderable die of claim 7 wherein the ketone solvent is acetone;
preferably, the soaking temperature is 20-30 ℃, and the soaking time is 1-2 min.
9. The method of chemical unsealing of the backside of a subsequent solderable die of claim 1 wherein said removing of the paste specifically comprises the steps of:
firstly dipping a ketone solvent to wipe off the surface mount adhesive on the back surface of the crystal grain until the back surface of the complete crystal grain is exposed; and placing the chip in a ketone solvent, performing ultrasonic treatment, and drying to obtain the subsequent solderable chip.
10. The method of chemical opening of the backside of a subsequent solderable die of claim 9 wherein the ketone solvent is acetone;
preferably, the power of the ultrasonic treatment is 40-45W, the temperature of the ultrasonic treatment is 20-30 ℃, and the time of the ultrasonic treatment is 10-30 s.
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| CN202311831830.4A CN117790350A (en) | 2023-12-27 | 2023-12-27 | Chemical unsealing method for back surface of subsequent solderable chip |
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| CN202311831830.4A CN117790350A (en) | 2023-12-27 | 2023-12-27 | Chemical unsealing method for back surface of subsequent solderable chip |
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