CN117790304A - Method for forming semiconductor structure - Google Patents
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- CN117790304A CN117790304A CN202410021212.1A CN202410021212A CN117790304A CN 117790304 A CN117790304 A CN 117790304A CN 202410021212 A CN202410021212 A CN 202410021212A CN 117790304 A CN117790304 A CN 117790304A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 238000003860 storage Methods 0.000 claims abstract description 59
- 239000011241 protective layer Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 58
- 150000002500 ions Chemical class 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000008569 process Effects 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus ion Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate having a first conductivity type, the substrate having a first face; forming an initial trench in the substrate recessed relative to the first face; forming a protective layer on the surface of the side wall of the initial groove; forming storage doped regions in the substrate at two sides of the bottom of the initial trench, wherein the storage doped regions are of a first conductive type, and the doping concentration of the storage doped regions is larger than that of the substrate; after the storage doping region is formed, etching the bottom of the initial groove, and forming a groove in the substrate, wherein the bottom of the groove is lower than the bottom of the storage doping region. The forming method provided by the technical scheme can form the storage doped region at the expected depth of the substrate.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
The Insulated Gate Bipolar Transistor (IGBT) is one of the most important devices in the current power semiconductors, has the advantages of easiness in driving, simplicity in control and high switching frequency of a MOSFET, and has the advantages of low on-state voltage, high on-state current and small loss of the power transistor, so that the Insulated Gate Bipolar Transistor (IGBT) is widely applied to the fields of power grids, rail transit, electric automobiles, industrial frequency conversion and household appliances.
Future development of IGBT products mainly proceeds along two routes: firstly, the preparation technology of the ultra-thin wafer IGBT process and secondly, the design technology of the IGBT surface structure. The surface structure design technology mainly aims at improving the performance of the device by improving the carrier concentration at one side of the emitter, and the storage doping area is formed by injecting and diffusing a high-energy N-type area under the P substrate of the IGBT, so that holes are accumulated under the P substrate when the device is conducted, the carrier concentration at one side of the emitter when the device is conducted positively is improved, the conductivity modulation effect of the device is enhanced, and the forward conduction voltage drop of the device is reduced. The storage doped region needs to reach a preset depth in the substrate, the existing traditional storage doped region forming mode needs ultra-high energy ion implantation and an ultra-long time thermal process, a certain depth can be realized, the ultra-high energy ion implantation often exceeds the operation capacity of an ion implantation machine, and the ultra-long time thermal process often brings other difficult-to-recover influences on the product performance.
Accordingly, it is highly desirable to provide a method of forming a semiconductor structure that can form a storage doped region within a predetermined depth of a substrate without requiring high energy and long thermal processes.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which can form a storage doped region at the expected depth of a substrate.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate having a first conductivity type, the substrate having a first face; forming an initial trench in the substrate recessed relative to the first face; forming a protective layer on the surface of the side wall of the initial groove; forming storage doped regions in the substrate at two sides of the bottom of the initial trench, wherein the storage doped regions are of a first conductive type, and the doping concentration of the storage doped regions is larger than that of the substrate; after the storage doping region is formed, etching the bottom of the initial groove, and forming a groove in the substrate, wherein the bottom of the groove is lower than the bottom of the storage doping region.
Optionally, the ratio of the depth of the initial trench to the depth of the trench ranges from 0.2 to 0.99.
Optionally, the depth of the initial groove is 1-5 microns; the depth of the groove is 3-7 microns.
Optionally, the distance from the top of the storage doped region to the surface of the substrate is 0.5-5 microns.
Optionally, the method for forming the protective layer on the surface of the side wall of the initial trench includes: and forming an initial protection layer on the side wall and the bottom surface of the initial groove, and etching to remove the initial protection layer on the bottom surface of the initial groove.
Optionally, after forming the storage doped region, before etching the bottom of the initial trench, the method further includes: and removing the protective layer on the surface of the side wall of the initial groove.
Optionally, the material of the protective layer includes oxide, silicon nitride or silicon rich nitride.
Optionally, the method for forming the storage doped region in the substrate at two sides of the bottom of the initial trench comprises the following steps: and implanting ions of a first conductivity type into the bottom of the initial trench, and annealing the substrate to form storage doped regions in the substrate at two sides of the bottom of the initial trench.
Optionally, the ion implantation dose of the first conductive type ion is 5E11 atoms/cm 2 ～5E14atom/cm 2 The implantation energy is 0 KeV-2 MeV, and the included angle between the implantation direction of the first conductivity type ions and the normal line of the substrate is 0-50 degrees.
Optionally, the annealing treatment temperature is 800-1200 ℃ and the annealing treatment time is 5-300 min.
Optionally, the first conductivity type is N-type.
Optionally, before forming the initial trench, forming a mask layer exposing a portion of the surface of the substrate on the substrate, and etching the substrate to form the initial trench by using the mask layer as a mask.
Optionally, the material of the mask layer includes one or more of an oxide or a nitride.
Optionally, the method further comprises: forming a base doping region in the substrate, wherein the base doping region is in contact with the storage doping region, the base doping region is positioned at the top of the storage doping region, and the base doping region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming an emitter doping region in the substrate at two sides of the groove, wherein the emitter doping region is positioned at the top of the base doping region, the emitter doping region is of a first conductive type, and the doping concentration of the emitter doping region is larger than that of the substrate; forming a gate structure in the trench; a collector doping region is formed in a second face of the substrate, the collector doping region being of a second conductivity type, the second face being opposite the first face, a buffer layer being provided between the collector doping region and the storage doping region.
Optionally, the method further comprises: and forming a contact region in the substrate, wherein the contact region is of a second conductivity type, the contact region is positioned at the top of the base doped region, and the doping concentration of the contact region is greater than that of the base doped region.
Optionally, the gate structure includes a gate dielectric layer on the sidewall and bottom surface of the trench, and a gate layer on the gate dielectric layer.
Optionally, the method further comprises: forming an emitter conductive layer on top of the emitter doping region; and forming a collector conductive layer on one side of the collector doping region, which is away from the substrate.
Optionally, the second conductivity type is P-type.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the method for forming the semiconductor structure, the initial groove is formed in the substrate, the protective layer is formed on the surface of the side wall of the initial groove, then the storage doping areas are formed in the substrate at the two sides of the bottom of the initial groove, the bottom of the initial groove can be used for positioning the depth of the storage doping areas, and the depth of the formed storage doping areas in the substrate can be controlled easily; and in the process of forming the storage doped region, the side wall of the initial groove is provided with a protection layer for protection, so that ions of the first conductivity type forming the storage doped region are prevented from entering the substrate, and then the doped region of the second conductivity type ions is formed.
Drawings
Fig. 1 to 14 are schematic views illustrating steps in a semiconductor structure forming process according to an embodiment of the present invention.
Detailed Description
As described in the background art, in the IGBT semiconductor device, a storage doped region needs to be formed in an expected depth of a substrate, and a method for forming the storage doped region is currently commonly used, in which high-energy ion implantation is directly performed on the substrate, and then ions are pushed in through annealing treatment, so that great heat is required, and the ions are difficult to push to the expected depth, so that the process effect is poor.
In order to solve the above-mentioned problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including providing a substrate having a first conductivity type, the substrate having a first face; forming an initial trench in the substrate recessed relative to the first face; forming a protective layer on the surface of the side wall of the initial groove; forming storage doped regions in the substrate at two sides of the bottom of the initial trench, wherein the storage doped regions are of a first conductive type, and the doping concentration of the storage doped regions is larger than that of the substrate; after the storage doping region is formed, etching the bottom of the initial groove, and forming a groove in the substrate, wherein the bottom of the groove is lower than the bottom of the storage doping region. An initial groove is formed in a substrate, the bottom of the initial groove is used as the depth of a storage doped region in the substrate to be positioned, the storage doped regions are formed in the substrate at the two sides of the bottom of the initial groove, the formed storage doped regions are guaranteed to be at the expected depth of the substrate, and a protective layer on the side wall surface of the initial groove can protect other regions in the substrate from being polluted by ions of a first conductivity type so as to form the regions of the other conductivity types later, so that the forming positions of the storage doped regions are accurate, and the required energy is small.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 14 are schematic views illustrating steps in a semiconductor structure forming process according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 having a first conductivity type is provided, the substrate 100 having a first face 101.
In this embodiment, the substrate 100 has a first side 101 and a second side 102 disposed opposite to each other.
In this embodiment, the first conductivity type is N-type.
In this embodiment, the substrate 100 is a silicon substrate.
An initial trench is formed in the substrate 100 that is recessed relative to the first face 101.
Referring to fig. 2, a mask layer 103 exposing a portion of the surface of the substrate 100 is formed on the first surface 101 of the substrate 100 before the initial trench is formed.
The material of the mask layer 103 includes one or more of oxide or nitride, and in this embodiment, the material of the mask layer 103 is ethyl silicate.
In this embodiment, the method for forming the mask layer 103 includes: forming a mask material layer (not shown) on the first side 101 of the substrate 100; forming a photoresist layer (not shown) on the mask material layer; developing and exposing the photoresist layer to form a patterned photoresist layer; etching the mask material layer by taking the patterned photoresist layer as a mask to form the mask layer 103; and removing the patterned photoresist layer.
Referring to fig. 3, the substrate 100 is etched with the mask layer 103 as a mask, and an initial trench 104 is formed in the substrate 100.
In this embodiment, the substrate 100 is etched by using a dry etching process, and the initial trench 104 is formed in the substrate 100.
The depth of the initial trench 104 ranges from 1 micron to 5 microns, the bottom of the initial trench 104 provides depth positioning for the subsequent formation of the storage doped region, and the depth of the initial trench 104 ranges from a predetermined depth of the storage doped region to be formed within the substrate 100.
After the initial trench 104 is formed, a protective layer is formed on the sidewall surface of the initial trench 104.
In this embodiment, the method for forming the protective layer includes:
referring to fig. 4 and 5, an initial protection layer 200 is formed on the sidewall and bottom surface of the initial trench 104, the initial protection layer 200 on the bottom surface of the initial trench 104 is etched away, and a protection layer 201 is formed on the sidewall surface of the initial trench 104.
In this embodiment, the initial protection layer 200 on the bottom surface of the initial trench 104 is etched and removed by using a dry etching process.
In this embodiment, the protection layer 201 is used to form the storage doped region later, ions of the first conductivity type need to be implanted into the substrate 100, and the protection layer 201 can protect the ions of the first conductivity type from diffusing into the substrate 100 on both sides of the sidewall of the initial trench 104.
The material of the protective layer 201 includes oxide, silicon nitride or silicon rich nitride.
After forming the protection layer 201, in this embodiment, the method for forming the storage doped region includes:
referring to fig. 6 and 7, a memory doped region 105 is formed in the substrate 100 on both sides of the initial trench 104.
The arrow direction in fig. 6 indicates the ion implantation direction.
In this embodiment, the method for forming the storage doped region 105 includes: ions of the first conductivity type are implanted into the bottom of the initial trench 104 and the substrate 100 is annealed.
In this embodiment, the first conductive type ion is an N-type ion, and the N-type ion includes a phosphorus ion, an arsenic ion, and the like.
Specifically, the implantation dose of the first conductivity type ion is 5E11atom/cm 2 ～5E14atom/cm 2 The implantation energy is 0 KeV-2 MeV.
In this embodiment, the ion doping concentration of the storage doping region 105 is greater than the ion doping concentration of the substrate 100.
It should be further noted that, when the first conductivity type ions are implanted into the bottom of the initial trench 104, the first conductivity type ions are not implanted into the substrate 100 covered by the mask layer 103 due to the mask layer 103; in addition, due to the existence of the protective layer 201, the ion implantation of the substrate 100 on both sides of the sidewall of the initial trench 104 can be avoided, the implantation angle of the first conductive type ions can be between 0 ° and 50 °, the implantation angle is the angle between the implantation direction and the normal line of the substrate 100, and the ion implantation can be performed by tilting a certain angle to better implant the ions into the substrate 100 on both sides of the bottom of the initial trench 104, so that energy is saved for the subsequent annealing treatment.
After implanting the first conductivity type ions, an annealing process is performed to diffuse the first conductivity type ions into the substrate on both sides of the initial trench 104. Specifically, the annealing treatment temperature is 800-1200 ℃ and the time is 5-300 min, and too high annealing temperature can lead to material performance reduction and too low annealing temperature can lead to difficult repair of lattice defects caused by ion implantation; too long an anneal results in energy waste and too short an anneal to ensure that the implanted ions diffuse to the corresponding sites.
Referring to fig. 8, after the memory doped region 105 is formed, the protective layer 201 of the sidewall surface of the initial trench 104 is etched away.
In this embodiment, a wet etching process is used to remove the protective layer 201.
Referring to fig. 9, the bottom of the initial trench 104 is etched, and a trench 106 is formed in the substrate 100, wherein the bottom of the trench 106 is lower than the bottom of the storage doped region 105.
In this embodiment, a dry etching process is used to etch the bottom of the initial trench 104.
In this embodiment, the depth of the trench 106 is 3 micrometers to 7 micrometers, and the depth of the trench 106 can be determined according to actual process requirements.
The ratio of the depths of the initial trench 104 and the trench 106 ranges from 0.2 to 0.99.
After forming the trench 106, the mask layer 103 is removed.
Referring to fig. 10, a base doping region 107 is formed in the substrate 100 in contact with the memory doping region 105, the base doping region 107 being located on top of the memory doping region 105, the doping type of the base doping region 107 being of a second conductivity type, the second conductivity type being opposite to the first conductivity type.
In this embodiment, the second conductivity type is P-type.
With continued reference to fig. 10, forming an emitter doped region 108 in the substrate 100 on both sides of the trench 106, the emitter doped region 108 being located on top of the base doped region 107, the emitter doped region 108 being of the first conductivity type, and the doping concentration of the emitter doped region 108 being greater than the doping concentration of the substrate 100.
In this embodiment, the doping concentration of the emitter doped region 108 is 1E14 atoms/cm 2 ～1E16atom/cm 2 。
Referring to fig. 11, further comprising: a contact region 109 is formed within the substrate 100, the contact region 109 being of the second conductivity type, and the contact region 109 being located on top of the base doping region 107, and the doping concentration of the contact region 109 being greater than the doping concentration of the base doping region 107.
In this embodiment, the doping concentration of the contact region 109 is 1E14atom/cm 2 ～1E16atom/cm 2 The doping concentration of the base doping region 107 is 1E2 atom/cm 2 ～1E14atom/cm 2 。
Referring to fig. 12, a gate structure 112 is formed within the trench 106, a top surface of the gate structure 112 being flush with a top surface of the emitter doped region 108.
In this embodiment, the gate structure 112 includes a gate dielectric layer 110 on the bottom and sidewall surfaces of the trench 106, and a gate layer 111 on the gate dielectric layer 110.
The gate dielectric layer 110 may be made of a high-k dielectric layer or silicon oxide, and the gate layer 111 may be made of a polysilicon material.
Referring to fig. 13, further comprising: a collector doping region 113 is formed in the second side 102 of the substrate 100, the collector doping region 113 being of the second conductivity type, a buffer layer 114 being provided between the collector doping region 113 and the storage doping region 105.
In this embodiment, the buffer layer 114 is of the first conductivity type.
Referring to fig. 14, further comprising: an emitter conductive layer 115 is formed on top of the emitter doped region 108 and a collector conductive layer 116 is formed on the side of the collector doped region 113 facing away from the substrate 100.
In this embodiment, specifically, the emitter conductive layer 115 is located on top of the emitter doped region 108 and the contact region 109.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate having a first conductivity type, the substrate having a first face;
forming an initial trench in the substrate recessed relative to the first face;
forming a protective layer on the surface of the side wall of the initial groove;
forming storage doped regions in the substrate at two sides of the bottom of the initial trench, wherein the storage doped regions are of a first conductive type, and the doping concentration of the storage doped regions is larger than that of the substrate;
after the storage doping region is formed, etching the bottom of the initial groove, and forming a groove in the substrate, wherein the bottom of the groove is lower than the bottom of the storage doping region.
2. The method of forming a semiconductor structure of claim 1, wherein a ratio of a depth of said initial trench to a depth of said trench ranges from 0.2 to 0.99.
3. The method of forming a semiconductor structure of claim 1, wherein a depth of the initial trench is 1 micron to 5 microns; the depth of the groove is 3-7 microns.
4. The method of claim 1, wherein a distance from a top of the storage doped region to a surface of the substrate is between 0.5 microns and 5 microns.
5. The method of forming a semiconductor structure of claim 1, wherein forming a protective layer on sidewall surfaces of the initial trench comprises: and forming an initial protection layer on the side wall and the bottom surface of the initial groove, and etching to remove the initial protection layer on the bottom surface of the initial groove.
6. The method of forming a semiconductor structure of claim 1, further comprising, after forming the storage doped region, prior to etching the initial trench bottom: and removing the protective layer on the surface of the side wall of the initial groove.
7. The method of forming a semiconductor structure of claim 1, wherein the material of the protective layer comprises an oxide, silicon nitride, or silicon-rich nitride.
8. The method of forming a semiconductor structure of claim 1, wherein forming a storage doped region in the substrate on both sides of the bottom of the initial trench comprises: and implanting ions of a first conductivity type into the bottom of the initial trench, and annealing the substrate to form storage doped regions in the substrate at two sides of the bottom of the initial trench.
9. The method of forming a semiconductor structure according to claim 8, wherein an ion implantation dose of 5e11 atoms/cm for implanting ions of the first conductivity type 2 ～5E14atom/cm 2 The implantation energy is 0 KeV-2 MeV, and the included angle between the implantation direction of the first conductivity type ions and the normal line of the substrate is 0-50 degrees.
10. The method of forming a semiconductor structure of claim 8, wherein the annealing is performed at a temperature of 800 ℃ to 1200 ℃ for a time of 5min to 300min.
11. The method of forming a semiconductor structure of claim 1, wherein the first conductivity type is N-type.
12. The method of forming a semiconductor structure of claim 1, further comprising forming a mask layer on the substrate exposing a portion of the substrate surface prior to forming the initial trench, etching the substrate to form the initial trench using the mask layer as a mask.
13. The method of forming a semiconductor structure of claim 12, wherein the material of the mask layer comprises a combination of one or more of an oxide or a nitride.
14. The method of forming a semiconductor structure of claim 1, further comprising: forming a base doping region in the substrate, wherein the base doping region is in contact with the storage doping region, the base doping region is positioned at the top of the storage doping region, and the base doping region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming an emitter doping region in the substrate at two sides of the groove, wherein the emitter doping region is positioned at the top of the base doping region, the emitter doping region is of a first conductive type, and the doping concentration of the emitter doping region is larger than that of the substrate; forming a gate structure in the trench; a collector doping region is formed in a second face of the substrate, the collector doping region being of a second conductivity type, the second face being opposite the first face, a buffer layer being provided between the collector doping region and the storage doping region.
15. The method of forming a semiconductor structure of claim 14, further comprising: and forming a contact region in the substrate, wherein the contact region is of a second conductivity type, the contact region is positioned at the top of the base doped region, and the doping concentration of the contact region is greater than that of the base doped region.
16. The method of forming a semiconductor structure of claim 14, wherein said gate structure comprises a gate dielectric layer on sidewalls and a bottom surface of said trench, and a gate layer on said gate dielectric layer.
17. The method of forming a semiconductor structure of claim 14, further comprising: forming an emitter conductive layer on top of the emitter doping region; and forming a collector conductive layer on one side of the collector doping region, which is away from the substrate.
18. The method of forming a semiconductor structure of claim 14, wherein the second conductivity type is P-type.
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| CN202410021212.1A CN117790304A (en) | 2024-01-05 | 2024-01-05 | Method for forming semiconductor structure |
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| CN202410021212.1A CN117790304A (en) | 2024-01-05 | 2024-01-05 | Method for forming semiconductor structure |
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