CN117788532B - Ultra-high definition double-light fusion registration method based on FPGA in security field - Google Patents
Ultra-high definition double-light fusion registration method based on FPGA in security field Download PDFInfo
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Abstract
The invention discloses an ultra-high-definition double-light fusion registration method based on an FPGA in the security field, and belongs to the field of double-light fusion. An ultra-high definition dual-light fusion registration method based on FPGA in the security field comprises the following steps: the FPGA acquires an original visible light image of 8K and an original infrared image of a first resolution which are acquired simultaneously; upsampling the original infrared image to a first infrared image of 8K; respectively carrying out distortion correction on an original visible light image and a first infrared image to obtain a first visible light image and a second infrared image; and fusing the first visible light image and the second infrared image to generate an original fused image of 8K. The fusion effect of the invention takes the characteristics of large resolution and high definition of visible light into account, and also takes the characteristics of far infrared thermal imaging into account, and the fusion detection distance is far longer than that of the existing method.
Description
Technical Field
The invention belongs to the field of double-light fusion, and particularly relates to an ultra-high definition double-light fusion registration method based on an FPGA in the field of security and protection.
Background
The resolution of the existing dual-light fusion camera in the security field is mainly 640 x 512 or 1280 x 1024, and the fused resolution is consistent with the infrared resolution, so that the loss of detailed information of a lot of visible light is caused, and the remote detection is invalid. Meanwhile, for security monitoring scenes, low delay is the largest requirement, and the existing remapping mode is basically delayed by more than one frame.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an ultra-high-definition double-light fusion registration method based on an FPGA in the security field.
The aim of the invention is realized by the following technical scheme: an ultra-high definition dual-light fusion registration method based on FPGA in the security field comprises the following steps:
the FPGA acquires an original visible light image of 8K and an original infrared image of a first resolution which are acquired simultaneously;
upsampling the original infrared image to a first infrared image of 8K;
Respectively carrying out distortion correction on an original visible light image and a first infrared image to obtain a first visible light image and a second infrared image;
and fusing the first visible light image and the second infrared image to generate an original fused image of 8K.
Further, acquiring an original visible image of 8K and an original infrared image of a first resolution acquired simultaneously, comprising:
generating a synchronous trigger signal by the FPGA;
The FPGA outputs the synchronous trigger signal to the visible light camera and the infrared camera so that the visible light camera and the infrared camera collect images at the same time;
the FPGA acquires an 8K original visible light image acquired by a visible light camera and an original infrared image with first resolution acquired by an infrared camera.
Further, upsampling the original infrared image to a first infrared image of 8K includes:
up-sampling the original infrared image to obtain an intermediate infrared image with a second resolution;
and up-sampling the intermediate infrared image to obtain a first infrared image with 8K resolution.
Further, when up-sampling is performed on the original infrared image or the intermediate infrared image, the original infrared image or the intermediate infrared image is up-sampled into an intermediate image, and then the intermediate image is down-sampled into an infrared image with a target resolution, wherein the resolution of the intermediate image is larger than the target resolution.
Further, respectively performing distortion correction on the original visible light image and the first infrared image to obtain a first visible light image and a second infrared image, including:
writing the original visible light image and the first infrared image into a memory respectively;
Simultaneously reading an original visible light image and a first infrared image from a memory;
performing distortion correction on the original visible light image read from the memory to obtain a first visible light image;
And carrying out distortion correction on the first infrared image read from the memory to obtain a second infrared image.
Further, the process of distortion correction includes:
Determining the coordinates of a first pixel point corresponding to each pixel point in the original image according to the projection mapping table;
calculating the color value of the first pixel point according to four pixel points around the first pixel point in the original image;
And determining the color value of each pixel point in the corrected image as the color value of the corresponding first pixel point.
Further, the process of distortion correction further includes: a projection mapping table is obtained.
Further, the process of distortion correction further includes:
acquiring an address offset mapping table;
Reading original image data from the memory according to the address offset table;
And writing original image data into the FIFO channel line by line, and when the FIFO channel is full of data for generating pixel points of the corrected line, reading out the data in the FIFO channel successively and writing the data into the RAM.
Further, the pre-buffering of the image data is performed in parallel using a plurality of FIFO channels.
The beneficial effects of the invention are as follows:
(1) The fusion effect of the invention takes the characteristics of large resolution and high definition of visible light into account, and also takes the characteristics of far infrared thermal imaging into account, texture information is not lost, and the fusion detection distance is far longer than that of the existing method;
(2) According to the invention, the fast registration of the double-light device can be realized through the writing of the execution file of the projection mapping table, the writing of a plurality of projection files supports the infrared and visible light fusion under each zoom state, and the implementation mode of external block read-write is adopted on the basis of a heterogeneous platform of the FPGA, so that the method is suitable for most security and protection application scenes with low delay;
(3) The invention adopts infrared up-sampling to realize uniform resolution, then completes fusion with visible light, and completes the corresponding relation of double-light fusion full pixel level through a uniform projection mapping table.
Drawings
FIG. 1 is a schematic flow chart of the ultra-high definition dual-optic fusion registration method of the invention;
FIG. 2 is a block flow diagram of the ultra-high definition dual light fusion registration method of the present invention;
FIG. 3 is a schematic diagram of a pixel point corresponding to the corrected pixel point in the original image;
FIG. 4 is a schematic diagram of a process for synchronously triggering and capturing images according to the present invention;
FIG. 5 is a schematic flow chart of the distortion correction in the present invention.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present invention, based on the embodiments of the present invention.
Referring to fig. 1 to 5, the invention provides an ultra-high definition dual-light fusion registration method based on an FPGA in the security field, which comprises the following steps:
As shown in fig. 1 and fig. 2, an ultra-high-definition dual-light fusion registration method based on an FPGA in the security field includes S100 to S400.
S100. The FPGA acquires an original visible light image of 8K and an original infrared image of a first resolution which are acquired simultaneously.
Typically, the first resolution is less than 8K. For example, the first resolution is 1280 x 1024.
In some embodiments, acquiring the simultaneously acquired 8K of raw visible light image and the first resolution of raw infrared image comprises: generating a synchronous trigger signal by the FPGA; the FPGA outputs the synchronous trigger signal to the visible light camera and the infrared camera so that the visible light camera and the infrared camera collect images at the same time; the FPGA acquires an 8K original visible light image acquired by a visible light camera and an original infrared image with first resolution acquired by an infrared camera.
Specifically, the FPGA generates and outputs a synchronous trigger signal, the visible light camera and the infrared camera start exposing and outputting data by receiving the same synchronous trigger signal, the original visible light image is input into the FPGA by adopting an MIPI interface, and the original infrared image is input into the FPGA by adopting a DVP interface. In general, the synchronization trigger signal is a pulse trigger signal.
S200, up-sampling the original infrared image into a first infrared image of 8K.
In this embodiment, by upsampling the original infrared image with lower resolution, instead of downsampling the original visible image with 8K resolution, it is ensured that the final fusion image is 8K resolution, and the fusion effect not only considers the characteristics of high resolution and high definition of the visible image, but also considers the characteristics of the infrared image, and texture information is not lost.
In some embodiments, upsampling the original infrared image to a first infrared image of 8K comprises: up-sampling the original infrared image to obtain an intermediate infrared image with a second resolution; and up-sampling the intermediate infrared image to obtain a first infrared image with 8K resolution. The original infrared image is up-sampled into the first infrared image of 8K through a twice up-sampling mode, so that the problem that the sampling frequency of the FPGA is insufficient to sample for one time to obtain the 8K infrared image is solved.
For example, for an original infrared image with a resolution of 1280 x 1024, the first upsample is 3840 x 3072 for an intermediate infrared image and the second upsample is 7680 x 4320 for a first infrared image.
In some embodiments, when up-sampling the original or intermediate infrared image, the original or intermediate infrared image is up-sampled to an intermediate image, and then the intermediate image is down-sampled to an infrared image of a target resolution, wherein the intermediate image has a resolution greater than the target resolution. When the original infrared image is up-sampled, the target resolution is the second resolution, and when the intermediate infrared image is up-sampled, the target resolution is 8K.
S300, respectively carrying out distortion correction on the original visible light image and the first infrared image to obtain a first visible light image and a second infrared image.
Specifically, distortion correction is carried out on an original visible light image to obtain a first visible light image; and carrying out distortion correction on the first infrared image to obtain a second infrared image.
In some embodiments, performing distortion correction on the original visible light image and the first infrared image to obtain a first visible light image and a second infrared image respectively includes: writing the original visible light image and the first infrared image into a memory respectively; simultaneously reading an original visible light image and a first infrared image from a memory; performing distortion correction on the original visible light image read from the memory to obtain a first visible light image; and carrying out distortion correction on the first infrared image read from the memory to obtain a second infrared image.
In this embodiment, the original visible light image and the first infrared image are written into the memory first, and then synchronously read from the memory, so as to perform distortion correction, thereby realizing the synchronization of the original visible light image and the first infrared image again.
In some embodiments, the process of distortion correction includes: determining the coordinates of a first pixel point corresponding to each pixel point in the original image according to the projection mapping table; calculating the color value of the first pixel point according to four pixel points around the first pixel point in the original image; and determining the color value of each pixel point in the corrected image as the color value of the corresponding first pixel point.
In this step, when the original visible light image is subjected to distortion correction, the original image is the original visible light image, and when the first infrared image is subjected to correction, the original image is the first infrared image.
The projection mapping table stores the coordinates of the corresponding pixel point (i.e., the first pixel point) of each pixel point in the corrected image in the original image. Generally, four pixel points around the first pixel point refer to that the first pixel point is located in an area surrounded by the four pixel points, that is, the four pixel points encircle around the first pixel point.
When the original image is in YUV format, the color value of the pixel point comprises a brightness value and a chromaticity value; when the original image is in RGB format, the color values of the pixels include R, G, B values.
For example, if the image block is 32×32, the high 16 bits (i.e. 0×0224) of the projection mapping table of bilinear interpolation is an address of 2×32+24, which needs to continuously take four data (2×32+24,2×32+25,3×32+24,3×32+25), wherein the low 16 (i.e. 0×1012) is a weight relationship, the 0×10 is an X-direction weight relationship, the 0×12 is a Y-direction weight relationship, as shown in fig. 3, the specific logic is that the sampling points D (j+x, k+y) in fig. 3 are the corresponding pixel points of the corrected pixel points in the original image, pic_a (j, k), pic_b (j, k+1), pic_c (j+1, k+1) are four pixel points around the sampling points D (j+x, k+y), and the calculation is d=c_a (j+1, k+y) and the arithmetic result of the four pixel points around the sampling points D (j+x+1, k+y) is satisfied, so that the arithmetic formula of d_c_1 (j+k+y+1) is satisfied. When x=0 or y=0, a condition is satisfied, D [9] is determined, D [9] is increased by one when D [9] = =1, otherwise D [14] is determined, and D [14] is increased by one when D [14] = =1.
In some embodiments, if there are no four pixels around the first pixel corresponding to the pixel (e.g., the pixel at the edge) in the corrected image, filling may be performed according to a preset rule to obtain four pixels.
In some embodiments, the process of distortion correction further comprises: a projection mapping table is obtained. Generally, the projection mapping table is stored in a flash, and the projection mapping table is loaded into a memory after the FPGA is powered on.
In some embodiments, the process of distortion correction further comprises: acquiring an address offset mapping table; reading original image data from the memory according to the address offset table; and writing original image data into the FIFO channel line by line, and when the FIFO channel is full of data for generating pixel points of the corrected line, reading out the data in the FIFO channel successively and writing the data into the RAM.
In general, an address offset table is stored in a flash, after the FPGA is powered on, the address offset table is loaded into a memory, and the address offset table stores starting coordinates of an address offset (i.e., starting positions of image blocks in an original image in the memory), where the number of starting coordinates is equal to the resolution of the original image divided by the size of the image blocks of the original image.
Generally, the address offset table and the projection mapping table are both generated in advance and stored in the flash, and the FPGA is loaded into the memory after being electrified.
In this embodiment, the distortion correction operation of the image is completed by prefetching blocks from the memory, and the larger the distortion of the camera lens is, the larger the original image for one line of distortion correction buffer is, so that the mode of pre-writing DDR is adopted. For example, in fig. 4, the frame_ctl module is used as a counter module for writing an infrared image and a visible light image into a memory, VPSS (video process subsystem) is used for implementing a zoom-in function of the image, datamover is an IP for implementing random burst reading and writing of DDR in an FPGA, ten rows of original pixels are required for correcting one row of lenses with 8mm, and when the writing memory is 10 rows, map_start= 1 is triggered, and meanwhile, the subsequent distortion correction operation is started.
For example, as shown in fig. 5, rd_ IRAnge represents a module for reading an address offset mapping table, rd_map represents a module for reading a projection mapping table, IRAnge is the start coordinate of an address offset, the number of coordinates is equal to the original resolution/BLOCK size, map is a projection mapping table for bilinear interpolation, rd_block represents a BLOCK for reading DDR according to the address offset mapping table, and Bilnear represents bilinear interpolation. And reading out original image blocks in the memory address through the address offset mapping table, and simultaneously reading out bilinear mapping tables in the memory in parallel. The distortion correction operation is started after receiving the map_start signal. Firstly, reading out an address offset mapping table from a memory, wherein each table is 32-bit data, for example, 0X004a05f6 is an address mapping table of an original image block, 004a is an X address coordinate of the original image block in the memory, 05f6 is a Y address coordinate of the original image block in the memory, and the original image block is de-indexed through the two coordinates and read out.
The function of rd_sync (coordination module) is to coordinate the original map block with the block of the bilinear interpolation projection mapping table, for example, the original map block is 24×13 in size of 64×64 bilinear interpolation projection mapping table. The rd_sync needs to dynamically coordinate the data read from the DDR (memory), and since DDR read data is an integer of 16 in burst form, 24×13 does not satisfy the integer of 16, redundant data needs to be reserved in the DDR. When map (projection mapping table) data of bilinear interpolation meets 24 x 16, automatically closing a read signal, waiting for the other party 64 x 64 data to finish reading and starting the next round of read-write operation.
In some embodiments, the image data is pre-cached in parallel by adopting a plurality of FIFO channels, so that the processing efficiency is greatly improved, the delay is reduced, and the method is particularly suitable for monitoring in the security field. For example, for an 8K image, at a clock of 400Mhz, an 8-channel parallel processing method is adopted, the processing efficiency is 1:1.371, and the added processing delay is 2.5ns by 0.371 by 7680 by 4320/8.
A 6 x 16 block under an 8mm lens may correspond to a 5 x 14 generated image. In the embodiment, the dual light fusion is a pixel-by-pixel line matching logic, so that a mode of pre-caching a plurality of FIFO channels is adopted, the generated images are written into the FIFO channels line by line through the counter logic, and the images are read out successively when one line is full, so that timeliness and instantaneity are improved.
S400, fusing the first visible light image and the second infrared image to generate an original fusion image of 8K.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (8)
1. The ultra-high definition dual-light fusion registration method based on the FPGA in the security field is characterized by comprising the following steps of:
the FPGA acquires an original visible light image of 8K and an original infrared image of a first resolution which are acquired simultaneously;
upsampling the original infrared image to a first infrared image of 8K;
Respectively carrying out distortion correction on an original visible light image and a first infrared image to obtain a first visible light image and a second infrared image;
Fusing the first visible light image and the second infrared image to generate an original fused image of 8K;
the process of distortion correction includes:
Determining the coordinates of a first pixel point corresponding to each pixel point in the original image according to the projection mapping table;
calculating the color value of the first pixel point according to four pixel points around the first pixel point in the original image;
And determining the color value of each pixel point in the corrected image as the color value of the corresponding first pixel point.
2. The ultra-high definition dual light fusion registration method based on the FPGA in the security field of claim 1, wherein the step of acquiring the 8K original visible light image and the first resolution original infrared image which are acquired simultaneously comprises the following steps:
generating a synchronous trigger signal by the FPGA;
The FPGA outputs the synchronous trigger signal to the visible light camera and the infrared camera so that the visible light camera and the infrared camera collect images at the same time;
the FPGA acquires an 8K original visible light image acquired by a visible light camera and an original infrared image with first resolution acquired by an infrared camera.
3. The ultra-high definition dual light fusion registration method based on the FPGA in the security field as claimed in claim 1, wherein the up-sampling of the original infrared image into the first infrared image of 8K comprises the following steps:
up-sampling the original infrared image to obtain an intermediate infrared image with a second resolution;
and up-sampling the intermediate infrared image to obtain a first infrared image with 8K resolution.
4. The ultra-high definition dual light fusion registration method based on the FPGA in the security field according to claim 3, wherein when the original infrared image or the intermediate infrared image is up-sampled, the original infrared image or the intermediate infrared image is up-sampled to be an intermediate image, and then the intermediate image is down-sampled to be an infrared image with target resolution, wherein the resolution of the intermediate image is larger than the target resolution.
5. The ultra-high definition dual light fusion registration method based on the FPGA in the security field of claim 1, wherein the distortion correction is performed on an original visible light image and a first infrared image respectively to obtain the first visible light image and a second infrared image, and the method comprises the following steps:
writing the original visible light image and the first infrared image into a memory respectively;
Simultaneously reading an original visible light image and a first infrared image from a memory;
performing distortion correction on the original visible light image read from the memory to obtain a first visible light image;
And carrying out distortion correction on the first infrared image read from the memory to obtain a second infrared image.
6. The ultra-high definition dual light fusion registration method based on the FPGA in the security field according to claim 1, wherein the distortion correction process further comprises: a projection mapping table is obtained.
7. The ultra-high definition dual light fusion registration method based on the FPGA in the security field according to claim 1, wherein the distortion correction process further comprises:
acquiring an address offset mapping table;
Reading original image data from the memory according to the address offset table;
And writing original image data into the FIFO channel line by line, and when the FIFO channel is full of data for generating pixel points of the corrected line, reading out the data in the FIFO channel successively and writing the data into the RAM.
8. The ultra-high definition dual light fusion registration method based on the FPGA in the security field as claimed in claim 7, wherein a plurality of FIFO channels are adopted to pre-cache image data in parallel.
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| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No. 401, 4th Floor, Building 2, No. 88 Shengtong Street, Chengdu High tech Zone, China (Sichuan) Pilot Free Trade Zone, Chengdu City, Sichuan Province 610095 Patentee after: Sichuan Guochuang Innovation Vision Ultra HD Video Technology Co.,Ltd. Country or region after: China Address before: Room 401, Building 2, Tianfu Changdao Phase 2, No. 88 Shengtong Street, High tech Zone, Chengdu City, Sichuan Province, 610000 Patentee before: Sichuan Xinshi Chuangwei ultra high definition Technology Co.,Ltd. Country or region before: China |