CN117787163A

CN117787163A - Time sequence analysis method, device, equipment and medium based on graph traversal

Info

Publication number: CN117787163A
Application number: CN202311842888.9A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Suzhou Yige Technology Co ltd
Current assignee: Suzhou Yige Technology Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-03-29

Abstract

The invention relates to the technical field of static time sequence analysis, and discloses a time sequence analysis method, a device, equipment and a medium based on graph traversal, wherein the method comprises the following steps: obtaining a directed node diagram corresponding to a target circuit, wherein directed edges of nodes in the diagram are used for connecting subsequent nodes of the nodes; determining a starting node, and performing traversal access on each node based on the directed edges of each node; when the repeated access node appears, removing the corresponding directed edge, and returning to the previous access node to continue traversing; if the current node does not have the non-accessed successor node, judging that the node is accessed completely, returning to the last access node to continue traversing until all the nodes are accessed completely, and obtaining a topology sequencing result according to the time sequence of the accessed completely; the invention realizes loop detection and ring breakage through one-time graph traversal based on the topology sequencing result to obtain the final topology sequencing result, thereby carrying out time sequence analysis and solving the problems of calculation redundancy and long running time.

Description

Time sequence analysis method, device, equipment and medium based on graph traversal

Technical Field

The invention relates to the technical field of static time sequence analysis, in particular to a time sequence analysis method, device, equipment and medium based on graph traversal.

Background

As integrated circuit designs continue to evolve, the requirements for circuit timing performance become increasingly stringent. Static timing analysis is a critical task for evaluating timing performance of signal transmissions in integrated circuits. In the process of performing static timing analysis on a circuit, topological sorting, loop detection and loop breaking are three indispensable steps, and directly influence the reliability and performance of the circuit.

The importance of topological ordering in circuit design is not negligible. The transmission sequence of signals is critical for proper timing analysis due to the large number of logic gates and interconnections contained in the circuit diagram. At the same time, the presence of loops may lead to uncertainty and instability in signal transmission, and loop detection becomes critical in circuit design as well. The loop breaking serves as a critical step to further ensure the stability and predictability of the circuit by eliminating the loop.

In the prior art, a conventional static timing analysis method generally requires multiple graph traversals, wherein topology ordering and loop detection are performed at different stages. Such staged processing results in computational redundancy and long run times, limiting the application of static timing analysis in large scale integrated circuit designs.

Disclosure of Invention

In view of the above, the present invention provides a timing analysis method, apparatus, device and medium based on graph traversal, so as to solve the problems of computational redundancy and long operation time when performing static timing analysis on a circuit.

In a first aspect, the present invention provides a timing analysis method based on graph traversal, the method comprising:

acquiring a description file of a target circuit, and generating a corresponding directed node diagram according to the description file, wherein directed edges of nodes in the directed node diagram are used for connecting subsequent nodes of the nodes;

determining a starting node, and performing traversal access on each node in the directed node diagram based on the starting node and directed edges of each node;

in the process of traversing access, when a repeated access node appears, removing a directed edge between the repeated access node and a last access node, and returning to the last access node to continue traversing access;

if the current node does not have the non-accessed subsequent node, judging that the current node is accessed completely, returning to the last access node of the current node, continuing to traverse access until all the nodes are accessed completely, and obtaining a topology sequencing result aiming at the target circuit according to the time sequence of the access completion of all the nodes;

And carrying out static time sequence analysis on the target circuit based on the topological sorting result.

The directed node diagram corresponding to the target circuit diagram is traversed, the directed edges corresponding to the repeatedly accessed nodes can be removed in one traversal process, the purpose of ring breaking is achieved, the nodes are ordered according to the traversal access states of the nodes in a convenient process, a final topology ordering result is obtained, static time sequence analysis is carried out, ring breaking can be completed only by traversing the diagram once, the topology ordering result is obtained, and the problems of calculation redundancy and long running time are greatly avoided.

In an optional embodiment, the performing traversal access on each node in the directed node graph based on the starting node and the directed edge of each node includes:

traversing access from the initial node, and updating the node state of the current node to accessed after the current node is accessed;

and determining a subsequent node of the current node according to the directed edge of the current node, and performing traversal access on the subsequent node.

The method has the advantages that the accessed node state is updated in the process of traversing the access node, so that the repeatedly accessed node is determined in the traversing process, the repeatedly accessed node is accurately determined, and the accuracy in the subsequent removal of the directed edge is ensured.

In an optional implementation manner, when a repeated access node appears in the process of traversing access, removing a directed edge between the repeated access node and a last access node, and returning to the last access node to continue traversing access, including:

and when the node state is the accessed first node in the traversal access, determining the first node as a repeated access node, removing a directed edge between the repeated access node and a previous access node, returning to the previous access node, and performing traversal access on other subsequent nodes of the previous access node.

And when the repeated access node appears, the directed edge between the node and the previous node is removed, so that a graph after ring breakage is obtained, the stability and predictability of the circuit are ensured, and a final topological ordering result is obtained.

In an alternative embodiment, the returning to the last access node of the current node continues traversing the access, including:

and according to the traversing access process, returning to a last access node of the current node, and performing traversing access on other non-accessed successor nodes of the last access node.

When the current node does not have a subsequent node, the method returns to the previous node to continue traversing so as to ensure that all nodes in the graph can be traversed and avoid node omission.

In an optional real-time manner, the obtaining the topology ordering result for the target circuit according to the time sequence of the access completion of each node includes:

and placing the node which is accessed first in the last position of the topological sorting, and obtaining a topological sorting result from the back to the front according to the time sequence of the accessed nodes.

And ordering the nodes according to the time sequence of the accessed nodes, wherein the last result of the topological ordering is corresponding to the node accessed first, so that an accurate topological ordering result is obtained.

In an alternative embodiment, the performing static timing analysis on the target circuit based on the topology ordering result includes:

calculating to obtain the arrival time and the latest migration time of each node according to the topology sequencing result and the signal transmission condition in the target circuit;

and performing static time sequence analysis on the target circuit based on the arrival time and the latest migration time.

The arrival time and the latest migration time of each node can be accurately obtained according to the topological sequencing result, and the accuracy of the calculation result is ensured, so that the effectiveness of static time sequence analysis is ensured.

In an optional implementation manner, the calculating to obtain the arrival time and the latest migration time of each node according to the topology ordering result and the signal transmission condition in the target circuit includes:

calculating the arrival time of each node according to the topology sequencing result and the time required by the transmission of the signals between each node in the target circuit;

and calculating the latest migration time of each node according to the reverse order of the topology sequencing result and the time required by the transmission of signals between each node in the target circuit.

The arrival time and the latest migration time are calculated through two opposite sequences, so that the effectiveness of calculation of the two data is ensured.

In a second aspect, the present invention provides a graph traversal-based timing analysis apparatus, the apparatus comprising:

the node diagram generation module is used for acquiring a description file of the target circuit, generating a corresponding directed node diagram according to the description file, wherein directed edges of all nodes in the directed node diagram are used for connecting subsequent nodes of all the nodes;

the traversal access module is used for determining a starting node, and performing traversal access on each node in the directed node diagram based on the starting node and the directed edges of each node;

The ring breaking processing module is used for removing a directed edge between the repeated access node and a last access node when the repeated access node appears in the process of traversing access, and returning to the last access node to continue traversing access;

the topology sequencing module is used for judging that the current node finishes accessing if the current node does not have the non-accessed subsequent node, returning to the last access node of the current node, continuing traversing the access until all the nodes finish accessing, and obtaining a topology sequencing result aiming at the target circuit according to the time sequence of finishing accessing of all the nodes;

and the time sequence analysis module is used for carrying out static time sequence analysis on the target circuit based on the topological ordering result.

In a third aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection, computer instructions are stored in the memory, and the processor executes the computer instructions, so that the time sequence analysis method based on graph traversal of the first aspect or any embodiment corresponding to the first aspect is executed.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the graph traversal-based timing analysis method of the first aspect or any of its corresponding embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a graph traversal-based timing analysis method according to an embodiment of the invention;

FIG. 2 is a flow chart of another graph traversal-based timing analysis method according to an embodiment of the invention;

FIG. 3 is an exemplary diagram of a topology ordering code according to an embodiment of the invention;

FIG. 4 is an exemplary diagram of a directed node in accordance with an embodiment of the present invention;

FIG. 5 is a diagram illustrating an example change in node state according to an embodiment of the present invention;

FIG. 6 is an exemplary graph of broken ring directed nodes according to an embodiment of the present invention;

FIG. 7 is a block diagram of a timing analysis device based on graph traversal according to an embodiment of the invention;

fig. 8 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

With the continued development of integrated circuit designs, the requirements for circuit timing performance are becoming increasingly stringent. It is therefore becoming increasingly important to conduct static timing analysis on circuits, which is used to evaluate timing performance of signal transmissions in integrated circuits. In the process of performing static timing analysis on a circuit, topological sorting, loop detection and loop breaking are three indispensable steps, and directly influence the reliability and performance of the circuit.

Since the circuit diagram includes a large number of logic gates and interconnections, the transmission order of signals is critical for proper timing analysis, so the importance of topological ordering in circuit design is not negligible. At the same time, the presence of loops may lead to uncertainty and instability in signal transmission, and loop detection becomes critical in circuit design as well. The loop breaking serves as a critical step to further ensure the stability and predictability of the circuit by eliminating the loop.

Therefore, the embodiment of the invention provides a static time sequence analysis method based on graph traversal, which completes loop detection and loop breaking in the process of traversing a directed node diagram corresponding to a target circuit once to finally obtain a topology sequencing result, so that the static time sequence analysis is carried out on the target circuit according to the topology sequencing result, and the problems of calculation redundancy and long running time caused by the need of graph traversal for multiple times in the traditional static time sequence analysis can be solved.

In accordance with an embodiment of the present invention, a graph traversal-based timing analysis method embodiment is provided, it being noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.

In this embodiment, a timing analysis method based on graph traversal is provided, which can be used for the static timing analysis described above, and fig. 1 is a flowchart of a timing analysis method based on graph traversal according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:

step S101, a description file of a target circuit is obtained, a corresponding directed node diagram is generated according to the description file, and directed edges of nodes in the directed node diagram are used for connecting subsequent nodes of the nodes.

In performing static timing analysis on a target circuit, first, description information of the circuit needs to be obtained from a description file of the target circuit, for example, the description information is read from a netlist file, so as to generate a directed node diagram corresponding to the target circuit. For example, in the generated directed node diagram, each circuit element or pin thereof in the target circuit corresponds to a node in the directed node diagram. Each node is connected by a directed edge, which is used to represent the dependency relationship between the individual circuit elements, which can be understood as the flow relationship of signals in the circuit. Each node is connected to a subsequent node of the node by a directed edge, which is understood to be the node that the next potential pass of the signal in the circuit after passing through the node.

Step S102, determining a starting node, and performing traversal access on each node in the directed node diagram based on the starting node and the directed edges of each node.

An initial node is determined in the obtained directed node diagram, and the initial node is usually set as a node corresponding to a circuit element for transmitting signals initially in a circuit, but different initial nodes can also be randomly set, and can possibly cause different topological sequences, but when static time sequence analysis is performed, the static time sequence analysis can also be completed according to different topological sequence results.

After determining the initial node, traversing the nodes in the graph from the initial node, wherein each node comprising the initial node can determine the subsequent nodes through corresponding directed edges, and traversing the nodes in the graph by taking depth priority as a principle.

Step S103, removing the directed edge between the repeated access node and the last access node when the repeated access node appears in the process of traversing access, and returning to the last access node to continue traversing access.

In the process of traversing access to nodes in the graph, it can be determined that the nodes in the graph are accessed and the nodes are not accessed along with the traversing process, when a node is repeatedly accessed, the loop is indicated to appear, and the directed edge between the node and the last access node corresponding to the node is required to be removed at the moment, so that the purpose of ring breaking is achieved, and the predictability of the circuit is ensured. And returning to the previous access node, and continuing to carry out traversal access on the subsequent nodes.

Step S104, if the current node does not have the non-accessed successor node, judging that the current node is accessed completely, returning to the last access node of the current node, continuing to traverse access until all the nodes are accessed completely, and obtaining a topology sequencing result aiming at the target circuit according to the time sequence of the access completion of all the nodes.

When traversing access is carried out, after one node is accessed, the subsequent node of the node is accessed according to the directed edge, after the directed edge between the current node and the repeated access node is removed, if the current node does not have the subsequent node which is not accessed, the node is indicated to have been accessed, and rollback is started. The previous node of the node is returned to access, if the previous node still has the non-accessed subsequent node, the subsequent node is continued to be traversed and accessed until the current node in the traversing and accessing process has the non-accessed subsequent node, and the completion of the node access is judged according to the content, and the returning is started; if the last node does not have the non-accessed subsequent node, the last node is considered to be accessed completely, the rollback is continued, and the steps are repeated until all the nodes are accessed completely. At this time, the topology sequencing result for the target circuit can be obtained according to the time sequence of the access completion of each node.

Step S105, performing static timing analysis on the target circuit based on the topology sequencing result.

After the topology sequencing result aiming at the target circuit is obtained, various data required in the process of topology analysis can be obtained according to the topology sequencing result, so that static time sequence analysis is carried out on the target circuit, and the time sequence performance of signal transmission in the target circuit is judged.

According to the graph traversal-based time sequence analysis method, loop detection is completed in the process of traversing the directed node graph corresponding to the target circuit once, and loop breaking is performed on the loop, so that a topology ordering result is finally obtained, and static time sequence analysis is performed on the target circuit according to the topology ordering result, so that the problems of calculation redundancy and long running time caused by the fact that multiple graph traversals are needed in traditional static time sequence analysis can be solved.

According to an embodiment of the present invention, another embodiment of a timing analysis method based on graph traversal is provided, which can be used for the static timing analysis described above, and fig. 2 is a flowchart of another timing analysis method based on graph traversal according to an embodiment of the present invention, as shown in fig. 2, where the flowchart includes the following steps:

step S201, a description file of a target circuit is obtained, a corresponding directed node diagram is generated according to the description file, and directed edges of nodes in the directed node diagram are used for connecting subsequent nodes of the nodes. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S202, determining a starting node, and performing traversal access on each node in the directed node diagram based on the starting node and the directed edges of each node.

Specifically, in the step S202, performing traversal access on each node in the directed node map based on the start node and the directed edges of each node, includes:

It will be appreciated that when traversing access to nodes in the directed node graph, the state of each node may be set, and after each node is accessed, the state may be updated to accessed. For example, before starting access, the state of each node in the directed node graph is not accessed, and the state of each node may be set to 0 to indicate that the node has not been accessed, and when the node with the node state of 0 is accessed, the node state is updated to be accessed, that is, the node state is updated to 1, to indicate that the node state of the node is accessed.

After one node is accessed, namely after the node state is updated to be 1, determining the subsequent node corresponding to the node according to the directed edge of the node, so as to access the subsequent node, and repeating the steps in the whole access process until the node which is accessed repeatedly or no subsequent node which is not accessed appears.

In step S203, when the repeated access node appears in the process of traversing access, the directed edge between the repeated access node and the last access node is removed, and the previous access node is returned to continue traversing access.

Specifically, in the step S203, when the repeated access node appears in the process of traversing access, the directed edge between the repeated access node and the previous access node is removed, and the previous access node is returned to continue traversing access, including:

and when the access is traversed, determining the first node as a repeated access node when the node state is the accessed first node, removing the directed edge between the repeated access node and the last access node, returning to the last access node, and carrying out traversal access on other subsequent nodes of the last access node.

It can be understood that when performing traversal access, the subsequent node of the current node may be the accessed node, that is, the accessed node state is the accessed first node, which indicates that an inner loop exists in the whole directed node graph, and then ring breaking processing is needed. And defining the first node as a repeated access node, removing the directed edge between the first node and the last access node corresponding to the expected node, namely performing ring breaking processing, returning traversal to the last access node to continue traversal access, and accessing the subsequent nodes of the last access node except the repeated access node.

Step S204, if the current node does not have the non-accessed successor node, judging that the current node is accessed completely, returning to the last access node of the current node, continuing to traverse access until all the nodes are accessed completely, and obtaining a topology sequencing result aiming at the target circuit according to the time sequence of the access completion of all the nodes.

Specifically, in the step S204, the previous access node that rolls back to the current node continues the traversal access, including:

and according to the traversing access process, returning to the last access node of the current node, and performing traversing access on other non-accessed successor nodes of the last access node.

It will be understood that after the directed edges between the current node and the repeatedly accessed successor nodes are eliminated in step S203, if the current node has no non-accessed successor nodes, for example, in the initial node diagram, all the successor nodes of the current node are accessed nodes, but the directed edges between the current node and these accessed nodes have been eliminated, the current node is rolled back, and if at this time the current node has no non-accessed successor nodes, that is, a successor node with a state of 0, at this time, it is determined that the current node is accessed completely, the state of the node may be set to 2.

Then, the method returns to the last access node, and there may be three subsequent nodes of the last access node, one node with a node state of 1, for which access can be continued, the ring-breaking processing mentioned above is performed, and after the ring-breaking processing, the method returns to the node, one node with a state of 0 is an access node, and for which access can be continued according to the above description, and one accessed node with a state of 2 is an accessed node. If the last node does not have any non-accessed node after performing ring breaking processing on all the accessed nodes corresponding to the last node, namely, if the last node has a subsequent node with a state of 0, the state of the last node is updated to be accessed, namely, the state of the last node is updated to be 2. And continuing to rollback at the moment, and repeating the steps until the node states of all the nodes are accessed. And at the moment, obtaining a topological ordering result aiming at the target circuit according to the time sequence of the access completion of each node.

When the current node does not have the successor nodes, the method returns to the previous node to continue traversing, so that each successor node of the node is ensured to be traversed and accessed in the access process, and omission of the node is avoided.

Specifically, in the step S204, a topology ordering result for the target circuit is obtained according to the time sequence of the access completion of each node, including:

It can be understood that the node status updated to the accessed node is determined to be the last position of the topological order, and the order is carried out according to the last position, and each time an accessed node appears, the node is set in a sequence of the topological order from back to front, and finally the topological order result is obtained.

In one example, due to different selection of the initial node, the node may return to the initial node if the node is not traversed in the traversing process, at this time, the node which is not accessed in the node diagram may be accessed, and the traversing is continued according to the flow corresponding to the method, until all the nodes in the node diagram are traversed, so as to obtain the final topology sequencing result.

Step S205, performing static time sequence analysis on the target circuit based on the topological sorting result.

Specifically, referring to fig. 2, the step S205 includes:

step S2051, calculating the arrival time and the latest migration time of each node according to the topology sequencing result and the signal transmission condition in the target circuit.

When signals in the circuit are transmitted, the time delay of the signals when the signals are transmitted between different nodes is determined according to the signal transmission condition in the target circuit. And calculating the arrival time and the latest migration time of each node according to the topological ordering result and the time delay in signal transmission.

Specifically, according to the topology sequencing result and the signal transmission condition in the target circuit, the arrival time and the latest migration time of each node are calculated, including:

It will be appreciated that, based on the topology ordering result, the arrival time of the signal transmitted to each node is calculated from the order in which the topology ordering result corresponds and the time required for signal transmission between each node, which is also called AT (arrival time) in some scenarios. In calculating the arrival time, in a node diagram corresponding to the target circuit, there may be a plurality of previous nodes in one node, and a plurality of arrival times exist, where the maximum value of the arrival times is determined as the arrival time of the node.

In some cases, also called RT (required time), the latest migration time corresponding to each node is calculated according to the sequence and the transmission time of the signal between the nodes, which is similar to the calculation method described above, but the latest migration time is calculated according to the reverse sequence, and the latest migration time is defined as the time corresponding to the minimum value.

Step S2052, performing static timing analysis on the target circuit based on the arrival time and the latest transition time.

Determining a specific analysis mode according to the type of the circuit, wherein some circuits consider that the difference value of the two is positive, and the time sequence analysis result is qualified; some circuits may be considered to be qualified when the difference between the two is negative, or in some cases, the timing analysis result may be judged to be qualified when the difference is 0, and the specific analysis method is determined according to the specific situation, which is not limited herein.

According to the time sequence analysis method based on graph traversal, which is provided by the embodiment of the invention, through obtaining the directed node graph corresponding to the target circuit, performing traversal access on each node, performing ring breaking processing in the access process, finally performing topology sequencing according to the access finishing sequence of each node, finally performing static time sequence analysis according to the topology sequencing result, and obtaining the final topology sequencing result by performing one-time traversal on the graph, thereby solving the problems of computational redundancy and long running time.

In order to facilitate understanding of the method embodiment provided by the present invention, a specific exemplary example is provided, as shown in fig. 3, which is an exemplary diagram of topologically ordered codes according to an embodiment of the present invention, in which a code manner is provided for implementing the content of the topologically ordered portion in the method embodiment described above. Meanwhile, an exemplary directed node diagram is provided, as shown in fig. 4, which is an exemplary directed node diagram according to an embodiment of the present invention, fig. 5 is an exemplary node state change diagram according to an embodiment of the present invention, and fig. 5 corresponds to the codes and directed node diagrams provided in fig. 3 and 4.

Taking fig. 4 as an example, a directed node diagram corresponding to a target circuit is generated, a point a in the diagram is taken as a starting node, the node states of all nodes before access are 0, referring to fig. 5, firstly, the point a is accessed, the node states of the point a become 1, the subsequent nodes of the point a are B and C, then, the point B is accessed after traversing selection, the node state of the point B becomes 1, and the same processing is performed on D and E; the successor node of E is F, the successor node of F is C, and the same process is performed on them. At this time, the node C is accessed, the subsequent node is E, the E is accessed, the E is found to have been accessed, the state is 1, the directed edge between C and E is disconnected, the broken ring directed node example diagram shown in fig. 6 is obtained, and the C is rolled back to the point C, at this time, the node C has no subsequent node which has not been accessed, the node state of the node C is updated to 2, that is, the access is completed, and the rolling back is performed, in the rolling back process, each node F, E, D, B, A updates the node state to 2 in this way, and the final topology ordering is the abdafc shown in fig. 5.

After the topology ordering result is obtained, calculating the arrival time and the latest migration time: from the result of the topological ordering we calculate the arrival time of each circuit node. The arrival time represents the time at which the signal actually arrives at the node in the circuit. Meanwhile, the latest migration time of the signals at each circuit node is calculated in the reverse topological order. The latest migration time represents the latest time at which the signal must complete processing at this node, and static timing analysis is performed using the calculated arrival time and the latest migration time. By comparing the arrival time with the latest transition time, it can be determined whether the signal meets timing requirements, thereby evaluating the performance and stability of the circuit.

The process is an exemplary topological ordering whole flow, and the graph traversal-based time sequence analysis method provided by the invention has a remarkable effect in static time sequence analysis. Compared with the traditional multi-traversal method, the method has the advantages that the traversal times are reduced, the calculation redundancy is eliminated, and the stability and predictability of the circuit are improved. Firstly, topology sequencing, loop detection and loop breaking are realized through one-time traversal, so that the calculation redundancy in static time sequence analysis is successfully eliminated, the operation efficiency of circuit design is greatly improved, and the time sequence analysis is quicker and more efficient. Second, implementation of this method reduces computational costs, providing a more cost-effective circuit verification and optimization means for the designer. In addition, the introduced loop breaking step helps to improve the stability of the circuit, ensuring reliable operation under various operating conditions. In general, the innovative approach of this patent will drive the advancement of Electronic Design Automation (EDA) tools, bringing more advanced timing analysis tools into the field of circuit design.

The embodiment also provides a time sequence analysis device based on graph traversal, which is used for realizing the embodiment and the preferred implementation, and the description is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a timing analysis device based on graph traversal, as shown in fig. 7, including:

the node diagram generating module 401 is configured to obtain a description file of the target circuit, generate a corresponding directed node diagram according to the description file, and use directed edges of each node in the directed node diagram to connect with subsequent nodes of each node;

a traversal access module 402, configured to determine a start node, and perform traversal access on each node in the directed node map based on the start node and the directed edges of each node;

the broken ring processing module 403 is configured to remove a directed edge between a repeated access node and a previous access node when the repeated access node appears in the process of traversing access, and return to the previous access node to continue traversing access;

The topology sequencing module 404 is configured to determine that the current node accesses the target circuit if there are no non-accessed successor nodes in the current node, and return to a previous access node of the current node to continue traversing the access until all nodes access the target circuit, and obtain a topology sequencing result for the target circuit according to a time sequence of completing the access of each node;

the timing analysis module 405 is configured to perform static timing analysis on the target circuit based on the topology ordering result.

In some alternative embodiments, traversing access to each node in the graph of directed nodes based on the starting node and the directed edges of each node includes:

In some optional embodiments, in the process of traversing access, when a repeated access node appears, removing a directed edge between the repeated access node and a last access node, and returning to the last access node to continue traversing access, including:

In some alternative embodiments, the last access node to fall back to the current node continues the traversal access, including:

In some optional embodiments, obtaining the topology ordering result for the target circuit according to the time sequence of the access completion of each node includes:

In some alternative embodiments, static timing analysis of the target circuit based on the topology ordering result includes:

according to the topology sequencing result and the signal transmission condition in the target circuit, calculating to obtain the arrival time and the latest migration time of each node;

In some optional embodiments, calculating the arrival time and the latest migration time of each node according to the topology ordering result and the signal transmission condition in the target circuit includes:

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The graph traversal-based timing analysis apparatus in this embodiment is presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit ) circuits or FPGA (Field Programmable Gate Array, field programmable gate array) circuits, processors and memories that execute one or more software or firmware programs, and/or other devices that can provide the above functions.

The embodiment of the invention also provides a computer device which is provided with the time sequence analysis device based on graph traversal shown in the figure 7.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 8, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 8.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 8.

The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointer stick, one or more mouse buttons, a trackball, a joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A graph traversal-based timing analysis method, the method comprising:

2. The method of claim 1, wherein the traversing access to each node in the directed node graph based on the starting node and the directed edges of each node comprises:

3. The method according to claim 2, wherein the removing the directed edge between the repeated access node and the last access node and returning to the last access node to continue the traversal access when the repeated access node appears during the traversal access comprises:

4. The method of claim 1, wherein the returning to the last access node of the current node continues traversing the access, comprising:

5. The method of claim 1, wherein the obtaining the topology ordering result for the target circuit according to the time sequence in which the nodes access is completed comprises:

6. The method of claim 1, wherein the performing static timing analysis on the target circuit based on the topology ordering result comprises:

7. The method of claim 6, wherein the calculating the arrival time and the latest migration time of each node according to the topology ordering result and the signal transmission condition in the target circuit includes:

8. A graph traversal-based timing analysis apparatus, the apparatus comprising:

9. A computer device, comprising:

a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the graph traversal-based timing analysis method of any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the graph traversal-based timing analysis method of any one of claims 1-7.