CN117785762A

CN117785762A - Information storage method, device, equipment and storage medium

Info

Publication number: CN117785762A
Application number: CN202311629219.3A
Authority: CN
Inventors: 陈绍银; 张匆; 卢文岩; 张涛; 蒋帅; 张丰涛; 竺杨明
Original assignee: Yusur Technology Co ltd
Current assignee: Yusur Technology Co ltd
Priority date: 2023-11-30
Filing date: 2023-11-30
Publication date: 2024-03-29

Abstract

The invention relates to an information storage method, an information storage device and a storage medium, wherein the information storage method comprises the following steps: receiving current response information, wherein the current response information comprises a target identifier of a target queue pair with a data receiving and transmitting processing function; acquiring state information corresponding to the target identifier, wherein the state information is used for recording parameter information of last response information generated by the target queue pair and stored in a first storage space, and the first storage space is used for storing various response information of a plurality of queue pairs; and determining a target storage address of the current response information in the first storage space based on the state information, and storing the current response information to the target storage address. The method provided by the disclosure can effectively reduce the consumption of storage resources while rapidly and orderly storing the response information.

Description

Information storage method, device, equipment and storage medium

Technical Field

The present invention relates to the field of information processing technologies, and in particular, to an information storage method, apparatus, device, and storage medium.

Background

With the wide application of network technology, in order to improve the network channel utilization, a remote direct memory access (Remote Direct Memory Access, RDMA) protocol adopts an Acknowledgement (ACK) aggregation mechanism, which is a mechanism that the receiving end selectively reduces sending response packets under the condition that the sending end does not influence the receiving condition of judging that the sending packet is received at the receiving end, that is, the middle response packets are directly aggregated into the latest necessary response packets, and each response packet is not sent separately, so that the data flow of the response packets is reduced, and the transmission efficiency of the network channel is improved.

RDMA is a Queue Pair (QP) based transmit receive traffic processing protocol, where each QP queue Pair can perform data transceiving processing. Currently, in the case where a plurality of queue pairs simultaneously generate response packet request information, the response packet request information of each queue pair is stored in a separate random access memory (Random Access Memory, RAM), resulting in a large consumption of memory resources.

Disclosure of Invention

In order to solve the technical problems, the embodiments of the present disclosure provide an information storage method, apparatus, device, and storage medium, which effectively reduce storage resource consumption while storing response information in a quick and orderly manner.

In a first aspect, an embodiment of the present disclosure provides an information storage method, including:

receiving current response information, wherein the current response information comprises a target identifier of a target queue pair with a data receiving and transmitting processing function;

acquiring state information corresponding to the target identifier, wherein the state information is used for recording parameter information of last response information generated by the target queue pair and stored in a first storage space, and the first storage space is used for storing various response information of a plurality of queue pairs;

And determining a target storage address of the current response information in the first storage space based on the state information, and storing the current response information to the target storage address.

In a second aspect, an embodiment of the present disclosure provides an information storage device, including:

the receiving unit is used for receiving current response information, wherein the current response information comprises a target identifier of a target queue pair with a data receiving and transmitting processing function;

the acquisition unit is used for acquiring state information corresponding to the target identifier, wherein the state information is used for recording parameter information of last response information generated by the target queue pair and stored in a first storage space, and the first storage space is used for storing various response information of a plurality of queue pairs;

and the storage unit is used for determining a target storage address of the current response information in the first storage space based on the state information and storing the current response information to the target storage address.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including:

a memory;

a processor; and

a computer program;

wherein the computer program is stored in the memory and configured to be executed by the processor to implement the information storage method as described above.

In a fourth aspect, the disclosed embodiments provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the information storage method as described above.

The embodiment of the disclosure provides an information storage method, which comprises the following steps: receiving current response information, wherein the current response information comprises a target identifier of a target queue pair with a data receiving and transmitting processing function; acquiring state information corresponding to the target identifier, wherein the state information is used for recording parameter information of last response information generated by the target queue pair and stored in a first storage space, and the first storage space is used for storing various response information of a plurality of queue pairs; and determining a target storage address of the current response information in the first storage space based on the state information, and storing the current response information to the target storage address. According to the method provided by the disclosure, the first storage space capable of storing various response information generated by various queue pairs is deployed, and the storage state information of each queue pair in the first storage space is recorded, so that the response information can be stored rapidly and orderly, and meanwhile, the consumption of storage resources is effectively reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic diagram of response packet aggregation and network packet loss according to an embodiment of the disclosure;

fig. 2 is a schematic flow chart of an information storage method according to an embodiment of the disclosure;

fig. 3 is a flowchart illustrating another information storage method according to an embodiment of the present disclosure;

FIG. 4 is a block diagram of an information processing architecture provided by an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of an information storage device according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.

Specifically, RDMA is a QP-based transmit-receive service processing protocol, each QP queue pair may perform data transceiving processing, and the message processing order of the same QP follows a sequence-preserving rule (i.e. if the request information order is 1 to N, then the processing order is also 1 to N), and the message processing order between different QPs is not required. Specifically, each QP consists of two queues, namely a Send Queue (SQ) and a Receive Queue (RQ).

In the RDMA protocol processing process, for reliable connection services such as reliable connection (Reliable Connection, RC), extended reliable connection (Reliable Connection, XRC), reliable data table (Reliable Datagram, RD), and the like, in order to confirm the condition that the receiving end receives the message, each service request sent by the sending end needs to reply to the corresponding response packet by the receiving end. In an RDMA system, a data path for replying a response packet and a data path for actively sending request information by SQ are the same path, and there is a contention waiting condition for data sending between the two paths. Thus, RDMA systems require buffering of response packets, subject to channel bandwidth and scheduling requirements, etc.

The response packet is used as a guarantee mechanism for reliable connection service, and mainly comprises the following messages.

(1) Response message (read response): corresponding to a read request (read request), the read request is responsible for carrying the data requested by the read request; specifically, the method comprises a normal read request response packet and a repeated read request response packet.

(2) Atom ACK (atomic ACK): corresponding to the atomic request, carrying atomic response data; specifically atomic CmpSwap ACK and atomic FetchAdd ACK.

(3) Acknowledgement (ACK): corresponding to send and write operations, the sender is responsible for informing that the request message is correctly received; specifically, the send ACK and the write ACK are included.

(4) Negative acknowledgement (negative acknowledgment, NAK): NAK exists in all operation types of the reliable connection service, namely NAK packets are responded when errors occur in the reception; specifically including plain NAK and RNR NAK; the RNR NAK refers to resources required for the receiving end not to be ready to receive data, but without errors; the normal NAK data packet has errors, and the NAK data frame contains error codes.

(5) Congestion Notification Packet (CNP): corresponding to the data packet with ECN congestion mark, is used for informing the opposite end of packet sending and decelerating.

At present, in order to improve the network channel utilization rate, the RDMA protocol adopts a mechanism called ACK aggregation, that is, when the receiving end replies to the request of the transmitting end, the receiving end can choose to reply only the latest necessary response packet, and for the middle response packet, the latest necessary response packet is directly aggregated, and is not separately transmitted, so that the data traffic of the response packet is reduced. When the transmitting end receives the latest response packet, the response packet which is aggregated can be deduced through a packet sequence (packet sequence number, PSN), a message sequence (Message Sequence Number, MSN), an operation type and the like, so that the receiving condition of the request message at the receiving end can be judged. This way of aggregation can only aggregate ACKs, i.e. response packets containing error information cannot be aggregated, and is therefore called ACK aggregation.

The ACK aggregation refers to a mechanism that the receiving end selectively reduces the sending response packet under the condition that the sending end does not influence the receiving condition of the sending end to judge that the sending packet is received at the receiving end. ACK aggregation follows several principles:

1) The aggregated data packets must be ACK response packets. Response packets with error information such as common NAK, RNR NAK and the like cannot be aggregated, otherwise, the sending end cannot judge the receiving condition of the data packet; response packets carrying data information such as an Atomic ACK and a read response cannot be aggregated, otherwise service data is lost; and discarding old ACK when the ACK is aggregated, and reserving the latest response packet.

2) The AckReq identified ACKs cannot be aggregated.

Referring to fig. 1, fig. 1 is a schematic diagram of response packet aggregation and network packet loss according to an embodiment of the disclosure, and fig. 1 is used for explaining a case where a transmitting end (request) determines data received by a receiving end (request). In fig. 1, r (request) represents a request, and a (response) represents a response. As can be seen from the figure, the transmitting end continuously transmits 4 requests, namely send (r 1), send (r 2), read (r 3) and send (r 4) in sequence. The receiving end correctly receives all requests and completes the response, the ACK positive responses of the first two send requests r1 and r2 are aggregated, and the ACK of the two requests is implicitly confirmed by a read response. However, due to network packet loss, the transmitting end does not receive the read response (a 3) responded by the receiving end, but receives the ACK (a 4) of the fourth request (r 4). In this case, the determination after the transmitting end receives a4 is: 1) And a4 is received, which indicates that all the packets are received correctly by the receiving end before. 2) The send request type ACK sent by the sending end can be aggregated, and the read response ACK cannot be aggregated, so that the r1 and r2 ACK can be aggregated by the r3 read response, and even if a1 and a2 are not received, the r1 and r2 tasks can be implicitly confirmed to be completed correctly. 3) Since read responses cannot be aggregated, there is an error in implicit confirmation r3, requiring retransmission. 4) Based on a message order-preserving mechanism, the sending end needs to resend r3 and r4, and the order-preserving mechanism is used for guaranteeing the order of sending each request to the receiving end by the sending end.

Generally, if multiple QPs generate the response packet request information at the same time, they will do the following for the response packet request information: storing the response packet of each QP into an independent RAM, and recording the corresponding relation between the RAM and the QP; each RAM needs an address maintenance mechanism to ensure the first-in first-out so as to achieve the effect of a first-in first-out storage structure (First in First out, FIFO); every time the response packet is written into the RAM, the type of the response packet needs to be recorded; when the response packet arrives each time, whether the last request type can be aggregated or not needs to be judged, if so, the last address is written, and if not, a new address is written, so that the aggregation function is completed; the RAM maintenance mechanism needs to provide RAM storage status, read interface externally.

However, the above method for requesting information for the response packet has the following problems: each QP corresponds to an independent RAM, and the consumption of storage resources is large; one address maintenance mechanism per QP, resulting in a large register consumption; when a response packet is output to the transmitting end, the precedence relationship cannot be determined by the request information among the plurality of QPs.

In view of the above technical problems, an embodiment of the present disclosure provides an information storage method, which may receive various response packet request information such as ACK, NAK, atomic ACK, read response, etc., that is, may store various types of response information. And secondly, a first storage space capable of sequentially storing various response packet request information (hereinafter referred to as response information) generated by a plurality of QPs is constructed, and state information of the latest response information stored in the first storage space by each QP is recorded, namely, response packet ACK aggregation processing is realized according to a response packet aggregation mechanism while response information caching work is finished, namely, a coalesce RAM and a state RAM which can be shared by a plurality of QPs simultaneously are constructed, and the ACK aggregation function is finished while storage resources are saved. In addition, a storage state and a storage reading interface are externally provided. Through the processing, the requirement that a plurality of QPs simultaneously generate response packet request information can be met, and the consumption of storage resources and registers is reduced. And in particular by one or more of the following examples.

Fig. 2 is a flow chart of an information storage method provided in an embodiment of the present disclosure, applied to a terminal or a server, where a logic block (RAM ctrl) is deployed in the server, and in a scenario of storing response information into a first storage space, an aggregate processing function of all QPs is implemented based on the RAM ctrl, so that control consumption logic resources are effectively reduced, and specifically includes steps S201 to S203 shown in fig. 2:

s201, receiving current response information, wherein the current response information comprises a target identifier of a target queue pair with a data receiving and transmitting processing function.

It can be understood that, response packet request information sent by a receiving end (receiving queue) in the target queue pair is recorded as current response information, where the target queue pair refers to QP with a data receiving and transmitting function, and the current response information refers to response information generated after the receiving end receives request information (sending packet) sent by a sending end (sending queue) in the target queue pair, and is used for characterizing a receiving condition of the sending packet at the receiving end. The current response message may be any of the above types of response packet messages, and the current response message includes a target identifier of the target queue pair, where the target identifier may be a QP number, or other identifier capable of identifying the queue pair, which is not limited herein.

S202, acquiring state information corresponding to the target identifier.

The state information is used for recording parameter information of last response information generated by the target queue pair and stored in a first storage space, and the first storage space is used for storing various response information of a plurality of queue pairs.

It can be understood that, on the basis of S201, a third storage space is previously constructed, and the third storage space may be understood as a state storage RAM (hereinafter referred to as a state RAM), which is used to record the state information of the latest response information stored in the first storage space by each queue pair, where the latest response information may be indexed according to the target identifier (QP serial number) in the third storage space, and the latest response information may be specifically understood as the last response information of the current response information.

The state information comprises an effect identifier, a storage address of the last response information in the first storage space and an information type of the last response information, wherein the effect identifier is used for identifying whether the response information generated by the target queue pair is stored in the first storage space or not, and the effect identifier is an invalid identifier or a valid identifier.

It can be understood that the status information specifically includes an information type of the latest response information, a storage address in the first storage space, and an effect identifier for characterizing a situation that the queue pair is stored in the first storage space, and is correspondingly denoted as last_type/last_addr/last_vld, where the status information is used for assisting in completing ACK aggregation. Wherein last_type represents an information type of the latest response information for judging whether the response information can be aggregated, and specifically, information type last_type=1 indicates that the response information can be aggregated, and last_type=0 indicates that the response information cannot be aggregated; the storage address last_addr represents the storage address (storage position) of the latest response information in the first storage space (coalesce RAM), if the latest response information can be aggregated, the current response information can be directly stored in the storage position, and the latest response information can be aggregated; the effect flag last_vld represents whether the latest response information is valid, that is, whether the QP generating the latest response information exists in the coalesce RAM, that is, whether the first storage space stores the response information of the QP, specifically, last_vld=1 indicates that the response information of the QP exists in the coalesce RAM, at this time, the effect flag is a valid flag, last_vld=0 indicates that the response information of the QP does not exist in the coalesce RAM, and the effect flag is an invalid flag.

S203, determining a target storage address of the current response information in the first storage space based on the state information, and storing the current response information at the target storage address.

It is understood that, based on the above parameter information included in the state information, the target storage address of the current response information in the first storage space is determined, where in one possible case, if it is determined that the current response information can be aggregated, the target storage address is the storage address of the previous response information in the first storage space, and in another possible case, the current response information is an information type that cannot be aggregated, for example, NAK type, the address to be allocated in the first storage space is determined as the target storage address, and the address to be allocated refers to the address in the first storage space to which any response information can be allocated and stored. After the target storage address is determined, the current response information is stored to the target storage address.

It can be appreciated that a third register is pre-constructed, and the third register is used for temporarily storing the current response information after receiving the current response information and before determining the target storage address. Correspondingly, the current response information is read from the third register to the target storage address. Or, after determining the target storage address, the handshake successfully stores the current response information to the target storage address by adopting a handshake mechanism.

In one embodiment, the address to be allocated is denoted as wr_addr, and from wr_addr=0, each response message is written in the first storage space, where wr_addr is added with 1, and wr_addr=1 as the address that can be allocated for the next response message. And so on, until wr_addr is equal to the maximum value, the storage is resumed from wr_addr=0, the maximum value is understood as the last storable address in the first storage space, for example, 10 storable addresses exist in the first storage space, wr_addr=9 indicates that one cycle of storage is completed, and the response information stored in the first storage space is read out based on the storage order (the order of 0 to 9), so that the storage in the next cycle can be continued from 0.

Optionally, the determining, in S203, the target storage address of the current response information in the first storage space based on the state information may specifically be implemented by the following steps:

under the condition that the effect identifier is an invalid identifier, acquiring an address to be allocated of the first storage space, and taking the address to be allocated as a target storage address; or determining the target storage address according to the storage address of the last response information and the information type of the last response information under the condition that the effect identifier is a valid identifier.

It can be understood that, according to the aggregation mechanism, the target storage address of the response information in the first storage space is determined, which specifically includes the following procedures: in the case where the effect flag is determined to be an invalid flag, that is, last_vld=0, that is, there is no response information of the QP in the coalesce RAM, the address to be allocated is taken as the target storage address, that is, the current response information is written into wr_addr in the coalesce RAM, and the address to be allocated is updated, that is, wr_addr is added with 1. In the case where the effect flag is determined to be a valid flag, that is, last_vld=1, that is, the response information of the QP is stored in the coalesce RAM, the flow of determining the target storage address is as follows.

Optionally, the determining the target storage address according to the storage address of the previous response message and the message type of the previous response message may be specifically implemented by the following steps:

determining the information type of the current response information, wherein the information type is a polymerizable type or a non-polymerizable type; when the information type of the current response information is the same as the information type of the last response information and the information type is the polymerizable type, taking the storage address of the last response information as the target storage address; or, in the case that the information type of the current response information and the information type of the last response information are different, taking the address to be allocated as the target storage address.

It can be understood that, the information type of the current response information is determined, the information type is a polymerizable type or a non-polymerizable type, if the information type is a polymerizable type, that is, last_type=1, that is, the current response information is a polymerizable ACK, the storage address of the last response information in the coalesce RAM is used as a target storage address, that is, last_addr is used as a target storage address, and the last response information is written into the coalesce RAM. Or if the information type is of a non-polymerizable type, that is, last_type=0, that is, the current response information is ACK of non-polymerizable, the address to be allocated is written into the coalesce RAM as the target storage address, and the wr_addr is added with 1.

In one possible embodiment, the determining the target storage address according to the storage address of the previous response message and the message type of the previous response message may specifically be implemented by the following steps:

taking the storage address of the last response information as the target storage address under the condition that the information type of the last response information is an aggregatable type; or, in the case that the information type of the last response information is a non-polymerizable type, the address to be allocated is used as the target storage address.

It can be understood that if the information type of the previous response information is the polymerizable type, the storage address of the previous response information may be directly used as the target storage address, and the current response information covers the previous response information stored at the target storage address, where in this case, the judgment after the sender receives the current response information is as follows: and receiving current response information, wherein the current response information indicates that all the request packets sent before have been correctly received by the receiving end.

Optionally, after determining the target storage address of the current response information in the first storage space, updating the state information may specifically be implemented by the following steps:

setting an effect identifier in the state information as a first parameter value, wherein the first parameter value indicates that the effect identifier is an effective identifier; and updating the state information according to the target storage address, the information type of the current response information and the first parameter value.

It can be understood that, after determining the target storage address or finishing the storage of the current response information, updating the state information of the target queue pair recorded in the third storage space, that is, taking the current response information as the latest response information of the target queue pair, writing the relevant information of the latest response information into the state RAM, specifically, writing the current state information into the target storage address used when writing the current state information into the coalesce RAM, and writing the last_addr of the state RAM; writing the information type of the current state information into the last_type, namely the current response information can be aggregated, setting the last_type as a first parameter value, otherwise setting the last_type as a second parameter value, preferably, the first parameter value is 1, and the second parameter value is 0; the valid state of the response information of the QP stored in the coalesce RAM is written into last_vld, i.e., last_vld is set to 1.

According to the information storage method provided by the embodiment of the disclosure, the response information is received, the response information is cached to the coalesce RAM, and meanwhile ACK aggregation processing is carried out in the coalesce RAM. According to the method, the cache processing of the response information is completed based on the coalesce RAM shared by the QPs, RAM does not need to be allocated for each QP independently, the resource consumption is effectively reduced, the ACK aggregation function of the response information is realized, and the network channel utilization rate is improved. And a state RAM is constructed for address maintenance, so that an address maintenance mechanism is not required to be set for each QP, and the consumption of registers is effectively reduced.

On the basis of the above embodiment, fig. 4 is a flowchart of another information storage method according to the embodiment of the present disclosure, after storing the current response information at the target storage address, the method reads the response information stored in the first storage space to the second storage space, and specifically includes the following steps S401 to S402 as shown in fig. 4:

the second storage space comprises a plurality of subspaces in parallel, each subspace stores response information generated by a queue pair at the same time, the second storage space is provided with a first-in first-out storage structure, and a storage state and a reading interface are provided for the outside.

It can be understood that the second storage space is pre-constructed, the second storage space can be understood as a parallel FIFO, the second storage space includes a plurality of parallel subspaces, that is, the parallel FIFO is a plurality of parallel FIFO storage structures, and stores the response information from the first storage space, and each FIFO stores the response information of only one QP at the same time, that is, the response information is transferred from the coalesce RAM to the parallel FIFO with only one channel. The parallel FIFO has a first-in first-out memory structure, and can provide a memory state and a read interface to the outside (transmitting end).

S401, acquiring an address to be read of the first storage space.

It can be understood that, the address to be read of the first storage space is obtained, and the address to be read is the address to be read from the first storage space to the second storage space next, and is denoted as rd_addr, where the updating modes of rd_addr and wr_addr are the same, and the updating mode starts from rd_addr=0, and each time a response message is read, the address of rd_addr is added by one, that is, rd_addr=1, as the address of the next data to be read. It will be appreciated that in the order of writing and reading from 0 to 9, the rd_addr is less than or equal to the wr_addr, i.e. the data is stored before being read, in the same period, i.e. the rd_addr is in the last period and the wr_addr is in the latest period, in which case the sizes of the rd_addr and the wr_addr are variable.

And S402, reading the current response information to a second storage space under the condition that the address to be read is the same as the target storage address.

It can be understood that, on the basis of S401, when the address to be read is the same as the target storage address, that is, after the current response information is written into the target storage address, the current response information is read out, where the current response information may be aggregated, or the address to be read is the same as the address to be allocated, that is, writing and reading are synchronous, and the current response information is read into the second storage space.

The second storage space further comprises at least one first register and a second register, the first register is used for recording the corresponding relation between the queue pair and the subspace, and the second register is used for temporarily storing the response information before determining the subspace corresponding to the response information.

Optionally, in S402, the reading of the current response information to the second storage space may be specifically implemented by the following steps:

reading the current response information to the second register under the condition that the address to be allocated and the address to be read of the first storage space are different; and determining a target subspace in the subspaces according to the corresponding relation, and reading the current response information from the second register to the target subspace.

It can be understood that the blank state of the coalesce RAM is judged by the address to be allocated and the address to be read, if the address to be allocated and the address to be read are different, namely wraddr-! =rd_addr, it indicates that the coalesce RAM is not empty in the area of rd_addr to wr_addr, that is, there is response information that has not been read by the coalesce RAM. If the address to be allocated and the address to be read are different, and wr_addr=rd_addr-1, it indicates that the coalesce RAM is full, that is, writing is more than reading by one cycle, and there is a large amount of unread response information in the coalesce RAM. When the coalesce RAM is not empty, that is, there is a response message that can be moved to the second storage space, and the response message is the current response message, in this case, the response message (current response message) at rd_addr is read and buffered in the second register. And determining a target subspace in the subspaces according to the corresponding relation between the subspaces recorded by each first register and the QP, and moving the current response information from the second register to the target subspace, wherein the current response information does not exist in the first storage space. It is understood that there is a corresponding first register in each subspace, or, a plurality of subspaces correspond to a first register, that is, the corresponding relationship between QP and subspace is implemented by using a register array, each first register records the QP number stored in the first register, and each subspace can be understood as a queue. It can be understood that the target subspace follows the first-in-first-out principle, that is, the response information stored in the subspace first is acquired by the transmitting end, and specifically, the transmitting end acquires the response information in the corresponding subspace through the reading interface of the second memory.

It can be understood that the response information in the coalesce RAM participates in aggregation, and the response information that has been read (moved) into the parallel FIFO does not participate in aggregation, and is directly read into the FIFO corresponding to the QP in sequence. For different response information, the write operation and the read operation for the first memory space may be performed simultaneously.

Optionally, determining the target subspace among the multiple subspaces according to the correspondence relation specifically may be implemented by the following steps:

determining whether an initial subspace exists in the second storage space according to the corresponding relation, wherein the initial subspace is used for storing the previous response information of the target queue pair; determining the initial subspace as the target subspace when the initial subspace exists in the second storage space and the storage space of the initial subspace is not full; alternatively, in a case where the initial subspace does not exist in the second storage space and a free subspace exists in the second storage space, the free subspace is determined as the target subspace.

It can be understood that, according to the first register that records the correspondence between the subspace and the queue pair, it is determined whether there is an initial subspace in the subspaces, where the initial subspace is the subspace in which the response information before the target queue pair is stored, that is, the first register that compares the correspondence between the parallel FIFO queue and the QP, and determines whether the response information of the QP is stored before in the parallel FIFO. Under the condition that the second storage space is provided with an initial subspace and the storage space of the initial subspace is not full, determining the initial subspace as a target subspace, namely, the parallel FIFO queue is provided with the response information of the QP, and if the queue is not full, directly writing the response information into the queue; or under the condition that the second storage space does not have the initial subspace and the second storage space has the free subspace, determining the free subspace as the target subspace, namely, the response information of the QP is not stored in the parallel FIFO, and the free queue exists in the parallel FIFO, directly writing the response information into the free queue, and recording the corresponding relation between the QP and the free queue, namely, writing the QP sequence number into a first register corresponding to the free queue.

Optionally, the method further comprises:

and if the second storage space is full of the initial subspace or if the second storage space is free of the free subspace, suspending the reading operation of reading the response information from the first storage space to the second storage space, and temporarily storing the current response information in the second register.

It can be appreciated that in the case where the second memory space has an initial subspace and the memory space of the initial subspace is full, that is, the current response information cannot be written into the queues, or in the case where the second memory space does not have a free subspace, that is, all queues in the parallel FIFO have stored the response information of each QP. In this case, the read operation of reading the response information from the first storage space to the second storage space, that is, the back pressure read data operation (suspension operation) is suspended, and the current response information is suspended in the second register until the storage space of the initial subspace is not full or the second storage space has a free subspace, and the current response information is written into the parallel FIFO.

Optionally, when the address to be read and the target storage address are different, that is, the next read is not the current response information, the state RAM information needs to be updated immediately, which can be achieved specifically by the following steps:

Determining a first queue pair for generating first response information stored at the address to be read; and setting an effect identifier in the state information corresponding to the first queue pair as a second parameter value under the condition that the storage address of the first storage space and the address to be read are the same in the last response information recorded in the state information corresponding to the first queue pair, wherein the second parameter value indicates that the effect identifier is an invalid identifier.

It can be understood that the first queue pair generating the first response information stored at the address to be read is determined, in the case that the storage address of the last response information recorded in the state information corresponding to the first queue pair is the same as the address to be read, that is, last_addr and rd_addr of the first response information recorded in the state RAM are equal, it means that the coalesce RAM has no response information of the QP, that is, the last response information (first response information) stored in the first storage space of the first queue pair is to be moved to the second storage space, in this case, last_vld is set to a second parameter value, which may be 0, the second parameter value means that the target is represented as an invalid identifier, otherwise, the state RAM is not updated.

According to the information storage method provided by the embodiment of the disclosure, parallel FIFOs are constructed to improve the parallelism of processing response packets and prevent mutual blocking between QPs. After receiving the response information, the response information is stored in the coalesce RAM and then is stored in the parallel FIFO, so that the occupied memory space of the parallel FIFO is small, namely the occupied memory resource is small. And the response information is output in parallel with the FIFO, and the sequence of the output of the response information is reserved due to the sequence of the first-in first-out of the coalesce RAM.

On the basis of the above embodiment, referring to fig. 4, for example, fig. 4 is a block diagram of an information storage system provided in an embodiment of the disclosure, where the information storage system includes a first storage space (coalesce RAM), a second storage space (parallel FIFO), a third storage space (state RAM), and a processing logic control block (RAM ctrl), where the coalesce RAM is used for primarily storing response information of a plurality of QPs, and implementing an ACK aggregation function of the plurality of QPs in a storage process. The parallel FIFO is used to store response information and provide response information for multiple QPs externally. The state RAM is used for storing information such as last_type/last_addr/last_vld and the like, and the state information is used for assisting in completing ACK aggregation. The RAM ctrl is used for executing the information storage method, and is particularly used for distributing the storage address in the coalesce RAM for the response information, recording the read address in the coalesce RAM, recording the empty and full state of the coalesce RAM and moving the response information stored in the coalesce RAM to the parallel FIFO.

It can be appreciated that the workflow of writing the response information into the coalesce RAM is as follows: 1) Initializing: initializing a state RAM, setting initial values of all parameters of the state RAM to 0, and setting wraddr in the RAM ctrl to zero. 2) And receiving response information, and inquiring state information in the state RAM according to the QP sequence number. 3) And writing the response information into the coalesce RAM according to the aggregation mechanism, and performing caching and aggregation processing. 4) The state RAM is updated.

It can be appreciated that the workflow of response information from the coalesce RAM to the parallel FIFO: 1) Initializing: setting rd_addr in RAM ctrl to zero, resetting a register recording the corresponding relation between a parallel FIFO queue and QP, resetting the parallel FIFO, and setting a coalesce RAM read enable strobe signal to 1 and not to be null, wherein it is understood that only one strobe signal for transmission exists in the coalesce RAM and the parallel FIFO, and when response information is written into the FIFO queue, the coalesce RAM read enable strobe signal is pulled high to support the next read operation. 2) And reading the response information stored in the coalesce RAM. 3) And writing the read response information into the parallel FIFO. 4) The state RAM information is updated.

It can be understood that the specific implementation steps of the writing process and the reading process are referred to the above embodiments, and are not repeated herein.

Fig. 5 is a schematic structural diagram of an information storage device according to an embodiment of the present disclosure. The information storage apparatus provided in the embodiment of the present disclosure may execute a processing flow provided in the embodiment of the information storage method, as shown in fig. 5, where the information storage apparatus 500 includes a receiving unit 501, an obtaining unit 502, and a storage unit 503, where:

a receiving unit 501, configured to receive current response information, where the current response information includes a target identifier of a target queue pair having a data transceiving processing function;

an obtaining unit 502, configured to obtain status information corresponding to the target identifier, where the status information is used to record parameter information of previous response information generated by the target queue pair and stored in a first storage space, and the first storage space is used to store multiple response information of multiple queue pairs;

and a storage unit 503, configured to determine a target storage address of the current response information in the first storage space based on the state information, and store the current response information to the target storage address.

Optionally, the status information in the apparatus 500 includes an effect identifier, a storage address of the last response information in the first storage space, and an information type of the last response information, where the effect identifier is used to identify whether response information generated by the target queue pair is stored in the first storage space, and the effect identifier is an invalid identifier or a valid identifier.

Optionally, the storage unit 503 is configured to:

under the condition that the effect identifier is an invalid identifier, acquiring an address to be allocated of the first storage space, and taking the address to be allocated as a target storage address; or,

and under the condition that the effect identifier is a valid identifier, determining the target storage address according to the storage address of the last response information and the information type of the last response information.

Optionally, the storage unit 503 is configured to:

determining the information type of the current response information, wherein the information type is a polymerizable type or a non-polymerizable type;

when the information type of the current response information is the same as the information type of the last response information and the information type is the polymerizable type, taking the storage address of the last response information as the target storage address; or, in the case that the information type of the current response information and the information type of the last response information are different, taking the address to be allocated as the target storage address.

Optionally, the apparatus 500 is further configured to:

setting an effect identifier in the state information as a first parameter value, wherein the first parameter value indicates that the effect identifier is an effective identifier;

And updating the state information according to the target storage address, the information type of the current response information and the first parameter value.

Optionally, the apparatus 500 is further configured to:

acquiring an address to be read of the first storage space, and reading the current response information to a second storage space under the condition that the address to be read is the same as the target storage address;

Optionally, the second storage space in the apparatus 500 further includes at least one first register and a second register, where the first register is configured to record a correspondence between a queue pair and a subspace, and the second register is configured to temporarily store the response information before determining the subspace corresponding to the response information.

Optionally, the apparatus 500 is further configured to:

reading the current response information to the second register under the condition that the address to be allocated and the address to be read of the first storage space are different;

And determining a target subspace in the subspaces according to the corresponding relation, and reading the current response information from the second register to the target subspace.

Optionally, the apparatus 500 is further configured to:

determining whether an initial subspace exists in the second storage space according to the corresponding relation, wherein the initial subspace is used for storing the previous response information of the target queue pair;

determining the initial subspace as the target subspace when the initial subspace exists in the second storage space and the storage space of the initial subspace is not full; or,

in the case where the second storage space does not have the initial subspace and the second storage space has a free subspace, the free subspace is determined as the target subspace.

Optionally, the apparatus 500 is further configured to:

determining a first queue pair for generating first response information stored at the address to be read;

and setting an effect identifier in the state information corresponding to the first queue pair as a second parameter value under the condition that the storage address of the first storage space and the address to be read are the same in the last response information recorded in the state information corresponding to the first queue pair, wherein the second parameter value indicates that the effect identifier is an invalid identifier.

The information storage device of the embodiment shown in fig. 5 may be used to implement the technical solution of the above-mentioned method embodiment, and its implementation principle and technical effects are similar, and will not be described herein again.

Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure. Referring now in particular to fig. 6, a schematic diagram of an electronic device 600 suitable for use in implementing embodiments of the present disclosure is shown. The electronic device 600 in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and the like, and fixed terminals such as digital TVs, desktop computers, smart home devices, and the like. The electronic device shown in fig. 6 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.

As shown in fig. 6, the electronic device 600 may include a processing means (e.g., a central processing unit, a graphic processor, etc.) 601, which may perform various suitable actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage means 608 into a Random Access Memory (RAM) 603 to implement an information storage method of an embodiment as described in the present disclosure. In the RAM 603, various programs and data required for the operation of the electronic apparatus 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

In general, the following devices may be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608 including, for example, magnetic tape, hard disk, etc.; and a communication device 609. The communication means 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. While fig. 6 shows an electronic device 600 having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.

In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts, thereby implementing the information storage method as described above. In such an embodiment, the computer program may be downloaded and installed from a network via communication means 609, or from storage means 608, or from ROM 602. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by the processing device 601.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

In some implementations, the clients, servers may communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol ), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the internet (e.g., the internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

Alternatively, the electronic device may perform other steps described in the above embodiments when the above one or more programs are executed by the electronic device.

Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including, but not limited to, an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or gateway that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or gateway. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or gateway comprising the element.

The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An information storage method, comprising:

2. The method of claim 1, wherein the status information includes an effect flag for indicating whether response information generated by the target queue pair is stored in the first storage space, the effect flag being an invalid flag or a valid flag,

the determining, based on the status information, a target storage address of the current response information in the first storage space includes:

3. The method of claim 2, wherein the determining the target memory address based on the memory address of the last response message and the message type of the last response message comprises:

4. The method of claim 1, wherein after determining the target memory address of the current response message in the first memory space, the method further comprises:

5. The method of claim 1, wherein after storing the current response information at the target storage address, the method comprises:

acquiring an address to be read of the first storage space;

reading the current response information to a second storage space under the condition that the address to be read is the same as the target storage address;

6. The method of claim 5, wherein the second memory space further comprises at least one first register and a second register, the first register being configured to record a correspondence between a queue pair and a subspace, the second register being configured to register the response information before determining the subspace to which the response information corresponds;

The reading the current response information to the second storage space includes:

7. The method of claim 6, wherein determining a target subspace among the plurality of subspaces according to the correspondence comprises:

8. The method of claim 7, wherein the method further comprises:

9. The method of claim 5, wherein in the case where the address to be read and the target storage address are different, the method further comprises:

10. An information storage device, comprising:

11. An electronic device, comprising:

a memory;

a processor; and

a computer program;

wherein the computer program is stored in the memory and configured to be executed by the processor to implement the information storage method of any one of claims 1 to 9.

12. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the information storage method according to any one of claims 1 to 9.