CN117769896A

CN117769896A - Semiconductor module and method for manufacturing the same, electronic device, electronic module, and method for manufacturing the same

Info

Publication number: CN117769896A
Application number: CN202280054608.5A
Authority: CN
Inventors: 栗田洋一郎
Original assignee: Aoi Electronics Co Ltd
Current assignee: Aoi Electronics Co Ltd
Priority date: 2021-08-20
Filing date: 2022-08-17
Publication date: 2024-03-26

Abstract

The method for manufacturing a semiconductor module includes sealing a first die having a first die electrode, a second die having a second die electrode, a first connection portion connected to the first die electrode, and a second connection portion connected to the second die electrode with a sealing body, and then mounting a bridge having a first bridge electrode and a second bridge electrode on a structure sealed with the sealing body. The first die and the second die (42) are electrically connected via a bridge.

Description

Semiconductor module and method for manufacturing the same, electronic device, electronic module, and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor module and a method for manufacturing the same.

Background

There is a technique of connecting a plurality of IC (Integrated Circuit: integrated circuit) chips. For example, patent document 1 describes a semiconductor package in which 2 IC chips are connected through a bridge (nest assembly) molded together with an interposer. Patent document 2 describes a semiconductor package in which 2 IC chips are electrically connected via a bridge integrally formed with an interposer through an underfill material.

Prior art literature

Patent literature

Patent document 1: U.S. patent application publication No. 2021/0005542 specification

Patent document 2: U.S. patent application publication 2020/0395313 specification

Disclosure of Invention

Problems to be solved by the invention

The present inventors have studied a semiconductor package including a plurality of IC chips connected via a bridge, and a semiconductor module using the semiconductor package, and as a result, have found that the semiconductor package and the semiconductor module have room for improvement. For example, in the case of electrically connecting 2 IC chips via a bridge integrated with an interposer, it is difficult to precisely align the terminals of each of the 2 IC chips with the terminals of the bridge. In this case, the densification of the terminal portion electrically connecting the IC chip and the bridge is limited.

The present invention has been completed under such circumstances, and one of exemplary objects of some form thereof is to provide a technique that enables an IC chip and a bridge to be coupled at a higher density.

Solution for solving the problem

The method for manufacturing a semiconductor module according to an embodiment includes: a step (a) of forming, on a first surface of a first support body, a first connection portion including a first columnar connection portion extending in an out-of-plane direction of the first surface, and a second connection portion including a second columnar connection portion extending in the out-of-plane direction of the first surface; a step (b) of preparing a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, and a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, each of the first semiconductor die and the second semiconductor die being mounted on the first support in such a manner that the first die electrode is arranged on the first connection portion and the second die electrode is arranged on the second connection portion; a step (c) of sealing the first semiconductor die, the second semiconductor die, the first connection portion, and the second connection portion with a first sealing body after the step (b); a step (d) of removing the first support body and exposing a part of the first columnar connection portion and a part of the second columnar connection portion from the first sealing body, respectively, after the step (c); and (e) preparing a bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, wherein after the step (d), the bridge is mounted on a structure sealed with the first sealing body so that the first bridge electrode is disposed on the first columnar connection portion and the second bridge electrode is disposed on the second columnar connection portion.

The method for manufacturing a semiconductor module according to another embodiment includes: a step (a) of forming a first opening and a second opening in a first insulating layer on a first surface of a first support after the first insulating layer is formed; a step (b) of forming a first connection portion including a first columnar connection portion formed in the first opening portion and a second connection portion including a second columnar connection portion formed in the second opening portion; a step (c) of preparing a first semiconductor die having a first IC chip, a first die electrode connected to the first IC chip, and a second insulating layer sealing the first die electrode, and a second semiconductor die having a second IC chip, a second die electrode connected to the second IC chip, and a third insulating layer sealing the second die electrode, and mounting each of the first semiconductor die and the second semiconductor die on the first support such that the first die electrode is arranged on the first connection portion and the second die electrode is arranged on the second connection portion; a step (d) of sealing the first semiconductor die and the second semiconductor die with a first sealing body after the step (c);

A step (e) of removing the first support body and exposing a part of the first columnar connection portion and a part of the second columnar connection portion from the first insulating layer, respectively, after the step (d); and (f) preparing a bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, and mounting the bridge on a structure sealed with the first sealing body so that the first bridge electrode is disposed on the first columnar connection portion and the second bridge electrode is disposed on the second columnar connection portion after the step (e). In the step (c), the first insulating layer and the second insulating layer are bonded to each other, and the first die electrode is sealed by the first insulating layer and the second insulating layer. In the step (c), the first insulating layer and the third insulating layer are bonded to each other, and the second die electrode is sealed by the first insulating layer and the third insulating layer.

The semiconductor module according to another embodiment includes: a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip; a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip; a first connection portion electrically connected to the first die electrode; a second connection portion electrically connected to the second die electrode; a bridge having a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion; and a first encapsulant sealing the first semiconductor die and the second semiconductor die. The first connection portion includes a first columnar connection portion disposed between the first semiconductor die and the bridge, extending in a direction from one of the first semiconductor die and the bridge to the other. The first connection portion includes a second columnar connection portion disposed between the first semiconductor die and the bridge and extending in a direction from one of the first semiconductor die and the bridge to the other. The first bridge electrode and the second bridge electrode are exposed from the first sealing body. Each of the first and second columnar connection portions is sealed by the first sealing body.

Another aspect of the invention relates to an electronic device. The electronic device is provided with: a first die having a first electrode; a second die having a second electrode; a first connection part electrically connected to the first electrode; a second connection part electrically connected to the second electrode; and a bridge electrically connected to the first connection portion and the second connection portion. The first connection has a columnar connection from the bridge to the first die.

Other aspects of the invention relate to electronic modules. The electronic module is provided with: the electronic device; a wiring layer in which wiring is provided; and a columnar connection portion for electrically connecting the wiring to the electronic device.

Another aspect of the present invention relates to a method for manufacturing an electronic device. The manufacturing method of the electronic device comprises the following steps: a forming step of forming, on a support, a first connection portion and a second connection portion including columnar connection portions protruding from the columnar support; a die coupling step of coupling a first electrode of the first die to the first connection portion and coupling a second electrode of the second die to the second connection portion; a sealing step of sealing the first die, the second die, and the first connection portion with resin; and a bridge coupling step of coupling the bridge to the lower portion of the first connection portion and the lower portion of the second connection portion.

Any combination of the above components, and the contents of the present invention, which are converted between methods, apparatuses, systems, recording media, computer programs, and the like, are also effective as modes of the present invention.

Effects of the invention

According to the above embodiment, the IC chip and the bridge can be coupled at a higher density.

Drawings

Fig. 1 is a schematic diagram of a chip integration system according to an embodiment.

Fig. 2 is a perspective view showing an exemplary configuration of the chip integrated body shown in fig. 1.

Fig. 3 is an explanatory diagram showing a configuration example of the chip integrated body shown in fig. 2.

Fig. 4 is an enlarged cross-sectional view showing an exemplary configuration of a part of the chip integrated module shown in fig. 3.

Fig. 5 is an explanatory view schematically showing a configuration example of the optical module shown in fig. 3.

Fig. 6 is an explanatory diagram showing an outline of a method for manufacturing a chip integrated module as a study example of an embodiment.

Fig. 7 is an explanatory diagram showing an outline of a manufacturing process of the chip integrated module shown in fig. 4.

Fig. 8 is an enlarged cross-sectional view showing details of the connecting portion forming process shown in fig. 7.

Fig. 9 is an enlarged cross-sectional view showing details of the connecting portion forming process subsequent to fig. 8.

Fig. 10 is an enlarged cross-sectional view showing details of the connecting portion forming process subsequent to fig. 9.

Fig. 11 is an enlarged cross-sectional view showing details of the connecting portion forming process subsequent to fig. 10.

Fig. 12 is an enlarged cross-sectional view showing details of the connecting portion forming step subsequent to fig. 11.

Fig. 13 is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in fig. 7.

Fig. 14 is an enlarged cross-sectional view showing details of the semiconductor die mounting process subsequent to fig. 13.

Fig. 15 is an enlarged cross-sectional view showing details of the semiconductor die mounting process subsequent to fig. 14.

Fig. 16 is an enlarged cross-sectional view showing the first sealing step shown in fig. 7 in detail.

Fig. 17 is an enlarged cross-sectional view showing details of the support removal process shown in fig. 7.

Fig. 18 is an enlarged cross-sectional view showing details of the connecting portion exposing step shown in fig. 7.

Fig. 19 is an enlarged cross-sectional view showing details of the connecting portion exposing step subsequent to fig. 18.

Fig. 20 is an enlarged cross-sectional view showing details of the bridge mounting process shown in fig. 7.

Fig. 21 is an enlarged cross-sectional view showing details of the bridge mounting process subsequent to fig. 20.

Fig. 22 is an enlarged cross-sectional view showing details of the bridge mounting process subsequent to fig. 21.

Fig. 23 is an enlarged cross-sectional view showing the second sealing step shown in fig. 7 in detail.

Fig. 24 is an enlarged cross-sectional view showing a modification example with respect to fig. 23.

Fig. 25 is an enlarged cross-sectional view showing a modification of the sealing body shown in fig. 4.

Fig. 26 is an enlarged cross-sectional view showing another modification of the sealing body shown in fig. 4.

Fig. 27 is an enlarged cross-sectional view showing another modification of the sealing body shown in fig. 4.

Fig. 28 is an enlarged cross-sectional view of a chip integrated module as a modification to fig. 4.

Fig. 29 is an explanatory diagram showing an outline of a manufacturing process of the chip integrated module shown in fig. 28.

Fig. 30 is an enlarged cross-sectional view showing details of the insulating layer formation process shown in fig. 29.

Fig. 31 is an enlarged cross-sectional view showing details of the insulating layer formation process subsequent to fig. 30.

Fig. 32 is an enlarged cross-sectional view showing details of the connecting portion forming process shown in fig. 29.

Fig. 33 is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in fig. 29.

Fig. 34 is an enlarged cross-sectional view showing details of the semiconductor die mounting process subsequent to fig. 33.

Fig. 35 is an enlarged cross-sectional view showing details of the semiconductor die mounting process subsequent to fig. 34.

Fig. 36 is an enlarged cross-sectional view showing the details of the sealing process shown in fig. 29.

Fig. 37 is an enlarged cross-sectional view showing details of the connecting portion exposing step shown in fig. 29.

Fig. 38 is an enlarged cross-sectional view showing details of the connecting portion exposing step subsequent to fig. 37.

Fig. 39 is an enlarged cross-sectional view showing details of the bridge mounting process shown in fig. 29.

Fig. 40 is an enlarged cross-sectional view showing details of the bridge mounting process subsequent to fig. 39.

Fig. 41 is an enlarged cross-sectional view showing details of the bridge mounting process subsequent to fig. 40.

Fig. 42 is an explanatory diagram showing a modification of the chip integrated body shown in fig. 3.

Fig. 43 is an explanatory view showing another modification of the chip integrated body shown in fig. 3.

Fig. 44 is a cross-sectional view showing a modification of the bridge shown in fig. 4.

Fig. 45 is a cross-sectional view showing an outline of a wiring layer forming process in the process of manufacturing the bridge shown in fig. 44.

Fig. 46 is a schematic cross-sectional view showing a wiring layer transfer process in the process of manufacturing the bridge shown in fig. 44.

Fig. 47 is a schematic cross-sectional view showing a support removal process in the process of manufacturing the bridge shown in fig. 44.

Fig. 48 is an explanatory diagram showing another modification of the bridge shown in fig. 4.

Fig. 49 is a diagram showing a part of a chip integrated module according to a modification example of fig. 4.

Fig. 50 is a diagram showing a structure of a chip integrated module according to a first modification of the chip integrated module shown in fig. 49.

Fig. 51 is a diagram showing a structure of a chip integrated module according to a second modification of the chip integrated module shown in fig. 49.

Fig. 52 is a diagram showing a structure of a chip integrated module according to a third modification of the chip integrated module shown in fig. 49.

Fig. 53 is a diagram showing a structure of a chip integrated module according to a fourth modification of the chip integrated module shown in fig. 49.

Fig. 54 is a diagram showing a structure of a chip integrated module according to a fifth modification of the chip integrated module shown in fig. 49.

Fig. 55 is a diagram for explaining a method of manufacturing a chip integrated module according to another embodiment.

Fig. 56 is a diagram for explaining a method of manufacturing the chip integrated module according to this embodiment.

Fig. 57 is a diagram for explaining a method of manufacturing the chip integrated module according to this embodiment.

Fig. 58 is a diagram for explaining a method of manufacturing the chip integrated module according to this embodiment.

Fig. 59 is a diagram for explaining a method of manufacturing the chip integrated module according to this embodiment.

Fig. 60 is a diagram for explaining a method of manufacturing the chip integrated module according to the embodiment.

Fig. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 62 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 63 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 64 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 65 is a diagram for explaining a method of manufacturing a chip integrated module according to a seventh modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 66 is a diagram for explaining a method of manufacturing a chip integrated module according to a seventh modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 67 is a diagram for explaining a method of manufacturing a chip integrated module according to an eighth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 68 is a diagram for explaining a method of manufacturing a chip integrated module according to an eighth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 69 is a diagram for explaining a method of manufacturing a chip integrated module according to an eighth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60.

Fig. 70 is a diagram for explaining a method of manufacturing an optical module according to an embodiment.

Fig. 71 is a diagram for explaining a method of manufacturing an optical module according to this embodiment.

Fig. 72 is a diagram for explaining a method of manufacturing an optical module according to this embodiment.

Fig. 73 is a diagram for explaining a method of manufacturing an optical module according to this embodiment.

Fig. 74 is a diagram for explaining a method of manufacturing an optical module according to this embodiment.

Fig. 75 is a diagram for explaining a method of manufacturing a chip integrated body according to another embodiment.

Fig. 76 is a diagram for explaining a method of manufacturing a chip integrated body according to this embodiment.

Fig. 77 is a diagram for explaining a method of manufacturing a chip integrated body according to this embodiment.

Fig. 78 is a diagram for explaining a method of manufacturing the chip integrated body according to this embodiment.

Fig. 79 is a diagram for explaining a method of manufacturing a chip integrated body according to this embodiment.

Fig. 80 is a diagram showing a configuration example of an integrated circuit chip according to an embodiment.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, a structure in which a circuit element such as a transistor or a wiring is formed on a semiconductor substrate is referred to as an IC chip. The IC chip includes a superconducting integrated circuit (quantum computer) and the like. A structure including a wiring layer laminated on a main surface of an IC chip is referred to as a semiconductor die. There is also a case where a rewiring layer is further formed on the IC chip, in which case the rewiring layer is included in the wiring layer. The plurality of semiconductor dies are sealed with a sealing body, and the integrated structure is referred to as a chip integrated module. The chip integrated module further includes a bridge electrically connecting the plurality of semiconductor die to one another. A structure in which a plurality of modules including a chip integrated module are integrated is referred to as a chip integrated body. The chip integrated body sometimes includes a module such as an optical module in addition to the chip integrated module. Chip assemblies sometimes include multiple chip assembly modules. Further, the chip integrated body may include a wide area wiring layer electrically connecting a plurality of modules, and a heat dissipation mechanism or a heat dissipation member having a function of dissipating heat generated in each module to the outside. The portion of the chip assembly other than the heat dissipation member is referred to as an integration layer. In the following description, a chip integrated module is exemplified as an example of the semiconductor module. In addition, as an example of the semiconductor package, an integration layer is cited.

However, the range of the semiconductor module and the range of the semiconductor package are not limited to the above definition. For example, as shown in fig. 1 described later, the chip integrated body 10 is one electronic component (module) assembled in the chip integrated system 1. In this case, the chip integrated body 10 can be considered as a semiconductor module assembled in the chip integrated system 1. The chip integrated module, the integrated layer, and the chip integrated body described below each include an IC chip, and may be circulated as a packaged semiconductor package. Thus, the manner of each of the chip integrated module, the integration layer, and the chip integrated body can be considered as a semiconductor package.

Chip integration System

Fig. 1 is a schematic diagram of a chip integration system according to an embodiment of the present invention. The chip integrated system 1 according to the present embodiment includes a plurality of chip integrated units 10. These chip assemblies 10 are connected to each other by optical wiring 110. For example, optical wiring is sometimes used to connect different chip assemblies to each other, but in the case of a large-scale chip assembly, it is sometimes used to connect different parts in the chip assembly. The chip integrated system 1 can be used, for example, for an artificial intelligence system or the like in which various processors and memories are highly integrated. Although fig. 1 shows 2 chip assemblies 10a and 10b, the chip integrated system 1 may include 3 or more chip assemblies 10, or the chip integrated system 1 may be configured of only 1 chip assembly 10.

The chip integrated body 10 is an integrated body including a plurality of chip integrated modules therein. The size of the chip integrated module is not particularly limited, and examples thereof include a size ranging from about 50mm square to a large size of about 300mm square. The chip integrated module is a semiconductor module including a plurality of IC chips. In fig. 1, a region in which the chip integrated module is arranged in the chip integrated body 10 is indicated by a broken line. In the example shown in fig. 1, the chip-integrated modules are arranged in 8 in the vertical direction and in 8 in the horizontal direction, and the chip-integrated body 10 includes a total of 64 chip-integrated modules. However, the number of chip modules included in the chip assembly 10 is not limited to this, and may be 63 or less, or 65 or more.

The chip assembly 10 according to the present embodiment includes an optical transceiver module (hereinafter referred to as an "optical module"). The chip assembly 10 according to the present embodiment includes, for example, 6 optical modules. In the example shown in fig. 1, the chip integrated body 10a includes optical modules 11a, 12a, 13a, 14a, 15a, and 16a. The chip integrated body 10b includes optical modules 11b, 12b, 13b, 14b, 15b, and 16b. The optical modules 11a to 16a and the optical modules 11b to 16b shown in fig. 1 correspond to the optical modules 11 to 16 shown in fig. 2 described later, respectively. These optical modules are connected to optical modules provided in the same chip assembly 10 or optical modules provided in other chip assemblies 10 via optical wiring 110. As a typical example of the optical wiring, an optical fiber is given, but the present invention is not limited thereto, and for example, a panel or a sheet on a plane having an optical waveguide, or an optical wiring using a free space may be used. In the chip integrated system 1 according to the present embodiment, since the signal in the chip integrated body 10 is transmitted by light, the signal can be transmitted at a higher speed than in the case where the signal is transmitted by only an electric signal.

< chip Integrated body >

Fig. 2 is a perspective view showing an exemplary configuration of the chip integrated body shown in fig. 1. The chip integrated body 10 according to the present embodiment includes an integrated layer (also referred to as a semiconductor package or an electronic module) 100, optical modules 11 to 16 disposed on the upper surface of the integrated layer 100, a heat dissipation mechanism 20 disposed on the upper surface of the integrated layer 100, and an external terminal 30 disposed on the lower surface of the integrated layer 100.

The integration layer 100 is a layer having a laminated structure and having a plurality of chip integrated modules (also referred to as semiconductor modules or electronic devices). The detailed structure of the integrated layer 100 will be described later with reference to fig. 3.

The heat dissipation mechanism 20 is a mechanism that dissipates heat generated in the chip integrated body 10. The heat dissipation mechanism 20 has a function of dissipating heat generated when the plurality of IC chips incorporated in the integration layer 100 and the IC chips included in the optical modules 11 to 16 operate, for example. In other words, the heat dissipation mechanism 20 can dissipate heat generated when the integrated circuit chip included in the integration layer 100 and the integrated circuit chips included in the optical modules 11 to 16 (see fig. 2) operate, for example.

The external terminal 30 is a terminal electrically connected to any one of the optical modules 11 to 16 or the chip integrated module 40 (see fig. 3 described later). In the example shown in fig. 2, the external terminals 30 are solder balls, and constitute a part of a transmission path of an electric signal. In the present embodiment, the external terminal 30 can be used to supply power to the optical module or the chip integrated module, or to input/output an electrical signal to/from the outside. As shown in fig. 2, the external terminal may have a spherical shape, or may have various shapes such as a pin shape or a pad shape.

Fig. 3 is an explanatory diagram showing a configuration example of the chip integrated body shown in fig. 2. Fig. 3 is a view showing a cross-sectional structure of the chip integrated body, but hatching is omitted for ease of observation. In addition, in fig. 3, the amounts of 2 out of the 64 chip integrated modules shown in fig. 1 are illustrated.

Each of the plurality of optical modules 11 to 16 shown in fig. 2 includes an optical transceiver, a connector, and a heat dissipation member. For example, the optical module 13 shown in fig. 3 includes an optical transceiver 130, a connector 132, and a heat radiation member 136. The heat radiation member 136 includes a support plate (heat sink) fixed to the optical transceiver 130 and a plurality of heat radiation fins fixed to the support plate and protruding in a direction away from the optical transceiver 130.

The optical transceiver 130 is an optical-to-electrical conversion unit, and has a function of converting an optical signal received via the optical wiring 110 (see fig. 1) into an electrical signal, and a function of converting the electrical signal into an optical signal and transmitting the optical signal to the outside via the optical wiring 110. A connector 132 is connected to the lower surface of the optical transceiver 130. In addition, the connector 132 is connected to an electrode 140 formed on the surface of the integrated layer 100 via solder 138. The optical transceiver 130 is capable of transmitting and receiving electrical signals with the integration layer 100 via the connector 132. By using the connector, the optical transceiver can be easily attached and detached, and for example, the optical transceiver can be quickly replaced when it is out of order.

A heat radiation member 136 is disposed on the upper surface of the optical transceiver 130. The heat dissipation member 136 can dissipate heat of the optical transceiver 130, for example. The heat dissipation member 136 includes a heat sink having a fin provided on an upper surface thereof to realize a large surface area in a small volume. The heat sink is capable of dissipating heat, such as the optical transceiver 130.

The heat dissipation mechanism 20 is supported by a support member 210 disposed on the surface of the integrated layer 100. The heat dissipation mechanism 20 includes a support plate fixed to the support member 210, and a plurality of heat dissipation fins fixed to the support plate and protruding in a direction away from the chip module 40. The heat dissipation mechanism 20 is thermally connected to the chip integrated module 40 (in other words, each of the plurality of IC chips) disposed inside the integrated layer 100 (in detail, inside the chip layer 104) via the support member 210. The support member 210 is, for example, a thermal interface material (TIM: thermal Interface Material), and is thermally connected to an IC chip disposed inside the integrated layer 100.

The integrated layer 100 shown in fig. 3 includes a wide area wiring layer 102, a chip layer 104, and a connection layer 106.

The wide area wiring layer 102 is a layer having a laminated structure composed of a plurality of layers. Each of the plurality of layers included in the wide area wiring layer 102 includes a conductor pattern such as a wiring and an insulating layer covering the conductor pattern. The insulating layer is made of, for example, insulating resin. Conductor patterns such as wirings are formed on the insulating layer of the substrate. The 2 wirings provided at mutually adjacent layers in the thickness direction are electrically connected through the conductor via holes. In the example shown in fig. 3, the wide area wiring layer 102 has 4 layers, and the external terminal 30 is formed on the wiring provided at the lowest layer (the layer farthest from the chip layer 104). Further, the wiring provided at the uppermost layer (the layer closest to the chip layer 104) of the wide area wiring layer 102 is electrically connected to the electrode provided at the chip layer 104.

The chip layer 104 is a layer including an insulating sealing body 105 and various conductors and functional devices embedded in the sealing body 105. The sealing body 105 is embedded with, for example, the conductor posts 146 and the plurality of chip integrated modules 40. In the example shown in fig. 3, an electrode 148 is provided on the lower surface of the conductor post 146, and the conductor post 146 is electrically connected to a wiring disposed at the uppermost layer of the wide area wiring layer 102 via the electrode 148.

In the example shown in fig. 3, the chip integrated module 40 is electrically connected to the wiring disposed at the uppermost layer of the wide area wiring layer 102 via the high post 401 of the conductor and the electrode 403. The constitution of the chip integrated module 40 will be described in detail later with reference to fig. 4.

The connection layer 106 is a layer for connecting the chip layer 10 and the constituent members arranged on the surface of the integrated layer 100. For example, the connection layer 106 has conductor vias 142 and electrodes 144 that connect the optical transceiver 130 with conductor pillars 146 of the chip layer 104 and electrodes 140 that are electrically connected to the optical transceiver 130.

In addition, the connection layer 106 has a contact portion 222 thermally connected to the metal of each of the plurality of chip-integrated modules 40, the contact portion 222 being connected to a coupling portion 220 provided inside the support member 210 of the heat dissipation mechanism 20. In this way, the chip integrated module 40 according to the present embodiment is thermally connected to the heat dissipation mechanism 20 via the contact portion 222 and the coupling portion 220.

Chip integration Module

Fig. 4 is an enlarged cross-sectional view showing an exemplary configuration of a part of the chip integrated module shown in fig. 3. As shown in fig. 4, the chip integrated module 40 according to the present embodiment includes a semiconductor die 41, a semiconductor die 42, and a sealing body 45 sealing the semiconductor die 41 and the semiconductor die 42. The chip integrated module 40 further includes a bridge 43 that electrically connects the semiconductor die 41 and the semiconductor die 42. The chip integrated module 40 includes a connection portion 47 for electrically connecting the semiconductor die 41 and the bridge 43, and a connection portion 48 for electrically connecting the semiconductor die 42 and the bridge 43. Each of the connection portions 47 and 48 is sealed by the sealing body 45. The semiconductor die 41 is electrically connected to the outside of the chip integrated module 40 (for example, the external terminal 30 shown in fig. 3) via the connection portion 49.

The semiconductor die 41 has: an IC chip 411 having a main surface 411t; and an insulating layer 412 and an insulating layer 413 stacked on the main surface 411t of the IC chip 411. The semiconductor die 41 has a wiring 414 and a wiring 415 electrically connected to the IC chip 411. In addition, the semiconductor die 41 has a die electrode 416 connected to the wiring 414 and a die electrode 417 connected to the wiring 415. In the example shown in fig. 4, the semiconductor die 41 has 2 insulating layers 412, 413. However, the total number of insulating layers included in the semiconductor die 41 is not limited to 2 layers, and may have 3 or more insulating layers, for example.

The IC chip 411 includes a semiconductor substrate such as silicon, and circuit elements such as transistors and diodes. As the integration method of the circuit elements in the IC chip 411, various integration methods can be employed, and for example, various integration methods such as an integration method in which the circuit elements are formed two-dimensionally or three-dimensionally on the main surface 411t of the IC chip, further, the circuit elements are formed on the respective layers in addition to the lamination of the semiconductor substrates themselves into a plurality of layers, and connection is performed through a via (TSV: through Silicon Via: through-silicon via) penetrating the semiconductor substrates can be envisaged.

The semiconductor die 42 has: an IC chip 421 having a main surface 421t; and an insulating layer 422 and an insulating layer 423, which are stacked on the main surface 421t of the IC chip 421. The semiconductor die 42 has wiring 425 electrically connected to the IC chip 421. In addition, the semiconductor die 42 has die electrodes 427 connected to the wirings 425. In the example shown in fig. 4, the semiconductor die 42 has 2 insulating layers 422, 423. However, the total number of insulating layers included in the semiconductor die 42 is not limited to 2 layers, and may include 3 or more insulating layers and 2 or more wiring layers, for example. The semiconductor die 42 has the same structure as the semiconductor die 41 described above, for example.

The bridge 43 has: a chip 431 having a main surface 431t; and an insulating layer 432 and an insulating layer 433, which are stacked on the main surface 431t of the chip 431. The bridge 43 has a wiring 434 formed on the insulating layer 432. The chip 431 is formed of a semiconductor substrate such as a silicon wafer, for example, but may be formed of an inorganic material such as glass as a modification. However, the total number of insulating layers included in the bridge 43 is not limited to 2 layers, and may include 3 or more insulating layers and 2 or more wiring layers, for example. In addition, when the chip 431 has a circuit, it may be electrically connected to the wiring 434. The bridge 43 has a bridge electrode 436 connected to the connection portion 47 and a bridge electrode 437 connected to the connection portion 48. The bridge electrode 436 and the bridge electrode 437 are electrically connected to each other via a wiring 434.

The bridge 43 according to the present embodiment is a column-based suspension bridge (Pillar Suspended Bridege). The wiring 434 according to the present embodiment is electrically connected to the chip 431, and the wiring 434 and the chip 431 are integrated and function as a bridge. However, as described later, the bridge 43 can function as a bridge circuit as long as it has a function of electrically connecting the semiconductor die 41 and the semiconductor die 42. Therefore, as a modification, the chip 431 may not be provided, or the chip 431 and the wiring 434 may not be electrically connected. In addition, in the example shown in fig. 4, the bridge 43 has 2 insulating layers 432, 433. However, the total number of insulating layers included in the bridge 43 is not limited to 2 layers, and may have 3 or more insulating layers, for example.

The connection portion 47 includes a columnar connection portion 472. In the example shown in fig. 4, the connection portion 47 has a columnar connection portion 472, a solder layer 473 connecting the columnar connection portion 472 and the die electrode 417, and a solder layer 474 connecting the columnar connection portion 472 and the bridge electrode 436.

The connection portion 48 includes a columnar connection portion 482. In the example shown in fig. 4, the connection portion 48 has a columnar connection portion 482, a solder layer 483 connecting the columnar connection portion 482 and the die electrode 427, and a solder layer 484 connecting the columnar connection portion 482 and the bridge electrode 437.

In the present embodiment, each of the columnar connection portions 472 and 482 is a columnar conductor (also referred to as a "microcolumn") of a μm size. The main body portions of the columnar connection portions 472 and 482 are made of a metal material containing copper as a main component, for example. At each of the bonding interface between the columnar connection portion 472 and the solder layer 473 and the bonding interface between the columnar connection portion 472 and the solder layer 474, an alloy layer of a metal material having higher oxidation resistance than the main body portion, in other words, having a higher free energy of oxide formation of the metal, for example, gold, and a solder containing tin as a main component, for example, is formed. The alloy layer is formed by eutectic reaction between a metal film formed at a joint interface between the columnar connection portion 472 and the solder layer 473, 474 and the solder layer when the columnar connection portion 472 and the solder layer are joined. Details of the alloy layer will be described later.

Similarly, a bonding film made of a metal material such as gold, for example, having higher oxidation resistance than the main body portion is formed at each of the bonding interface between the columnar connection portion 482 and the solder layer 483 and the bonding interface between the columnar connection portion 482 and the solder layer 484. However, when the columnar connection portion 482 is bonded to the solder layers 483 and 484, an alloy layer is formed in the vicinity of the bonding film with the solder layers 483 and 484, and the original constituent of the bonding film itself may be diffused in the solder layer.

In the example shown in fig. 4, the connection portion 49 has an electrode 492 connected to the high post 401, and a solder layer 493 connecting the electrode 492 and the die electrode 426. In the example shown in fig. 4, since the high post 401 connected to the electrode 492 is not included in the chip integrated module 40, it is indicated by a broken line. However, as a modification, the high column 401 may be regarded as a part of the chip integrated module 40.

In the case of the present embodiment, in the example shown in fig. 4, each of the bridging electrodes 436 and 437 is sealed by a sealing body 44 formed separately from the sealing body 45. The sealing body 44 is, for example, an underfill resin. However, as a modification, a sealing body that seals the chip 431 and the bridge electrodes 436 and 437 together may be used. Alternatively, as another modification, a part of the sealing body 44 may be replaced with a sealing body 105 shown in fig. 3. As shown in fig. 4, the structure in which the connection portions 47 and 48 are sealed by the sealing body 45 and the bridge 43 is exposed from the sealing body 45 is a structure obtained by a method of manufacturing the chip integrated module 40 described below. The reason for obtaining the structure shown in fig. 4 will be described in detail later.

In the present embodiment, the bridge 43 is described as an example of a semiconductor die including the chip 431, but the bridge may not include the chip 431 and mainly include the wiring 434, the insulating layers 432 and 433 in which the wiring is embedded, and the bridge electrodes 436 and 437. In the present embodiment, each of the connection portions 47 and 48 has one columnar connection portion 472, 482. However, each of the connection portions 47 and 48 sometimes has two or more columnar connection portions stacked in accordance with the distance separating the semiconductor die 41 from the bridge 43. The cross-sectional shape and cross-sectional area of the stacked columnar connection portions may also be different.

< light Module >

Fig. 5 is an explanatory view schematically showing a configuration example of the optical module shown in fig. 3. The optical module 13 according to the present embodiment mainly includes an optical system mechanism 131, an optical transceiver 130, and a connector 132. The optical module 13 includes a mechanism for transmitting an optical signal to the outside (hereinafter also referred to as "transmitting mechanism 13T") and a mechanism for receiving an optical signal from the outside (hereinafter also referred to as "receiving mechanism 13R"). In fig. 5, the transmitting mechanism 13T is shown on the left side with respect to the paper surface, and the receiving mechanism 13R is shown on the right side, but there are various modifications of the positional relationship between the transmitting mechanism 13T and the receiving mechanism 13R in addition to the one shown in fig. 5. In the following, the configuration of the transmitting mechanism 13T will be described, and the description of the portions common to the configuration of the transmitting mechanism 13T among the configurations of the receiving mechanism 13R may be omitted.

The optical system mechanism 131 of the transmission mechanism 13T includes an optical fiber 600, a lens 601, a reflection mechanism (mirror in fig. 5) 602, and a lens 603. Light incident on the lens 603 from the optical transceiver 130 is transmitted through the lens 603 and reflected in the reflection mechanism 602. The reflected light is transmitted through the lens 601 and is incident on the optical fiber 600. Thereby, the optical signal is transmitted to the outside via the optical fiber 600.

The optical system mechanism 131 of the receiving mechanism 13R includes an optical fiber 610, a lens 611, a reflecting mechanism (mirror in fig. 5) 612, and a lens 613. Light emitted from the optical fiber 610 is transmitted through the lens 611 and reflected by the reflection mechanism 612. The reflected light is transmitted through the lens 613 and is incident on the optical transceiver 130. Thus, the optical signal received by the optical fiber 610 is converted into an electrical signal, and various processes are performed. The lens or the reflection mechanism constituting the optical system mechanism 131 may be added or deleted as appropriate based on the design requirements, and may be configured such that an optical fiber is coupled to an optical element chip of an optical transceiver without the lens or the reflection mechanism, or is directly coupled to a light emitting element or a light receiving element, as the case may be.

The optical transceiver 130 mainly includes a chip layer 620, a wiring layer 630, 2 optical element chips 605, 615 disposed on the wiring layer 630, a light emitting element 606, and a light receiving element 616. In this embodiment, the 2 optical element chips 605 and 615, the light emitting element 606, and the light receiving element 616 are electrically connected to the wiring layer 630, and the connection portion is sealed with the underfill resin 607 or the like. In other words, in the present embodiment, the 2 light element chips 605 and 615, the light emitting element 606, and the light receiving element 616 are fixed by a fixing member (underfill resin 607) made of resin or the like.

The wiring layer 630 according to the present embodiment is configured by, for example, a 2-layer structure. Conductor patterns such as wirings and electrodes are formed on each of the wiring layers 630. The chip layer 620 includes an optical element driving chip 621 and an optical element driving chip 622. The light element driving chips 621 and 622 are chips that control driving of the light element chip 605 and the light element chip 615, respectively. The optical element driving chips 621 and 622 may include a function of converting the electrical signal level (voltage, current) required for the optical element to appropriately convert the optical/electrical, and the electrical signal level inputted/outputted from the outside of the optical transceiver, and the like.

The light emitting element 606 of the transmitting means is provided on the surface of the optical element chip 605, and is an element that emits an optical signal based on an electrical signal transmitted from the optical element chip 605. The optical signal emitted from the light emitting element 606 is incident on the lens 603 of the optical system mechanism 131.

The optical element chip 605 is connected to an electrode 631 of a layer formed on the upper side of the wiring layer 630 via an electrode terminal 608 and a solder layer 609, and the optical element driving chip 621 is connected to an electrode 633 of a layer formed on the lower side of the wiring layer 630 via an electrode terminal 623 and a solder layer 634. Accordingly, the optical element chip 605 and the optical driving element chip 621 are electrically connected via the wiring layer 630. This structure enables multi-parallel and short-distance connection by substantially vertical electrical connection in the wiring layer 630 between the optical element chip and the optical element driving chip. This enables broadband signal transmission between the optical element groups and the optical element driving chips arranged in a two-dimensional array. Note that, depending on the manufacturing method of the optical transceiver, the solder layer 634 is not necessarily required. Further, by arranging the electrode terminals 608, the conductor through holes 632, and the electrode terminals 623 in substantially straight lines, the length of the electrical connection path between the optical element chip and the optical driving element chip can be minimized, and excellent electrical connection with low parasitic impedance can be achieved.

A metal layer 629 made of metal is formed on the lower surface of the light element driving chip 621. The metal layer 629 is thermally connected with a conductor via 641 provided to the connector 132 via a coupling member 640. Thereby, heat generated when the light element driving chip 621 is driven is dissipated in the direction of an arrow (direction from the metal layer 629 toward the connector 132) schematically shown in fig. 5 via the coupling member 640. The metal layer 629 is preferably present in terms of heat dissipation, but effects can be obtained even if it is not necessarily present.

The conductor via 641 of the connector 132 is connected to the electrode 140 formed on the surface of the connection layer 106 via the solder layer 642. In addition, as shown in fig. 3, the electrode 140 is connected to an electrode 148 connected to a conductor post 146 formed on the chip layer 104 via a conductor via 142. Accordingly, heat dissipated to the connector 132 is dissipated through the conductor posts 146.

An electrode terminal 624 is formed on the upper surface of the light element driving chip 621, and the electrode terminal 624 is connected to an electrode 626 formed under the wiring layer 630 via a solder layer or a conductor connection portion 625. Further, a wiring 635 is formed in the wiring layer 630. The wiring 635 is connected to an electrode 626 electrically connected to the light element driving chip 621 via a conductor via 636. In addition, the wiring 635 is connected to an electrode 627 coupled to a conductor post 628 formed in the chip layer 620 via a conductor via 637.

The conductor post 628 is electrically connected to a conductor throughhole 644 of the connector 132 via a coupling member 643. In the example shown in fig. 5, for example, in the coupling member 643, the electric signals between the optical transceiver 130 and the connector 132 are mutually transmitted. However, as a modification, the transmission direction of the electric signal between the optical transceiver 130 and the connector 132 may be any direction. That is, in the case of the transmitting means 13T, an electrical signal is transmitted from the connector 132 to the optical transceiver 130, and in the case of the receiving means 13R, an electrical signal is transmitted from the optical transceiver 130 to the connector 132.

< method for manufacturing chip Integrated Module >

Next, a method of manufacturing the chip integrated module 40 shown in fig. 3 and 4 will be described. Before explaining the method of manufacturing the chip integrated module according to the present embodiment, an outline of the method of manufacturing studied by the inventors of the present application will be briefly described. Fig. 6 is an explanatory diagram showing an outline of a method for manufacturing a chip integrated module as a study example of the present embodiment.

In the method of manufacturing the chip integrated module shown in fig. 6, first, as shown in the upper stage of fig. 6, a plurality of semiconductor dies 51 and bridge structures 52 are prepared. The bridge structure 52 is a structure in which a plurality of bridges 520 and a plurality of connection portions 521 are integrated by being sealed with a sealing body 523. In the example shown in fig. 6, the plurality of high struts 401 are sealed together with the plurality of bridges 520 by a sealing body 523.

Next, as shown in the middle stage of fig. 6, a plurality of semiconductor dies 51 are mounted on the bridge structure 52. At this time, the plurality of die electrodes 511 of the semiconductor die 51 and the plurality of connection portions 521 of the bridge structure 52 are bonded, respectively.

Next, as shown in the lower stage of fig. 6, the plurality of semiconductor dies 51 are sealed with a sealing body 512, and the plurality of semiconductor dies 51 and the bridge structure 52 are integrated to obtain the chip integrated module 50.

In the case of the study example shown in fig. 6, by integrating the plurality of bridge structures 52 in advance, the operation efficiency of electrically connecting the plurality of semiconductor chips 51 and the plurality of bridges 520 can be improved.

However, in the case of the manufacturing method shown in fig. 6, the following concerns are found. That is, it has been found that it is difficult to improve the positional accuracy of each of the plurality of connection portions 521 due to contraction or expansion of the sealing body 523 constituting the bridge structure 52. As a countermeasure against this problem, a method of increasing the area of the joint interface of each of the plurality of connection portions 521 and increasing the margin that can be allowed for the positional displacement is considered. However, in this case, since the arrangement pitch of the adjacent connection portions 521 also needs to be increased, the densification of the connection portions 521 is hindered. That is, the densification of the terminal portion electrically connecting the semiconductor die 51 and the bridge 520 is limited.

As described above, it is considered that the reason why it is difficult to improve the positional accuracy of each of the plurality of connection portions 521 is due to the large volume of the sealing body 523. A measure for reducing the linear expansion coefficient of the sealing body 523 by mixing inorganic filler particles described later into the sealing body 523 is also considered, but this measure is also limited.

Based on the above-described results, the present inventors have found a method for manufacturing a chip integrated module according to the present embodiment. As will be described later in detail, the method for manufacturing a chip integrated module according to the present embodiment is to prepare a structure in which a plurality of semiconductor dies and a plurality of connection portions are integrated by a sealing body, and to mount a plurality of bridges on each of the structure. The volume of the sealing body in the structure integrating the plurality of semiconductor dies and the plurality of connection portions can be smaller than the volume of the sealing body 523 in the bridge structure 52 shown in fig. 6. In particular, by reducing the gap between adjacent IC chips, the influence of thermal contraction and thermal expansion can be reduced. As a result, according to the method for manufacturing a chip integrated module according to the present embodiment, the positional accuracy of each of the plurality of connection portions can be improved, and thus, the terminal portion for electrically connecting the semiconductor die and the bridge can be increased in density.

Hereinafter, a method for manufacturing a chip integrated module according to the present embodiment will be described in detail. Fig. 7 is an explanatory diagram showing an outline of a manufacturing process of the chip integrated module shown in fig. 4. As shown in fig. 7, the method for manufacturing the chip integrated module according to the present embodiment includes a connection portion forming step, a semiconductor die mounting step, a first sealing step, a support removing step, a connection portion exposing step, a bridge mounting step, and a second sealing step.

The step of forming the connecting portion shown in fig. 7 includes the steps shown in fig. 8 to 12. Fig. 8 to 12 are enlarged cross-sectional views each showing details of the connecting portion forming process shown in fig. 7. In the connection portion forming step, as shown in fig. 11, a connection portion 47 including a columnar connection portion 472 extending in the out-of-plane direction of the upper surface 70t and a connection portion 48 including a columnar connection portion 482 extending in the out-of-plane direction of the upper surface 70t are formed on the upper surface 70t of the support body 70.

Specifically, first, as shown in fig. 8, a support 70 having an upper surface 70t is prepared. A peeling layer 71 and a seed layer 72 are formed in advance on an upper surface 70t of the support 70. The material of the support 70 is not particularly limited as long as it is a plate having rigidity to such an extent that workability is not impaired in each step before the support removal step shown in fig. 7. For example, a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as a glass or sapphire substrate, a resin plate, or the like can be exemplified. However, in view of expansion caused by heating at the time of connection, it is preferable that the linear expansion coefficient of the support is close to that of the semiconductor die.

The release layer 71 is a functional layer having a function of releasing the support 70 in the support removing step shown in fig. 7, and various materials are selected according to various methods such as a method of releasing by an energy beam such as a laser or a method of mechanically releasing. The seed layer 72 is a seed film as a base for forming conductor members such as the connection portions 47, 48, 49 by plating. The seed layer 72 can be formed by, for example, forming copper on the release layer 71 by sputtering.

Next, as shown in fig. 9, a resist mask 73 is formed on the upper surface 70t of the support 70, specifically, on the seed layer 72. A plurality of openings 73H are formed in the resist mask 73 by, for example, photolithography.

Next, as shown in fig. 10, a metal film is deposited in the opening 73H of the resist mask 73 by plating or the like, whereby the connection portions 47, 48, and 49 are formed. Since the seed layer 72 is formed in advance on the upper surface 70t of the support 70, the columnar connection portion 472 as a part of the connection portion 47, the columnar connection portion 482 as a part of the connection portion 48, and the electrode 492 as a part of the connection portion 49 can be formed by plating, for example. In the example shown in fig. 10, the columnar connection portion 472 includes a main body portion 472A and a metal film 472B. The columnar connection portion 482 includes a main body portion 482A and a metal film 482B. The electrode 492 includes a main body 492A and a metal film 492B. The main bodies 472A, 482A, 492A are each made of, for example, copper, and the metal films 472B, 482B, 492B are each made of, for example, a metal material having higher oxidation resistance than copper, such as gold. The metal films 472B, 482B, 492B each have a function of preventing oxidation of the bonding surfaces of the main body portions 472A, 482A, 492A made of copper, and enabling solder bonding without flux in a semiconductor die mounting process described later.

Next, as shown in fig. 11, the resist mask 73 is removed (see fig. 10). When the resist mask 73 is removed, the side surfaces of the connection portions 47, 48, 49 and a part of the upper surface of the seed layer 72 are exposed. Although the process may proceed to the semiconductor die mounting process shown in fig. 7 in the state of fig. 11, it is preferable to include a process of forming an oxide film 72A on the side surfaces of the connection portions 47, 48, 49 and the exposed surface of the seed layer 72, as shown in fig. 12. By forming the oxide film 72A in advance before the semiconductor die mounting step, it is possible to prevent solder from wetting and spreading on the side surfaces of the connection portions in the semiconductor die mounting step, and the bonding shape from becoming unstable. In the case where the step of forming the oxide film 72A on the side surfaces of the connection portions 47, 48, and 49 and the exposed surface of the seed layer 72 is included, as shown in fig. 4, the side surfaces of the connection portions 47, 48, and 49 are covered with the oxide film 72A. In this step, when the oxide film 72A is not formed, the oxide film 72A shown in fig. 4 may not be formed as shown in fig. 24 described later, for example.

The method of forming the oxide film 72A includes, for example, the following method. For example, there is a method of exposing the oxide film 72A shown in fig. 12 to an atmosphere containing oxygen until the oxide film is formed in a state where the resist mask 73 shown in fig. 10 is removed. Further, as a method of forming the oxide film 72A in a shorter time, a method of heating the side surfaces of the connection portions 47, 48, 49 and the exposed surface of the seed layer 72 in an atmosphere containing oxygen is given. In fig. 12, the oxide film 72A is shown to be thick for the sake of convenience of observation, but the oxide film 72A may be formed to be thin on the side surfaces of the connection portions 47, 48, and 49 and the exposed surface of the seed layer 72.

The semiconductor die mounting process shown in fig. 7 includes the steps shown in fig. 13 to 15. Fig. 13 to 15 are enlarged cross-sectional views each showing details of the semiconductor die mounting process shown in fig. 7. In the semiconductor die mounting process, as shown in fig. 15, a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and a semiconductor die 42 having an IC chip 421 and a die electrode 427 connected to the IC chip 421 are prepared. In the semiconductor die mounting step, the semiconductor die 41 and the semiconductor die 42 are mounted on the support 70 so that the die electrode 417 is disposed on the connection portion 47 and the die electrode 427 is disposed on the connection portion 48.

In detail, first, as shown in fig. 13, a semiconductor die 41 and a semiconductor die 42 are prepared. The detailed structures of the semiconductor die 41 and the semiconductor die 42 are as already described using fig. 4, so duplicate description is omitted. Next, as shown in fig. 13, each of the semiconductor die 41 and the semiconductor die 42 is aligned with the support 70 so that the die electrode 417 is arranged on the connection portion 47 and the die electrode 427 is arranged on the connection portion 48. A solder layer 473 is formed on the die electrode 417 of the semiconductor die 41. A solder layer 493 is formed on the die electrode 416 of the semiconductor die 41. A solder layer 483 is formed on the die electrode 427 of the semiconductor die 42.

Next, as shown in fig. 14, the die electrode 417 of the semiconductor die 41 is pressed to the connection portion 47 via the solder layer 473. At this time, the die electrode 416 of the semiconductor die 41 is pressed to the connection portion 49 via the solder layer 493. Likewise, the die electrode 427 of the semiconductor die 42 is pressed to the connection portion 48 via the solder layer 483. In this step, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-phase diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily bonded by solid-phase diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid phase diffusion bonding.

Next, each of the bonding interface of the solder layer 473 and the metal film 472B of the columnar connection portion 472, the bonding interface of the solder layer 493 and the metal film 492B of the electrode 492, and the bonding interface of the solder layer 483 and the metal film 482B of the columnar connection portion 482 shown in fig. 14 is heated to the melting temperature of the solder and held. This can generate a liquid phase at each joint interface. As shown in fig. 15, an alloy layer 472D, an alloy layer 482D, and an alloy layer 492D are formed at each joint interface. When the temperature at which the liquid phase is generated is maintained, the element in the liquid phase diffuses toward the alloy layer, and the melting point of the liquid phase increases. As a result, the liquid phase partially solidifies. This bonding is called liquid phase diffusion bonding. As in the present embodiment, when the temporary bonding by solid-phase diffusion bonding and the bonding by liquid-phase diffusion bonding are combined, a strong and thermally stable bonding state can be achieved without using a solder in the bonding step using the solder. In the case of the reflow bonding method using flux, in the micro bonding as in the present embodiment, there is a high possibility that flux residue remains around the bonding portion. On the other hand, in the case of the present embodiment, since the flux residue does not remain, the step of cleaning the flux residue can be omitted. In addition, the step of cleaning and removing the flux residue is difficult due to miniaturization and high density of the connection portion. In the case of the present embodiment, since there is no need to clean the flux residue, it is possible to achieve miniaturization or high density of the connection portion. As an option for the bonding process, a normal solder bonding (brazing), a solder bonding using a flux, or a solid phase diffusion bonding of metals may be used in addition to the above, depending on the size and arrangement of the bonding portions.

In the solder bonding, it is preferable to suppress the solder component of each solder layer from wetting and spreading on the side surface of the columnar connection portion. This is because if the solder component wets and spreads on the side surface of the columnar connection portion or the upper surface of the seed layer 72, the shape of the joint portion is unstable, or the seed layer and the peeling layer are highly likely to be adversely affected by the solder. In the case of the present embodiment, as described above, the oxide film 72A is formed on the side surface of the columnar connection portion and the exposed surface of the seed layer 72. In this case, since the wetting spread of the solder component can be suppressed, the die electrode and the connection portion can be joined by a small amount of solder.

In the first sealing step shown in fig. 7, after the semiconductor die mounting step, as shown in fig. 16, the semiconductor die 41, the semiconductor die 42, the connection portion 47, and the connection portion 48 are sealed with a sealing body 45. Fig. 16 is an enlarged cross-sectional view showing the first sealing step shown in fig. 7 in detail. In this step, the semiconductor die 41, the semiconductor die 42, the connection portion 47, and the connection portion 48 are integrated by the sealing body 45. In the example shown in fig. 16, the connection portion 49 is also sealed by the sealing body 45. The sealing body 45 is exemplified by a resin material including a thermosetting resin or the like. As a modification of the sealing body 45, as will be described later, a plurality of inorganic filler particles may be contained in the resin.

In the chip integrated module 40 shown in fig. 4, the semiconductor die 41 is spaced apart from the semiconductor die 42 by a narrow distance. For example, in the example shown in fig. 16, the distance G1 between the semiconductor die 41 and the semiconductor die 42 is shorter than the shortest distance G2 from the upper surface 70t of the support 70 to the portion of the semiconductor die 41 other than the die electrodes 416, 417. In addition, the IC chip occupying most of the semiconductor die 41 and the semiconductor die 42 is composed of a semiconductor material having a much lower linear expansion coefficient than the sealing body 45. Therefore, even when the sealing body 45 is thermally expanded or thermally contracted, the positions of the die electrodes 416, 417, 427 are hardly affected by this. In addition, each of the connection portions 47, 48, 49 has been fixed to the semiconductor die 41 or the semiconductor die 42 before the first sealing process. Therefore, each of the connection portions 47, 48, 49 can maintain high positional accuracy even when sealed by the sealing body 45. Therefore, the problem described with reference to fig. 6 that it is difficult to improve the positional accuracy of each of the plurality of connection portions 521 of the bridge structure 52 is difficult to occur in the case of the present embodiment.

In the support removal step shown in fig. 7, after the first sealing step, the support 70 is removed as shown in fig. 17 (see fig. 16). Fig. 17 is an enlarged cross-sectional view showing details of the support removal process shown in fig. 7. In this step, energy is applied to the release layer 71 by laser light or the like, so that the release layer 71 is decomposed (ablated), and the adhesion of the release layer 71 to the support is greatly reduced, whereby the support 70 can be easily released. In the support removal step, the release layer may be peeled off by mechanical stress.

In the step of exposing the connecting portion shown in fig. 7, after the step of removing the supporting body, as shown in fig. 18, a part (lower surface) of the columnar connecting portion 472 and a part (lower surface) of the columnar connecting portion 482 are exposed from the sealing body 45, respectively. Fig. 18 is an enlarged cross-sectional view showing details of the connecting portion exposing step shown in fig. 7. In this step, the peeling layer 71 and the seed layer 72 shown in fig. 17 are removed by etching, for example. In this step, the oxide film 72A shown in fig. 17 is removed from the portion formed on the upper surface of the seed layer 72. In the example shown in fig. 18, in this step, a part (lower surface) of the electrode 492 is also exposed from the sealing body 45.

In this step, as shown in fig. 19, it is preferable that after the connection portions are exposed from the sealing body 45, metal films 472C, 482C, 492C are formed on the exposed surfaces of the connection portions. Fig. 19 is an enlarged cross-sectional view showing details of the connecting portion exposing step subsequent to fig. 18. As shown in fig. 19, in this step, a metal film 472C is formed on the surface of the columnar connection portion 472 exposed from the sealing body 45. Similarly, a metal film 482C is formed on the surface of the columnar connection portion 482 exposed from the sealing body 45. A metal film 492C is formed on the surface of the electrode 492 exposed from the sealing body 45. Each of the metal films 472C, 482C, 492C has a function of preventing oxidation of the joint surfaces of the main body portions 472A, 482A, 492A made of copper, and a function of enabling joining in a low-temperature process by performing a eutectic reaction with solder mainly containing tin in a semiconductor die mounting process described later. For example, each of the metal films 472C, 482C, 492C is made of a metal material (e.g., gold or the like) having higher oxidation resistance than the material of the main body portions 472A, 482A, 492A, as with each of the metal films 472B, 482B, 492B. As an example of the metal material having the above-described function, gold can be exemplified. By providing the metal films 472C, 482C, 492C, the above-described solder bonding can be performed in the bridge attachment process shown in fig. 7.

The bridge mounting process shown in fig. 7 includes the steps shown in fig. 20 to 22. Fig. 20 to 22 are enlarged cross-sectional views each showing details of the bridge mounting process shown in fig. 7. In the bridge mounting step, as shown in fig. 22, a bridge 43 including a bridge electrode 436 connected to a connection portion 47 and a bridge electrode 437 connected to a connection portion 48 is prepared. In the bridge mounting step, after the connecting portion exposing step, the bridge 43 is mounted on the structure sealed with the sealing body 45 so that the bridge electrode 436 is disposed on the columnar connecting portion 472 and the bridge electrode 437 is disposed on the columnar connecting portion 482.

In detail, first, as shown in fig. 20, the bridge 43 is prepared. The detailed structure of the bridge 43 is as already described using fig. 4, so that duplicate description is omitted. Next, as shown in fig. 20, the bridge 43 and the structure sealed by the sealing body 45 are aligned so that the bridge electrode 436 is disposed on the columnar connection portion 472 and the bridge electrode 437 is disposed on the columnar connection portion 482. A solder layer 474 is formed on the bridging electrode 436. A solder layer 484 is formed on the bridge electrode 437.

Next, as shown in fig. 21, the bridge electrode 436 of the bridge 43 is pressed to the columnar connection portion 472 of the connection portion 47 via the solder layer 474. At this time, the bridge electrode 437 of the bridge 43 is pressed to the columnar connection portion 482 of the connection portion 48 via the solder layer 484. In this step, the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (specifically, the metal film 472C of the columnar connection portion 472) are temporarily bonded by solid-phase diffusion bonding. Similarly, the solder layer 484 and the columnar connection portion 482 (specifically, the metal film 482C of the columnar connection portion 482) of the connection portion 48 are temporarily bonded by solid phase diffusion bonding.

Next, the bonding interface between the solder layer 474 and the metal film 472C of the columnar connection portion 472 and the bonding interface between the solder layer 484 and the metal film 482C of the columnar connection portion 482 shown in fig. 21 are bonded by liquid phase diffusion bonding. The method of liquid phase diffusion bonding is as described above, and thus a repetitive description is omitted. Each of the metal films 472C, 482C shown in fig. 21 is formed as alloy layers 472E, 482E by eutectic reaction of tin, which is a main component of the solder layer, and a material (e.g., gold) of the metal film as shown in fig. 22 by liquid phase diffusion bonding. If the flux residue can be cleaned by including the semiconductor die mounting step, a solder reflow process using flux may be performed instead of the combination of the solid phase diffusion bonding and the liquid phase diffusion bonding.

However, in the bridge mounting step as in the present embodiment, when the solder layers 473, 483 that join the columnar connection portions 472, 782 and the die electrodes 417, 427 are already sealed with the sealing body 45, liquid phase diffusion bonding is particularly preferably applied from the viewpoint of preventing the sealed solder layers 473, 483 from melting. In the case of liquid phase diffusion bonding, the interface between the solder layer 474 and the columnar connection portion 472 and the interface between the solder layer 484 and the columnar connection portion 482 can be bonded at a temperature lower than the melting point of the solder layers 473 and 483.

In the second sealing step shown in fig. 7, after the bridge mounting step, as shown in fig. 23, the bridge electrode 436 and the bridge electrode 437 are sealed with a sealing body 44. Fig. 23 is an enlarged cross-sectional view showing the second sealing step shown in fig. 7 in detail. In the case of the example shown in fig. 23, the sealing body 44 is an underfill resin that is buried between the bridge 43 and the sealing body 45. By sealing the bridging electrodes 436 and 437 with the sealing body 44, a part of the columnar connection portions 472, 482 exposed from the sealing body 45 can be protected.

However, there are various modifications of the embodiment shown in fig. 23. For example, the second sealing step shown in fig. 7 may be omitted, and the semiconductor module in the state shown in fig. 22 may be shipped as a product. Alternatively, as shown in fig. 24 as a modification, the bridging electrode 436 and the bridging electrode 437 may be sealed with the sealing body 105 together with the conductor high post 401. This sealing process is commonly referred to as Molded Underfill (MUF). In this modification, a step of forming the high column 401 is required before the second sealing step. For example, the step of forming the high post is preferably performed after the step of exposing the connecting portion and before the bridge mounting step. The method of forming the high post 401 can be performed in the same manner as the step of forming the connecting portion described with reference to fig. 8 to 12. That is, a resist mask is formed on the lower surface 45b of the sealing body 45 shown in fig. 24. The resist mask has an opening at a position overlapping with a part of the connection portion 49. The high pillars 401 are formed by depositing a metal film in the openings of the mask by plating or the like. In this case, the high post 401 is formed directly on the electrode 492.

In the case of the modification shown in fig. 24, the whole of the chip layer 104, the whole of the integrated layer 100, or the whole of the chip integrated body 10 shown in fig. 3 can be regarded as a semiconductor module.

As shown in fig. 7, in the case of the manufacturing method in which the bridge mounting step is performed after integrating the plurality of semiconductor dies in the first sealing step, each of the plurality of die electrodes and the plurality of connection portions can be arranged with high positional accuracy, and therefore, the IC chip and the bridge can be coupled at a higher density. As described with reference to fig. 4, the structure in which each of the connection portion 47, the connection portion 48, the semiconductor die 41, and the semiconductor die 42 is sealed with one sealing body 45 is a structure manufactured by using the manufacturing method described with reference to fig. 7 to 24.

< modification of seal body >

Next, a modification of the sealing body 45 and the sealing body 44 shown in fig. 4 will be described. Fig. 25 to 27 are enlarged cross-sectional views each showing a modification of the sealing body shown in fig. 4.

The sealing body 45A and the sealing body 44A of the chip integrated module 40A shown in fig. 25 are different from the chip integrated module 40 shown in fig. 4. Seal 45A includes a plurality of filler particles 451, and seal 44A includes a plurality of filler particles 441. The average particle diameter of the plurality of filler particles 451 is larger than the average particle diameter of the plurality of filler particles 441. As in the present modification, the linear expansion coefficient of the sealing body 45A as a whole can be reduced by including the plurality of filler particles 451 having a large average particle diameter in the sealing body 45A. As a result, in the bridge mounting process described using fig. 7 and 20 to 22, the positional accuracy of the connection portions 47 and 48 can be further improved. The plurality of filler particles 451 are mixed in advance with the sealing resin used in the first sealing step used in fig. 7. Similarly, a plurality of filler particles 441 are previously mixed in the sealing resin used in the second sealing step shown in fig. 7.

The sealing body 45B and the sealing body 44B of the chip integrated module 40B shown in fig. 26 are different from the chip integrated module 40 shown in fig. 4. Seal 45B includes a plurality of filler particles 452 and seal 44 includes a plurality of filler particles 442. The packing ratio of the plurality of packing particles 452 to the sealing body 45B is larger than the packing ratio of the plurality of packing particles 442 to the sealing body 44B. The "filling rate of the filler particles 452" is defined as a total value of the volumes of the plurality of filler particles 452 contained in the volume of the entire sealing body 45B including the resin 453 and the plurality of filler particles 452. The "filling rate of the filler particles 442" is defined as a total value of the volumes of the plurality of filler particles 442 contained in the entire volume of the sealing body 44B including the insulating resin 443 and the plurality of filler particles 442.

However, in the case of calculating the filling rate, for example, the cross sections of two or more randomly determined regions in the sealing body 45A are imaged, and the ratio of the cross-sectional area of the filler particles 452 to the cross-sectional area of the sealing body 45A is measured in each of the imaged regions, so that the average value of the regions can be regarded as "the filling rate of the filler particles 452". The same applies to "filling rate of filler particles 442". As in the present modification, by increasing the filling rate of the plurality of filler particles 452 in the sealing body 45B, the linear expansion coefficient of the sealing body 45B as a whole can be reduced. As a result, in the bridge mounting process described using fig. 7 and 20 to 22, the positional accuracy of the connection portions 47 and 48 can be further improved. The plurality of filler particles 452 are mixed in advance with the sealing resin used in the first sealing step used in fig. 7. Similarly, a plurality of filler particles 442 are mixed in advance with the sealing resin used in the second sealing step shown in fig. 7.

The sealing body 45B of the chip-integrated module 40C shown in fig. 27 is different from the chip-integrated module 40 shown in fig. 4. The sealing body 45B includes a plurality of filler particles 452, and the sealing body 44 is an insulating resin 443 that does not include filler particles. As in the present modification, the linear expansion coefficient of the entire sealing body 45B can be reduced as long as the sealing body 45B contains filler particles, regardless of the presence or absence of filler particles in the sealing body 44. As a result, in the bridge mounting process described using fig. 7 and 20 to 22, the positional accuracy of the connection portions 47 and 48 can be further improved.

< modification of manufacturing method >

Next, a modification of the method for manufacturing the chip integrated module 40 described with reference to fig. 7 to 23 will be described. Fig. 28 is an enlarged cross-sectional view of a chip integrated module as another modification with respect to fig. 4. The chip integrated module 40D shown in fig. 28 is different from the chip integrated module 40 shown in fig. 4 in that the connection portions 47 and 48 are sealed by the insulating layer 81, and each of the die electrodes 416, 417 of the semiconductor die 41 and the die electrode 427 of the semiconductor die 42 is sealed by the insulating layer 82 which is in close contact with the insulating layer 81. In addition, the chip integrated module 40D is different from the chip integrated module 40 shown in fig. 4 in that each of the bridge electrodes 436 and 437 of the bridge 43 is sealed by an insulating layer 84 that is in close contact with the insulating layer 81.

A method for manufacturing the chip integrated module 40D shown in fig. 28 will be described below. In the following description, differences from the method for manufacturing the chip integrated module 40 described using fig. 7 to 23 will be mainly described, and description of common steps may be omitted. Fig. 29 is an explanatory diagram showing an outline of a manufacturing process of the chip integrated module shown in fig. 28. As shown in fig. 29, the method for manufacturing the chip integrated module according to the present modification includes an insulating layer forming step, a connecting portion forming step, a semiconductor die mounting step, a sealing step, a support removing step, a connecting portion exposing step, and a bridge mounting step.

The insulating layer forming process shown in fig. 29 includes the steps shown in fig. 30 and 31. Fig. 30 and 31 are enlarged cross-sectional views each showing details of the insulating layer forming process shown in fig. 29. In the insulating layer forming step, as shown in fig. 30, an insulating layer 81 is formed on the upper surface 70t of the support 70, and then, as shown in fig. 31, openings 81H1 and 81H2 are formed in the insulating layer 81. In the example shown in fig. 31, the opening portions 81H3 for forming the connection portion 49 shown in fig. 28 are formed together. The insulating layer 81 is bonded to the insulating layer 82 shown in fig. 28 in a semiconductor die mounting process described later. Therefore, among the insulating materials used for the insulating layer 82, a material having high heat resistance is preferably used in addition to the electrical insulating property. Examples of such a material include an organic insulating material such as polyimide or PBO (polybenzoxazole). The support 70, the release layer 71, and the seed layer 72 shown in fig. 30 and 31 are as described above with reference to fig. 8, and thus overlapping description thereof is omitted.

In the connection portion forming step shown in fig. 29, as shown in fig. 32, the connection portion 47 including the columnar connection portion 472 formed in the opening 81H1 and the connection portion 48 including the columnar connection portion 482 formed in the opening 81H2 are formed. Fig. 32 is an enlarged cross-sectional view showing details of the connecting portion forming process shown in fig. 29. In the example shown in fig. 32, an electrode 492 constituting the connection portion 49 is formed in the opening 81H 3. In the case of the present modification, the manufacturing method is different from that described using fig. 10 in that the insulating layer 81 is used as a mask instead of using the resist mask 73 described using fig. 10. The structures of the columnar connection portions 472 and 482 and the electrode 492 are as described with reference to fig. 10, so that overlapping description is omitted.

As described above, in the case of the present modification, the connection portions 47, 48, 49 are formed using the insulating layer 81 as a mask. Therefore, the step of removing the resist mask 73 described with reference to fig. 11 and the step of forming the oxide film 72A described with reference to fig. 12 are not applicable to the case of the present modification.

The semiconductor die mounting process shown in fig. 29 includes the steps shown in fig. 33 to 35. Fig. 33 to 35 are enlarged cross-sectional views each showing details of the semiconductor die mounting process shown in fig. 29. In the semiconductor die mounting process, as shown in fig. 35, a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and a semiconductor die 42 having an IC chip 421 and a die electrode 427 connected to the IC chip 421 are prepared. In the semiconductor die mounting step, the semiconductor die 41 and the semiconductor die 42 are mounted on the support 70 so that the die electrode 417 is disposed on the connection portion 47 and the die electrode 427 is disposed on the connection portion 48.

Specifically, first, as shown in fig. 33, a semiconductor die 41 and a semiconductor die 42 are prepared. In this modification, the insulating layer 82 is formed on the upper surface (die electrode forming surface) of the semiconductor die 41 and the insulating layer 83 is formed on the upper surface (die electrode forming surface) of the semiconductor die 42, which is different from the semiconductor die mounting process described with reference to fig. 13 to 15. The insulating layer 82 is an insulating layer bonded to the insulating layer 81 in this step. The material of the insulating layers 82 and 83 is particularly preferably composed of the same material as the insulating layer 81, if the bondability to the insulating layer 81 is considered. The detailed structure of the semiconductor die 41 and the semiconductor die 42 other than the above-described difference is as already described using fig. 4, so that a repetitive description is omitted.

Next, as shown in fig. 33, each of the semiconductor die 41 and the semiconductor die 42 is aligned with the support 70 so that the die electrode 417 is arranged on the connection portion 47 and the die electrode 427 is arranged on the connection portion 48. A solder layer 473 is formed on the die electrode 417 of the semiconductor die 41. A solder layer 483 is formed on the die electrode 427 of the semiconductor die 42. In the case of the present modification, in the sealing step described in fig. 29, the sealing body 45 does not contact each of the connection portions 47, 48, and 49. Therefore, it is preferable that the solder layer 493 is formed on the joint surface of the electrode 492 having a relatively larger area than the die electrode 416. Thus, after the semiconductor die mounting process, the volume of the void around the solder layer 493 can be reduced. On the other hand, from the viewpoint of preventing oxidation of the bonding surface of the die electrode 416, it is preferable that a solder layer is also formed on the die electrode 416.

Next, as shown in fig. 34, the die electrode 417 of the semiconductor die 41 is pressed to the connection portion 47 via the solder layer 473. At this time, the die electrode 416 of the semiconductor die 41 is pressed to the solder layer 493. Likewise, the die electrode 427 of the semiconductor die 42 is pressed to the connection portion 48 via the solder layer 483. In this step, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-phase diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily bonded by solid-phase diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid phase diffusion bonding. At this point, the insulating layer 81 is in contact with each of the insulating layers 82 and 83, but has not yet been bonded.

Next, the bonding interface between the solder layer 473 and the metal film 472B of the columnar connection portion 472, the bonding interface between the solder layer 493 and the metal film 492B of the electrode 492, and the bonding interface between the solder layer 483 and the metal film 482B of the columnar connection portion 482 shown in fig. 34 are bonded by the above-described liquid phase diffusion bonding, respectively. In this case, as shown in fig. 35, an alloy layer 472D, an alloy layer 482D, and an alloy layer 492D generated by a eutectic reaction are formed at each joint interface. The details of the liquid phase diffusion bonding are as already described, and thus overlapping description is omitted.

In the case of the present modification, in the semiconductor die mounting process, the insulating layer 81 and the insulating layer 82 are bonded to each other, and the die electrode 417 is sealed with the insulating layer 81 and the insulating layer 82. In the semiconductor die mounting process, the insulating layer 81 and the insulating layer 83 are bonded to each other, and the die electrode 427 is sealed with the insulating layer 81 and the insulating layer 83. The timing at which the insulating layer 81 is bonded to each of the insulating layers 82 and 83 may be substantially the same as the timing at which liquid phase diffusion bonding is performed. That is, when the solder layer 473 and the metal film 472B shown in fig. 34 are heated to a temperature at which a eutectic reaction occurs, each of the insulating layers 81, 82, 83 is also heated together. Thereby, the material constituting the insulating layers 81, 82, 83 is softened, and the contact interfaces thereof are bonded. As a bonding principle between insulating layers, not only bonding (fusion/bonding) by dehydration polymerization of hydroxyl groups on the surface of the insulating layers, but also bonding by softening and melting can be used depending on materials. In the case of using the fusion bonding method, it is preferable that activation of the surface of the insulating layer by plasma is performed before bonding the insulating layers to each other.

In the case of the present modification, the connection portions 47, 48, and 49 are surrounded by the insulating layer 81. Therefore, when liquid phase diffusion bonding is performed, wetting spread of the solder component can be suppressed. Therefore, in the case of the present modification, the die electrode and the connection portion can be joined by a small amount of solder.

In the sealing step shown in fig. 29, after the semiconductor die mounting step, as shown in fig. 36, the semiconductor die 41 and the semiconductor die 42 are sealed with a sealing body 45. Fig. 36 is an enlarged cross-sectional view showing the details of the sealing process shown in fig. 29. In this step, the semiconductor die 41 and the semiconductor die 42 are integrated by the sealing body 45. In the case of the present modification, since the connection portions 47, 48, and 49 have been sealed, respectively, the semiconductor die 41 and the semiconductor die 42 are integrated, strictly speaking, via the insulating layer 81, respectively. In this step, the rigidity of the structure in which the semiconductor die 41 and the semiconductor die 42 are integrated is improved by sealing with the sealing body 45.

In the case of the present modification, the volume of the sealing body 45 is smaller than that of the sealing body 45 shown in fig. 4. Therefore, even when the sealing body 45 is thermally expanded or thermally contracted, the connection portions 47, 48, 49 can maintain high positional accuracy when the sealing body 45 is sealed.

In the support removing step shown in fig. 29, the support 70 shown in fig. 36 is removed after the sealing step. The method of removing the support 70 is the same as the support removing step described with reference to fig. 17, and therefore, a repetitive description is omitted.

In the connection portion exposure step shown in fig. 29, after the support removal step, as shown in fig. 37, a part (lower surface) of the columnar connection portion 472 and a part (lower surface) of the columnar connection portion 482 are exposed from the insulating layer 81, respectively. Fig. 37 is an enlarged cross-sectional view showing details of the connecting portion exposing step shown in fig. 29. In this step, the peeling layer 71 and the seed layer 72 shown in fig. 36 are removed by etching, for example. In the example shown in fig. 37, in this step, a part (lower surface) of the electrode 492 is also exposed from the insulating layer 81.

In this step, as shown in fig. 38, it is preferable that after the connection portions are exposed from the insulating layer 81, metal films 472C, 482C, 492C are formed on the exposed surfaces of the connection portions. Fig. 38 is an enlarged cross-sectional view showing details of the connecting portion exposing step subsequent to fig. 37. As shown in fig. 38, in this step, a metal film 472C is formed on the surface of the columnar connection portion 472 exposed from the sealing body 45. Similarly, a metal film 482C is formed on the surface of the columnar connection portion 482 exposed from the sealing body 45. A metal film 492C is formed on the surface of the electrode 492 exposed from the sealing body 45. The metal films 472C, 482C, 492C are described in detail with reference to fig. 19, and thus overlapping description is omitted.

The bridge mounting process shown in fig. 29 includes the steps shown in fig. 39 to 41. Fig. 39 to 41 are enlarged cross-sectional views each showing details of the bridge mounting process shown in fig. 29. In the bridge mounting step, as shown in fig. 41, a bridge 43 including a bridge electrode 436 connected to a connection portion 47 and a bridge electrode 437 connected to a connection portion 48 is prepared. In the bridge mounting step, after the connecting portion exposing step, the bridge 43 is mounted on the structure sealed with the sealing body 45 so that the bridge electrode 436 is disposed on the columnar connecting portion 472 and the bridge electrode 437 is disposed on the columnar connecting portion 482.

Specifically, first, as shown in fig. 39, the bridge 43 is prepared. The present modification differs from the semiconductor die mounting process described with reference to fig. 13 to 15 in that the insulating layer 84, the bridge electrode 436, and the bridge electrode 437 are formed on the upper surface (bridge electrode forming surface) of the bridge 43 and are sealed with the insulating layer 84. The detailed structure of the bridge 43 other than the above-described differences is as already described using fig. 4, so that a repetitive description is omitted.

Next, as shown in fig. 39, the bridge 43 and the structure sealed by the sealing body 45 are aligned so that the bridge electrode 436 is disposed on the columnar connection portion 472 and the bridge electrode 437 is disposed on the columnar connection portion 482. A solder layer 474 is formed on the bridging electrode 436. A solder layer 484 is formed on the bridge electrode 437.

Next, as shown in fig. 40, the bridge electrode 436 of the bridge 43 is pressed to the columnar connection portion 472 of the connection portion 47 via the solder layer 474. At this time, the bridge electrode 437 of the bridge 43 is pressed to the columnar connection portion 482 of the connection portion 48 via the solder layer 484. In this step, the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (specifically, the metal film 472C of the columnar connection portion 472) are temporarily bonded by solid-phase diffusion bonding. Similarly, the solder layer 484 and the columnar connection portion 482 (specifically, the metal film 482C of the columnar connection portion 482) of the connection portion 48 are temporarily bonded by solid phase diffusion bonding.

In the case of the present modification, at this time, the insulating layer 81 and the insulating layer 84 are in contact with each other. At this time, however, the insulating layer 81 and the insulating layer 84 have not yet been bonded.

Next, the bonding interface between the solder layer 474 and the metal film 472C of the columnar connection portion 472 and the bonding interface between the solder layer 484 and the metal film 482C of the columnar connection portion 482 shown in fig. 40 are bonded by liquid phase diffusion bonding. The method of liquid phase diffusion bonding is as described above, and thus a repetitive description is omitted. The metal films 472C and 482C shown in fig. 40 are formed into alloy layers 472E and 482E (see fig. 41) by eutectic reaction of tin, which is a main component of the solder layer, and a material (e.g., gold) of the metal films by liquid phase diffusion bonding.

In the case of the present modification, the insulating layer 81 and the insulating layer 84 are bonded to each other in the bridge mounting step. The timing at which the insulating layer 81 and the insulating layer 84 are bonded to each other is the timing at which liquid phase diffusion bonding is performed. That is, when the solder layer 474 and the metal film 472C shown in fig. 40 are heated to a temperature at which eutectic reaction occurs, the insulating layer 81 and the insulating layer 84 are also heated together, respectively. Thereby, the materials constituting the insulating layer 81 and the insulating layer 84 soften, and the contact interface thereof is bonded. As a principle of bonding the insulating layers to each other, the above-described bonding (fusion/bonding) or the like based on dehydration polymerization of hydroxyl groups on the surface of the insulating layer can also be used.

Although this modification is described as an example using the insulating layers 81 to 84 shown in fig. 28, a configuration example shown in fig. 4 or a configuration of the modification described using fig. 24 may be partially applied. For example, in place of the insulating layer 84 shown in fig. 28, the bridging electrode 436 and the bridging electrode 437 are sometimes sealed with the sealing body 44 shown in fig. 4 or the sealing body 105 shown in fig. 24, respectively.

In the present modification, the example in which the upper surface of the bridge 43 is covered with the insulating layer 84 has been described, but the insulating layer 84 may not be formed. For example, in the case of using a functional insulating film called NCF (Non Conductive Film: nonconductive film) instead of the insulating layer 84, the NCF is arranged so as to cover the insulating layer 81, the connecting portion 47, and the connecting portion 48 after the process shown in fig. 38. In this case, in the bridge mounting step, the bridge 43 having the structure shown in fig. 20 is pressed against the NCF, so that the above-described solid-phase diffusion bonding and liquid-phase diffusion bonding are performed in a state where the bridge electrode 436 and the bridge electrode 437 penetrate the NCF and come into contact with the connection portion 47 or the connection portion 48, respectively, whereby the same structure as the chip integrated module 40D shown in fig. 28 can be obtained.

< method for manufacturing chip Integrated body >

Next, a method for manufacturing the chip integrated body will be described with reference to fig. 3. First, the wide area wiring layer 102 is formed on a support not shown. The method for forming the wide area wiring layer 102 is not particularly limited, and for example, build-up (build-up) method can be used. Next, a plurality of electrodes 403 and a high post 401 are formed on the wide area wiring layer 102. The method of forming the electrode 403 and the high post 401 can be applied by using the connection portion forming step described with reference to fig. 8 to 12. In this step, the electrode 148 and the conductor post 146 are also formed. If the thicknesses of the electrode 148 and the electrode 403 are the same, they can be formed together at the same timing. On the other hand, since the conductor posts 146 and the high posts 401 are different in thickness, they are formed separately.

Next, the chip integrated module 40 is mounted on the high post 401. The high post 401 is connected to a connection 49 shown in fig. 4. The method for connecting the high post 401 and the connecting portion 49 is not particularly limited, and may be, for example, connected via a solder layer, not shown. In this case, from the viewpoint of preventing the solder layer in the chip integrated module 40 from remelting, liquid phase diffusion bonding is preferably used.

Next, various members formed on the chip layer 104 are sealed with a sealing body 105. In the example shown in fig. 3, the conductor post 146, the electrode 148, the chip integrated module 40, the high post 401, and the electrode 403 are sealed by the sealing body 105, respectively. After that, a support body, not shown, is removed from the wide area wiring layer 102. Further, the upper portion of the sealing body 105 is polished to expose the conductor posts 146 and the chip integrated module 40.

Next, a connection layer 106 is formed on the sealing body 105. More specifically, the connection layer 106 is formed on the sealing body 105 so that the wiring included in the connection layer 106 is connected to the exposed portion of the conductor post 146 or the exposed portion of the chip integrated module 40. For example, the electrode 140 formed over the connection layer 106 is connected to the conductor post 146 through the conductor via 142.

Next, the heat dissipation mechanism 20 is mounted on the contact portion 222. Further, the optical module 13 to which the optical fiber 600 (see fig. 5) or the optical fiber 610 (see fig. 5) is connected to the electrode 140. The heat dissipation member 136 is connected to the optical module 13 in advance. Next, if a plurality of external terminals 30 are mounted on the wide area wiring layer 102, the chip integrated body 10 shown in fig. 3 is obtained.

< modification of chip Integrated body >

Next, a modification of the chip integrated body shown in fig. 3 will be described. Fig. 42 and 43 are explanatory views each showing a modification of the chip integrated body shown in fig. 3. The chip integrated body 10A shown in fig. 42 is different from the chip integrated body 10 shown in fig. 3 in that a part of the optical module 13 is buried in the chip layer 104 of the integration layer 100. Specifically, the portion of the connector 132 in the optical module 13 is sealed by the sealing body 105. The connector 132 and the electrode 148 are connected via the conductor via 142. In the case where the connector 132 is partially embedded in the chip layer 104, the height of the entire chip integrated body 10A can be reduced, and the distance from the chip integrated module to the optical transceiver can be shortened as compared with the case of fig. 3, whereby the signal transmission characteristics can be improved. Further, since the optical transceiver 130 is exposed from the chip layer 104 and the connection layer 106, the optical transceiver 130 can be easily attached and detached.

The chip integrated body 10B shown in fig. 43 is different from the chip integrated body 10 shown in fig. 3 in that the optical module 13 is arranged on the back surface 100B side of the integration layer 100. The integrated layer 100 includes a front surface 100f on which the heat dissipation mechanism 20 is mounted and a rear surface 100b opposite to the front surface 100 f. The optical module 13 is mounted on the back surface 100b side. By disposing the optical module 13 on the rear surface 100b, the distance between the heat dissipation mechanism 20 and the optical module 13 increases, and therefore, the thermal influence from the heat dissipation mechanism 20 can be reduced. In the example shown in fig. 43, the optical module 13 is arranged at a position overlapping the chip integrated module 40 in the thickness direction of the integrated layer 100. In this case, since the distance between the chip integrated module 40 and the optical module 13 becomes short, the transmission efficiency of the electric signal can be improved.

Modified example of parasitic capacitance reduction countermeasure generated in bridge

In the signal transmission path via the bridge 43 shown in fig. 4, signals are transmitted at an ultra-high speed. In the case of a high-speed signal transmission path, it is preferable to reduce the electric parasitic capacitance given to the transmission path. Hereinafter, a technique of reducing parasitic capacitance generated between the chip 431 and the wiring 434 shown in fig. 4 is described as a modification. Fig. 44 is a cross-sectional view showing a modification of the bridge shown in fig. 4.

The bridge 43A shown in fig. 44 is different from the bridge 43 shown in fig. 4 in that an insulating layer 438 is further provided between the insulating layer 432 and the chip 431. Otherwise identical to bridge 43 shown in fig. 4. The bridge 43A has: a chip 431; an insulating layer 438, an insulating layer 432, and an insulating layer 433 are sequentially stacked over the chip 431; and a wiring 434 sandwiched between the insulating layers 432 and 438, connected to each of the bridge electrodes 436 and 437. The insulating layer 438 is a thick film insulating layer. The thickness of the insulating layer 438 is thicker than the thickness of the insulating layer 432 and the thickness of the insulating layer 433. Insulating layer 438 has a face 438t bonded to insulating layer 432 and a face 438b bonded to chip 431. The surfaces 438t and 438b have an adhesive function, and the insulating layer 438 is adhesively fixed to the insulating layer 432 and the chip 431 via the adhesive function of the surfaces 438t and 438b. The entirety of the insulating layer 438 may be an adhesive layer.

As in the bridge 43A, in the case where the insulating layer 438 is interposed between the insulating layer 432 and the chip 431, the distance between the wiring 434 and the chip 431 can be increased. As a result, parasitic capacitance generated between the chip 431 and the wiring 434 can be reduced as compared with the bridge 43 shown in fig. 4.

In the case of the bridge 43A provided with the insulating layer 438, buckling deformation of the bridge is likely to occur as compared with the bridge 43 shown in fig. 4. The warp deformation of the bridge is caused by film formation stress (curing shrinkage or thermal shrinkage of the resin) generated when the insulating layer 438 is formed. From the viewpoint of reducing the warp deformation, a material having a low elastic modulus is preferably used for the insulating layer 438. From the same point of view, a resin material having a lower curing temperature and a lower thermal decomposition temperature is preferably used as compared with the insulating layer 432 and the insulating layer 433. For example, in the case where the insulating layers 432 and 433 are made of polyimide resin and the insulating layer 438 is made of epoxy resin, the insulating layer 438 is made of a resin material having a lower curing temperature and thermal decomposition temperature than the insulating layers 432 and 433, and thus warp deformation of the bridge 43A can be suppressed.

The bridge 43A shown in fig. 44 is manufactured as follows, for example. Fig. 45 to 47 are cross-sectional views showing an outline of a process for manufacturing the bridge shown in fig. 44. The method for manufacturing the bridge 43A includes a wiring layer forming step shown in fig. 45, a wiring layer transfer step shown in fig. 46, a support removing step shown in fig. 47, and a bridge electrode forming step shown in fig. 44.

First, in the wiring layer forming step, an insulating layer 433, a wiring 434, and an insulating layer 432 are sequentially formed on a support 80 shown in fig. 45. Specifically, in the wiring layer forming step, a support 80 shown in fig. 45 is prepared. A peeling layer 81A and a seed layer 82A are formed in advance on the upper surface 80t of the support 80. The material of the support 80 is not particularly limited as long as it is a plate having rigidity to such an extent that workability is not impaired in each step before a support removal step described later. For example, a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as a glass or sapphire substrate, a resin plate, or the like can be exemplified. The release layer 81A is the same as the release layer 71 described using fig. 8, and the seed layer 82A is the same as the seed layer 72 described using fig. 8, so that overlapping description is omitted.

In the wiring layer forming step, after the support 80 is prepared, the insulating layer 433 is deposited on the seed layer 82A. Next, an opening is formed in a part of the insulating layer 433, and a wiring 434 is formed in the opening. Although the overlapping description is omitted, the formation method of the opening portion and the formation method of the wiring 434 in the opening portion can be formed by a method using the photolithography technique described with reference to fig. 9 and 10. Next, the insulating layer 432 is formed so as to cover the insulating layer 433 and the wiring 434, whereby the structure shown in fig. 45 can be obtained.

Next, in the wiring layer transfer step, as shown in fig. 46, an insulating layer 432 on the support 80 is bonded to the chip 431 via an insulating layer 438. Fig. 46 illustrates an example of attaching a singulated chip 431. However, as a modification, in this step, a silicon wafer before singulation, a glass substrate before singulation, or a sapphire substrate before singulation may be attached instead of the chips 431. In the case of attaching the substrate in a state before singulation in this step, after the bridge electrode forming step, a singulation step of cutting the substrate to obtain a plurality of bridges 43A (see fig. 44) is performed. In this modification, a plurality of bridges 43A can be manufactured at once, and therefore, it is preferable from the viewpoint of improving the manufacturing efficiency. If these modifications are included, the present step can be expressed as follows. That is, in the wiring layer transfer step, the insulating layer 432 on the support 80 is bonded to the substrate via the insulating layer 438. The term "substrate" as used herein includes, in addition to the chips shown in fig. 46, a semiconductor substrate such as a silicon wafer before singulation, a glass substrate before singulation, a sapphire substrate before singulation, and the like. As described with reference to fig. 44, since the surface 438t and the surface 438b of the insulating layer 438 each have an adhesive function, the insulating layer 432 on the support 80 and the chip 431 are adhered and fixed via the insulating layer 438. In the case of the present modification, the chip 431 and the wiring 434 are not electrically connected. In the case where a portion of the chip 431 is not connected to another circuit, the portion of the chip 431 shown in fig. 44 may be replaced with a substrate (for example, a semiconductor substrate, a glass substrate, or the like) on which an integrated circuit is not formed. Alternatively, as described later, the bridge may be formed by removing a portion of the chip 431.

Next, in the support removal step, as shown in fig. 47, energy is applied to the release layer 81A (see fig. 46), and the release layer 81A is decomposed, for example. After the support removing step, the conductor portions connected to the bridge electrode 437 and the bridge electrode 436 (the conductor portion 437A connected to the bridge electrode 437 and the conductor portion 436A connected to the bridge electrode 436) are exposed. Each of the conductor part 436A and the conductor part 437A functions as a contactor for electrically connecting the wiring substrate and the bridging electrode. In this step, the peeling layer 81A and the seed layer 82A shown in fig. 46 are removed by etching, for example.

Next, in the bridge electrode forming step, as shown in fig. 44, a bridge electrode 437 is formed on the conductor part 437A connected to the wiring 434, and a bridge electrode 436 is formed on the conductor part 436A connected to the wiring 434. In this step, a solder layer 474 is formed on the front end surface of the bridge electrode 436, and a solder layer 484 is formed on the front end of the bridge electrode 437.

The bridge 43A shown in fig. 44 can be formed by dividing the wafer or panel into bridges of a predetermined size after the above steps are performed in a large size. The bridge 43A can be replaced with the bridge 43 shown in fig. 4, for example. In the case where the bridge 43 is replaced with the bridge 43A, parasitic capacitance between the chip 431 and the wiring 434 is reduced, and thus is particularly suitable for the case of transmitting a high-speed signal. In this modification, as a modification to the bridge 43 shown in fig. 4, a bridge 43A shown in fig. 44 and a bridge 43B shown in fig. 48 described later are described. However, the bridge 43A and the bridge 43B can be replaced with the illustrated bridge 43 in any one of the chip integrated module 40A shown in fig. 25, the chip integrated module 40B shown in fig. 26, the chip integrated module 40C shown in fig. 27, and the chip integrated module 40D shown in fig. 28.

Fig. 48 is a cross-sectional view showing another modification of the bridge shown in fig. 4. Bridge 43B shown in fig. 48 is different from bridge 43 shown in fig. 4 in that a portion corresponding to chip 431 has been removed. In the case of the bridge 43B, since the chip 431 is not disposed in the vicinity of the wiring 434, the influence of parasitic capacitance on the wiring 434 can be further reduced.

However, in the case of the bridge 43B, the rigidity is lower than that of the bridge 43 shown in fig. 4 or the bridge 43A shown in fig. 44. Therefore, in the process of manufacturing the chip integrated module 40E, it is preferable to perform the steps in the same manner as the manufacturing method described using fig. 20 to 23, with the insulating layer 433 held on the chip 431, before the semiconductor die 41 and the semiconductor die 42 are bonded to the bridge 43B, respectively, and the periphery of the bridge electrode 436 and the bridge electrode 437 are sealed. Thereafter, the method of manufacturing the chip 431 is preferably removed in the state shown in fig. 23. As a method for removing chip 431, for example, the following method can be used: in the case where the chip 431 is formed using silicon, the chip 431 can be removed by dry etching or the like, and in the case where the chip is formed using an inorganic material such as glass, the peeling layer is interposed between the chip 431 and the insulating layer 433 in advance, and the peeling layer is decomposed (ablated) by an energy beam such as a laser to remove the chip 431. As a modification of the method for manufacturing the bridge 43B, the method described with reference to fig. 44 to 47 may be used.

< other variants of chip Integrated Module >

Fig. 49 is a diagram showing a configuration of a part of the chip integrated module according to the modification example of fig. 4. As shown in fig. 49, the chip integrated module 40E according to the present embodiment includes a first die 41E, a second die 42E, a bridge 43E, and sealing members 45E and 46E sealing them. The first die 41E is connected to the bridge 43E via the first connection 47E. In addition, the bridge 43E is connected to the second die 42E via a second connection 48E. Further, the first die 41E is connected to the outside of the chip integrated module 40E via the third connection portion 49E.

The first die 41E includes: a first integrated circuit chip 402E; die electrodes 408E, 410E; wires 404E, 406E connected to the first integrated circuit chip 402E; and insulating layers 412E and 414E in which wirings 404E and 406E are buried. The wirings 404E and 406E are wirings different from the wiring layer included in the first integrated circuit chip 402E. In more detail, the wirings 404E and 406E may be thick film wirings using an insulating film of an organic (or inorganic) resin, which is called a so-called re-wiring (RDL: redistribution Layer). The wiring provided in the second die and the bridge is also referred to as rewiring. The second integrated circuit chip 420 and the third integrated circuit chip 442E described later may have the same configuration as the first integrated circuit chip 402E.

The second die 42E includes: a second integrated circuit chip 420E; die electrode 424E; a wiring 422E connected to the second integrated circuit chip 420E; and insulating layers 426E and 428E in which the wiring 422E is buried.

The bridge 43E includes: a third integrated circuit chip 442E; bridging electrodes 446E, 448E; a wiring 444E connected to the third integrated circuit chip 442E; and insulating layers 450E and 452E in which a wiring 444E is buried. In this embodiment, the wiring 444E constitutes a part of a bridge electrically connected to the first connection portion 47E and the second connection portion 48E. The bridge according to the present embodiment is a column-based suspended bridge (Pillar Suspended Bridege). The wiring 444E according to the present embodiment is electrically connected to the third integrated circuit chip 442E, and the wiring 444E and the third integrated circuit chip 442E are integrated and function as a bridge.

The first connection portion 47E includes columnar connection portions 474E, 472E. In the present embodiment, the columnar connection portion is a columnar conductor (also referred to as a "microcolumn") of a μm size. The columnar connection portions 472E, 474E are columnar conductors formed so as to go from the bridge 43E to the first die 41E. In the present embodiment, the cross-sectional area of the portion of the columnar connection portion 472E connected to the columnar connection portion 474E is larger than the cross-sectional area of the portion of the columnar connection portion 474E connected to the columnar connection portion 472E. In this modification, the columnar connection parts 474E are connected to the die electrodes 408E via solder 478E. In addition, the columnar connection portion 472E is connected to the bridge electrode 446E via solder 476E.

The second connection portion 48E includes columnar connection portions 480E and 482E. The columnar connection portions 480E and 482E are columnar conductors formed so as to go from the bridge 43E to the second die 42E. In this modification, the cross-sectional area of the portion of the columnar connection portion 480E connected to the columnar connection portion 482E is larger than the cross-sectional area of the portion of the columnar connection portion 482E connected to the columnar connection portion 480E. In this modification, the columnar connection 482E is connected to the die electrode 424E via solder 486E. The columnar connection portion 480E is connected to the bridge electrode 448E via solder 484E.

The third connection portion 49E includes a columnar connection portion 492E. The columnar connection 492E is a columnar conductor formed so as to go outward from the first die 41E. The columnar connection 492E is connected to the die electrode 410E via solder 490E. In addition, the columnar connection portion 492E is connected to an electrode pad 494E connected to the outside (e.g., the wide area wiring layer 102 or the like). The third connection portion 49E may have various structures in addition to (or instead of) the structure shown in fig. 49. For example, the third connection portion 49E may include various structures that can be connected to the wide area wiring layer 102 (see fig. 3) provided on the lower side of the electrode pad 494E, such as a deep via, a high post, and a columnar connection portion.

In the present modification, the bridge is described as an example of a die including an integrated circuit chip, but the bridge may not include an integrated circuit chip and mainly include a wiring and an insulating layer in which the wiring is embedded. In the present embodiment, an example in which a die and a bridge are connected by 2 columnar connection portions having different diameters is described. The die and the bridge may be connected by 1 columnar connection portion, or may be connected by 3 or more columnar connection portions.

(first modification)

Fig. 50 is a diagram showing a structure of a chip integrated module according to a first modification of the chip integrated module shown in fig. 49. Among the components of the chip-integrated module 40F shown in fig. 50, the components substantially identical to those of the chip-integrated module 40E shown in fig. 50 are denoted by the same reference numerals, and the description thereof is omitted appropriately.

The chip integrated module 40F according to the first modification example is different from the chip integrated module 40E (see fig. 49) described above in the configuration of the first connection portion, the second connection portion, and the third connection portion. Specifically, in the first modification, the columnar connection portion or the electrode pad is directly connected to another electrode or wiring without solder. More specifically, in the first connection portion according to the first modification, the columnar connection portion 502F is connected to the die electrode 408E and the bridge electrode 446E. In addition, in the second connection portion, the columnar connection portion 504 is connected to the die electrode 424E and the bridge electrode 448E. Also, in the third connection portion, the die electrode 410E is connected to the electrode pad 494E. Here, the columnar connection portion and the die electrode or the bridge electrode, or the die electrode and the electrode pad may be connected by various known techniques related to hybrid bonding.

In the first modification, various conductors are buried in an insulator. Specifically, the die electrodes 408E, 410E, 424E are buried in the insulating film 510F. In addition, the electrode pad 494E and the columnar connection portions 502F, 504F are buried in the insulating layer 512F. The bridge electrodes 446E and 448E are buried in the insulating film 514F. Further, the first die 41E and the second die 42E are sealed with an insulating resin 506F. The die electrode 408E and the columnar connection portion 502F, and the insulating film 510F and the insulating layer 512F can be connected and bonded by selecting an appropriate material system and process conditions among various known techniques related to hybrid bonding. In the same manner, the bridge electrodes 446E and 448E can be connected to and bonded to the insulating layer 512F and the insulating film 514F and the insulating layer 512F.

In the first modification, the bridge includes an integrated circuit chip, but the present invention is not limited to this, and the bridge may not include an integrated circuit chip. Instead of the integrated circuit chip, the bridge may be formed of, for example, a solid chip made of various materials such as silicon and glass.

(second modification)

Fig. 51 is a diagram showing a structure of a chip integrated module according to a second modification of the chip integrated module shown in fig. 49. In the chip integrated module 40G according to the second modification, a deep via hole 520G is formed in the insulating resin 524G of the sealing bridge 43E, and the first die 41E is electrically connected to an external conductor through the deep via hole 520G. More specifically, the deep via hole 520G may be connected to the electrode pad 494E connected to the bridge 43E, and the solder 522G connected to the external conductor may be formed at the end of the deep via hole 520G. Here, the deep via 520G may be formed to have a diameter that becomes larger as going from the electrode pad 494E to the solder 522G. In the second modification, the lower surface of the third integrated circuit chip 442E may be exposed.

In the second modification, the bridge including the bridge 43E is sealed with the insulating resin 524G. Therefore, in the second modification, the bridge is protected by the insulating resin 524G. In addition, the bridge can be sealed, and at the same time, the connection portion of the bridge and other members can be sealed (underfilled). Further, by flattening the portion where the terminals of the die are formed, the pitch of the connection portion with the wide area wiring layer can be made narrower.

(third modification)

Fig. 52 is a diagram for explaining a chip integrated module according to a third modification of the chip integrated module shown in fig. 49. Fig. 52 shows the vicinity of a portion of the third integrated circuit chip 442E and the deep via 520G of the chip integrated module H, which is a modification of the chip integrated module 40G shown in fig. 51. In the third modification, differences from the chip integrated module 40G according to the second modification will be mainly described. The chip-integrated module according to the third modification may have the structure of the chip-integrated module 40G according to the second modification. That is, the configuration not shown in fig. 52 may be substantially the same as the configuration shown in fig. 51. In the chip integrated module 40H according to the third modification, unlike the second modification, the lower surface of the third integrated circuit chip 442E is not exposed. More specifically, the lower side of the third integrated circuit chip 442E is covered with the insulating resin 525G.

(fourth modification)

Fig. 53 is a diagram showing a chip integrated module according to a fourth modification of the chip integrated module shown in fig. 49. In the chip integrated module 40K according to the fourth modification, a wiring layer 570 is formed under the insulating resin 524 in which the bridge 43E is embedded. The first die 41E and the bridge 43E are connected to the wiring formed in the wiring layer 570K.

The wiring layer 570K according to the fourth modification example includes various conductors embedded in an insulating layer, specifically, a wiring 578K and an electrode 576 embedded in insulating layers 572K and 574K. These wiring 578K and the electrode 576K may be electrically connected to an external conductor. According to a fourth modification, terminals can be arranged in the bridge, for example. In addition, for example, direct power supply from the outside to the bridge can be performed.

The third integrated circuit chip 564K according to the fourth modification example includes a functional element 566K having various functions in a region surrounded by a dotted line. The functional element 566K is connected to an electrode 576K formed in the wiring layer 570K through a via 568K formed inside the third integrated circuit chip 564K. In this embodiment, the bridge electrode 446E is connected to the wiring 443K, and the bridge electrode 448E is connected to the wiring 444E. In this way, in the fourth modification, the first die 41E and the second die 42E are connected via the functional element 566K.

In addition, the electrode pad 494E electrically connected to the first die 41E is connected to the wiring 578K of the wiring layer 570K through the high post 560K. Unlike the deep via hole 520G (see fig. 51) described in the second modification, the cross-sectional area from the electrode pad 494E to the wiring 578K may be substantially constant.

(fifth modification)

Fig. 54 is a diagram showing a chip integrated module according to a fifth modification of the chip integrated module shown in fig. 49. In the chip integrated module 40M according to the fifth modification, the bridge mainly includes wiring. Specifically, the bridge 580M according to the fifth modification has various wirings and an insulating layer in which the wirings are embedded, but does not have an integrated circuit chip.

The bridge 580M has a wiring 588M embedded in the insulating layer 582M, and the wiring 588M is connected to the bridge electrodes 446E and 448E. Further, wirings 589M and 590 are embedded in the insulating layers 582M, 584M and 586M. These wirings 589M, 590M are connected to the electrode 576 of the wiring layer 570K through the contact hole 592M.

< other modification of the method for manufacturing a chip Integrated Module >

With reference to fig. 55 to 60, another modification of the method for manufacturing the chip integrated module will be described.

First, a flat support 800 having a release film 802 formed on the surface thereof as shown in fig. 55 is prepared. Various conductors are formed on the release film 802 (forming step). As the support, various supports typified by glass, silicon, and metal can be suitably used. For example, columnar connection portions 806 and 808 protruding from the surface of the support 800 are formed on the release film 802. In addition, electrode pads 804, 809 may be formed on the release film 802.

Next, as shown in fig. 56, a plurality of dies including a first die 81E and a second die 82E are bonded to various conductors formed over a release film 802. The first die 81E has: the first integrated circuit chip 810, a wiring layer 812 formed on a surface of the first integrated circuit chip 810, and various electrodes including die electrodes 814, 816 formed on a surface of the wiring layer 812. In addition, the second die 82E has: the second integrated circuit chip 820, a wiring layer 822 formed on a surface of the second integrated circuit chip 820, and various electrodes including die electrodes 824, 826 formed on a surface of the wiring layer 822.

In the present embodiment, die electrodes formed on a die are coupled to various conductors (die coupling step). For example, the die electrode 814 and the die electrode 816 of the first die 81E are coupled to the electrode pad 804 and the columnar connection 806, respectively. In addition, the die electrode 824 and the die electrode 826 of the second die 82E are coupled to the electrode pad 809 and the columnar connection 808, respectively. The die electrode may be connected to the electrode pad or the columnar connection portion via solder, or may be coupled to the electrode pad or the columnar connection portion by hybrid bonding without solder.

Next, as shown in fig. 57, various conductors and a plurality of dies formed on the release film 802 are sealed with a resin 818 (sealing member) (sealing process). The first die 81E and the second die 82E may be sealed in advance with an insulating resin such as injection and curing (Capillary Underfill: capillary Underfill) using capillary phenomenon caused by liquid Underfill resin or NCF (Non Conductive Film: non-conductive film) before the sealing step with resin 818, or may be sealed simultaneously (Mold Underfill) in the sealing step with resin 818. Thereby, the plurality of dies are fixed in a state of being coupled to the columnar connection portion and the metal pad.

Next, as shown in fig. 58, a process is performed to remove the release film 802 and the support 800, and remove the release film remaining in the electrode pad and the like. As a method for removing the support, various methods such as a method of mechanically peeling the support, a method of peeling the support by irradiating a peeling film with laser light, and a method of removing the support by grinding or etching, as the case may be, can be used. In the case of a polishing or etching-based method, there is sometimes no need to peel off the film. Further, the resin 818 on the surface side of the die is polished. Thereby, the die can be exposed. Hereinafter, according to the method described with reference to fig. 55 to 58, as shown in fig. 58, a resin in which various conductors and a plurality of dies are embedded and polished is also referred to as an intermediate 84E.

Next, as shown in fig. 59, the bridge is coupled to the plurality of columnar connection portions (bridge coupling process). In the present embodiment, each of the plurality of dies including the bridge 83E is used as a bridge, and the bridge is coupled to the respective lower portions of the plurality of columnar connection portions. In the present embodiment, the bridge 83E has: the third integrated circuit chip 830, a wiring layer 832 formed on a surface of the third integrated circuit chip 830, and bridge electrodes (including bridge electrodes 834, 836) formed over the wiring layer 832.

Bridge 83E has a bridge electrode 834 coupled to the pillar connection 806 connected to the first die 81E. Also, the bridge 83E has a bridge electrode 836 coupled to the pillar connection 808 connected to the second die 82E. Thus, the bridge 83E functions as a bridge electrically connected to the first die 81E and the second die 82E, and a structure having the characteristics of a column-based suspension bridge is formed. Note that the bridge electrode may be coupled to the columnar connection portion via solder, or may be coupled to the columnar connection portion by hybrid bonding without solder.

Next, as shown in fig. 60, the resin 818 is cut so as to be divided for each chip integrated module 80. Thereby, each chip integrated module is formed individually.

According to the method of manufacturing the chip integrated module according to the present embodiment, as described with reference to fig. 57, after the first die, the second die, and the columnar connection portion are fixed with the resin, the subsequent steps are performed. Therefore, in the subsequent steps, the positional relationship of the plurality of dies does not shift, and the integrated circuit chips can be connected to each other with higher accuracy. In addition, more simple steps and treatments can be performed. Further, the external terminals can be formed directly under the integrated circuit chip, and excellent characteristics can be expected in terms of Power Integrity (PI) and Signal Integrity (SI). Further, since stable relative positional accuracy of the die can be ensured independently of the size of the module, expansion of the Panel-salt to large-scale chip integration becomes easy according to the present embodiment.

(sixth modification)

Fig. 61 to 64 are diagrams for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in fig. 55 to 60. In the sixth modification, a method for manufacturing a chip-integrated module having the same configuration as the chip-integrated module 40F according to the second modification described with reference to fig. 50 will be described.

First, a plurality of intermediate bodies 84E embedded in a resin 818 are prepared in the same manner as in the method described above with reference to fig. 55 to 58.

The next step will be described with reference to fig. 61. First, a bridge is connected to a columnar connection portion. The bridge according to the sixth modification example includes a wiring layer 946 and an integrated circuit chip 948. The wiring layer 946 has a wiring (not shown in fig. 61) connected to a plurality of bridge electrodes. The bridge electrode is connected to the columnar connection portion. For example, bridge electrode 942 is connected to columnar connection 806, and bridge electrode 944 is connected to columnar connection 808. Thus, the bridge electrodes 942 and 944, the wiring layer 946, and the integrated circuit chip function as a bridge.

Further, the die electrode, the wiring layer, and the integrated circuit chip are covered and resin-sealed (fig. 61). Further, the integrated circuit chip is exposed by polishing or the like (fig. 62).

The next step will be described with reference to fig. 62. In fig. 61, the lower surface of the integrated circuit chip is covered with a resin 940. The lower surface of the integrated circuit chip and the resin 940 of the lower surface are polished. Thus, as shown in fig. 62, the lower surface of the integrated circuit chip is exposed.

The next step will be described with reference to fig. 63. In this step, an opening 950 of a via hole is formed in the resin 940 in which the integrated circuit chip is embedded. For example, the opening 950 may be formed in the resin by irradiating laser light to the resin 940. For example, the opening 950 may be formed such that an electrode pad 809 connected to the integrated circuit chip is exposed. In addition, the opening 950 of the formed through-hole may be formed to have a diameter that becomes larger as going downward from the electrode pad 809.

The next step will be described with reference to fig. 64. In this step, a metal is formed in the opening formed in the resin 940 by plating, for example, and solder is provided at the end portion thereof. Thus, as shown in fig. 64, a deep through hole 952 having solder 954 at the end is formed in the resin 940. Further, by cutting the resins 818 and 940, the chip integrated modules can be singulated into a desired size.

In the sixth modification, the description was made of the case where the lower surface and the resin 940 of the lower surface of the integrated circuit chip are polished, but the present invention is not limited to this, and the opening 950 may be formed without polishing the resin 940 or the like, and a deep through hole having solder provided at the end portion of the opening 950 may be formed. This makes it possible to produce the chip integrated module described in the third modification.

(seventh modification)

A method for manufacturing a chip integrated module according to a seventh modification will be described with reference to fig. 65 to 66. In the seventh modification, first, an intermediate 84E is produced as described with reference to fig. 55 to 58.

The next step will be described with reference to fig. 65. In this step, a high support 962 is formed on the electrode pad 809 embedded in the resin 818 or a bridge is bonded to the connection portion. The bridge according to the seventh modification has a wiring layer 964 and an integrated circuit chip 966. The wiring layer 964 has a wiring, and is connected to, for example, columnar connection portions 806 and 808 via bridge electrodes provided on the surface of the wiring, thereby functioning as a bridge.

Further, the resin sealing is performed so as to cover the formed high pillars and the bridges coupled to the columnar connection portions (fig. 64). Further, the high posts and the bridge are exposed by grinding or the like (fig. 65).

The next step will be described with reference to fig. 66. In this step, the resin 960 sealing the high post and the bridge, the high post, and the integrated circuit chip are polished. Thus, as shown in fig. 66, the surface of the high post and the integrated circuit chip is exposed on the surface of the resin 960. Further, by cutting the resins 818 and 960, a chip integrated module having a desired size can be manufactured.

(eighth modification)

A method for manufacturing a chip integrated module according to an eighth modification will be described with reference to fig. 67 to 69. In the eighth modification, first, as described with reference to fig. 55 to 58, an intermediate 84E is prepared.

The next step will be described with reference to fig. 67. In this step, the bridge is bonded to the connection portion embedded in the resin 818. The bridge according to the eighth modification has a wiring layer 986 and an integrated circuit chip 988. The wiring layer 986 has wiring. The bridge electrode provided on the surface of the wiring is connected to the columnar connection portions 806 and 808, and the bridge electrode and the wiring layer 986 function as a bridge.

Further, the wiring layer 986 and the bridge electrode formed on the wiring layer 986 are sealed with resin. Thus, as shown in fig. 67, in a state where the die electrode and the wiring layer 986 are fixed by the resin 980, the bridge is connected to the columnar connection portion.

The next step will be described with reference to fig. 68. In this step, the integrated circuit chip 988 is removed from the wiring layer 986. Further, by cutting the resin 818, a chip integrated module of a desired size can be manufactured.

The process of removing the integrated circuit chip 988 from the wiring layer 986 is described in detail with reference to fig. 69. In the eighth modification, a peeling layer 996 is provided between the integrated circuit chip 988 and the insulating layer 994 of the wiring layer. By irradiating the release layer 996 with energy particles 981 (for example, laser light or the like), at least a part of the release layer 996 can be decomposed (modified). By moving the region irradiated with the energy particles in the scanning direction indicated by the arrow, the peeling layer 996 can be entirely decomposed. Thereby, the integrated circuit chip 988 can be removed from the insulating layer 994.

Here, an example in which the peeling layer 996 is decomposed by scanning the region to which the energy particles are irradiated is described, but the present invention is not limited to this, and the energy particles may be irradiated to the entire peeling layer 996 at one time without scanning.

Method for manufacturing optical module

A method for manufacturing an optical module according to an embodiment of the present invention will be described with reference to fig. 70 to 74.

First, a support 850 having a release layer 852 formed on the surface thereof is prepared. Next, as shown in fig. 70, a wiring layer 860 is formed on the surface of the peeling layer 852. The wiring layer 860 may have a 2-layer structure, and more specifically, may have substantially the same configuration as the wiring layer 630 described with reference to fig. 5. In this embodiment, a plurality of conductor vias are formed in a layer above the wiring layer 630, and electrodes are coupled to the respective conductor vias. For example, the electrode 862 connected to the conductor post is coupled to the conductor via 861, and the electrode 864 connected to the optical element driving chip is coupled to the conductor via 863.

Next, as shown in fig. 71, the conductor pillar 870 and the optical element driving chip 880 are coupled to the electrodes. For example, conductor post 870 is coupled to electrode 862. In addition, the light element driving chip 880 has a plurality of electrode terminals 874. The electrode terminal 874 is connected to an electrode 872 formed on the surface of the wiring layer 860 via a solder 782.

Next, as shown in fig. 72, the plurality of conductor pillars 870 and the optical element driving chip 880 are sealed with a resin 882. Thereby, the plurality of conductor posts 870 and the optical element driving chip 880 are fixed.

Next, a process is performed to remove the peeling layer 852 and the support 850, and to remove the peeling layer 852 remaining on the lower surface of the wiring layer 860. Further, as shown in fig. 73, a metal layer 884 is formed on the upper surface of the optical element driving chip 880 on the upper surface of the polishing resin 882.

Next, as shown in fig. 74, the entire metal layer 884 is turned upside down so as to be a lower surface, and the optical element chip 890 is bonded to the upper surface of the wiring layer 860. The light-emitting element 892, the light-receiving element 894, and a plurality of electrode terminals 896 are provided in the light-element chip 890. Each of the plurality of electrode terminals 896 is bonded to an electrode 866 of the wiring layer 860 via a solder 868, whereby the optical element chip 890 is bonded to the wiring layer 860. The lower side of the light-emitting element chip 890, the light-emitting element 892, the light-receiving element 894, and the plurality of electrode terminals 896 are sealed with a resin 898. Thereby manufacturing the optical module 89.

Modification of the method for manufacturing a chip Integrated

A method for manufacturing a chip integrated body according to another embodiment will be described with reference to fig. 75 to 79.

First, as shown in fig. 75, a support 900 having a release layer 902 formed on the surface thereof is prepared, and various conductors are formed on the surface of the release layer 902. Specifically, an electrode 906 to which a conductor pillar is connected, a pillar-shaped connection portion 908 (high pillar) to which a chip integrated module is connected, and the like are formed.

Next, as shown in fig. 76, various members are formed on various conductors formed over the peeling layer 902. For example, a conductor post 907 may be formed at the electrode 906, or a chip integrated module 909 may be connected at a post connection 908. The chip integrated module 909 may be connected to the columnar connection 908 by solder disposed over the columnar connection 908. In the case where the thickness of the bridge of the chip integrated module is sufficiently thin, the columnar connection portion 908 may also replace the solder bump having a lower height than it.

Next, as shown in fig. 77, the various members formed are sealed with resin. Specifically, the conductor post 907, the columnar connection portion 908, the chip integrated module 909, and the like may be sealed with a resin 914. After that, the support 900 is removed from the wiring layer 904 together with the peeling layer 902. Further, the resin 914 is ground to expose the conductor posts 907 and the chip integrated module 909.

Next, as shown in fig. 78, a wiring layer 912 is formed over the resin 914. More specifically, the wiring layer 912 is formed over the resin 914 in such a manner that the wiring included in the wiring layer 912 is connected to the exposed portion of the conductor post 907 or the exposed portion of the chip integrated module 909. For example, the electrode 916 formed over the wiring layer 912 may be connected to the conductor post 907 through a conductor via. In addition, the contact metal 918 may be connected to the chip integrated module 909 through a conductor via.

Next, as shown in fig. 79, a heat dissipation mechanism 922 is mounted on the contact metal 918. Further, the optical module 917 to which the optical wiring 920 is connected to the electrode 916. Thus, the chip integrated body according to the present embodiment is fabricated.

Integrated circuit chip

Fig. 80 is a diagram showing a configuration example of an integrated circuit chip according to an embodiment. Integrated circuit chip 35 includes wiring layer 350, transistor 370, and connection layer 390 connecting wiring layer 350 and transistor 370.

The wiring layer 350 has a laminated structure of 5 layers, each layer having a film for insulating an interlayer, a wiring embedded in the film, and a via hole for connecting the wirings of the layers adjacent to each other. For example, the wiring 352 of the second layer and the wiring 354 of the third layer are connected via a via 353, and the wiring 354 is buried in an insulating film 356. The film of each layer may be formed of, for example, BPSG (Boron-Phosphorous Silicate Glass: borophosphosilicate glass). The wiring included in each layer may be made of a metal such as copper. Since the wiring of the upper layer (for example, the fifth layer and the fourth layer) is power or ground, the wiring may not be finer than the wiring of the other layer.

While several exemplary embodiments have been described above with reference to the drawings, various modifications are possible in the above-described embodiments and modifications. Some of the embodiments may be modified as appropriate within a range that does not contradict the above description. Further, for example, some of the above embodiments and modifications may be applied in combination with some of the other embodiments.

In the above-described embodiment, examples of the substantially vertical direction of the surfaces of the various columnar connection portions facing the die are mainly described. The columnar connection portions may be formed to face any direction as long as they extend in the direction toward the other die. The columnar connecting portion can be appropriately set in various dimensions, cross-sectional shapes, aspect ratios (ratio of dimension in the cross-sectional direction to dimension in the direction perpendicular thereto), and the like, according to requirements from performance, reliability, and the like, optional manufacturing processes, and the like.

In the above-described embodiment, an example was described in which in the case where the bridge includes a chip, the bridge mainly includes a wiring via which the chip is connected to the bridge electrode. The bridge is not limited thereto, and the chip may be directly connected to the bridge electrode without including a wiring.

In addition, in the above-described embodiments, examples in which various dies (e.g., a first die, a second die, and the like) include wiring have been mainly described. Without limitation thereto, the die may not include wiring. In this case, the integrated circuit chip that the die has may be directly connected to the die electrode.

In the above embodiment, the thin film wiring layer formed on the support 900 is used as the wiring 904, but the wiring 904 is not limited to this, and various known inserters or wiring substrates may be used.

Industrial applicability

The present invention can be widely applied to semiconductor modules and the like.

Claim (modification according to treaty 19)

1. A method of manufacturing a semiconductor module, comprising:

a step (a) of forming, on a first surface of a first support body, a first connection portion including a first columnar connection portion extending in an out-of-plane direction of the first surface, and a second connection portion including a second columnar connection portion extending in the out-of-plane direction of the first surface;

a step (b) of preparing a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, and a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, each of the first semiconductor die and the second semiconductor die being mounted on the first support in such a manner that the first die electrode is arranged on the first connection portion and the second die electrode is arranged on the second connection portion;

a step (c) of sealing the first semiconductor die, the second semiconductor die, the first connection portion, and the second connection portion with a first sealing body after the step (b);

A step (d) of removing the first support body and exposing a part of the first columnar connection portion and a part of the second columnar connection portion from the first sealing body, respectively, after the step (c);

and (e) preparing a bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, wherein after the step (d), the bridge is mounted on a structure sealed with the first sealing body so that the first bridge electrode is disposed on the first columnar connection portion and the second bridge electrode is disposed on the second columnar connection portion.

2. The method for manufacturing a semiconductor module according to claim 1, wherein,

further comprising a step (f) of sealing the first bridge electrode and the second bridge electrode with a second sealing body after the step (e).

3. The method for manufacturing a semiconductor module according to claim 2, wherein,

the first seal includes a plurality of first filler particles,

the second seal includes a plurality of second filler particles,

the average particle size of the plurality of first filler particles is greater than the average particle size of the plurality of second filler particles.

4. The method for manufacturing a semiconductor module according to claim 1, wherein,

in the step (a), each of the first and second connection portions is formed on a seed layer of a substrate,

in the step (b), the side surfaces of the first connection portion and the side surfaces of the second connection portion are covered with an oxide film.

5. The method for manufacturing a semiconductor module according to claim 4, wherein,

in the step (b) of the above-mentioned process,

the first die electrode is bonded to the first connection portion via a solder material,

the second die electrode is bonded to the second connection portion via a solder material.

6. The method for manufacturing a semiconductor module according to claim 4, wherein,

in the step (e) of the above-mentioned process,

the first bridge electrode is bonded to the first connection portion via a welding material,

the second bridge electrode is bonded to the second connection portion via a welding material.

7. The method for manufacturing a semiconductor module according to claim 1, wherein,

in the step (e), the step of preparing the bridge further includes:

a step (e 1) of sequentially forming a first insulating layer, a wiring, and a second insulating layer on a second support in a stacked manner;

A step (e 2) of bonding the second insulating layer on the second support to a substrate via a third insulating layer thicker than the second insulating layer after the step (e 1);

a step (e 3) of removing the second support after the step (e 2);

and (e 4) forming the first bridge electrode and the second bridge electrode electrically connected to the wiring on the first insulating layer after the step (e 3).

8. A method of manufacturing a semiconductor module, comprising:

a step (a) of forming a first opening and a second opening in a first insulating layer on a first surface of a first support after the first insulating layer is formed;

a step (b) of forming a first connection portion including a first columnar connection portion formed in the first opening portion and a second connection portion including a second columnar connection portion formed in the second opening portion;

a step (c) of preparing a first semiconductor die having a first IC chip, a first die electrode connected to the first IC chip, and a second insulating layer sealing the first die electrode, and a second semiconductor die having a second IC chip, a second die electrode connected to the second IC chip, and a third insulating layer sealing the second die electrode, and mounting each of the first semiconductor die and the second semiconductor die on the first support such that the first die electrode is arranged on the first connection portion and the second die electrode is arranged on the second connection portion;

A step (d) of sealing the first semiconductor die and the second semiconductor die with a first sealing body after the step (c);

a step (e) of removing the first support body and exposing a part of the first columnar connection portion and a part of the second columnar connection portion from the first insulating layer, respectively, after the step (d);

a step (f) of preparing a bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, and, after the step (e), mounting the bridge on a structure sealed with the first sealing body so that the first bridge electrode is arranged on the first columnar connection portion and the second bridge electrode is arranged on the second columnar connection portion,

in the step (c) of the above-mentioned process,

the first insulating layer and the second insulating layer are bonded to each other, and the first die electrode is sealed by the first insulating layer and the second insulating layer,

the first insulating layer and the third insulating layer are bonded to each other, and the second die electrode is sealed by the first insulating layer and the third insulating layer.

9. The method for manufacturing a semiconductor module according to claim 8, wherein,

in the step (b) of the above-mentioned process,

10. The method for manufacturing a semiconductor module according to claim 9, wherein,

the bridge prepared in the step (f) further has a fourth insulating layer sealing a portion of each of the first bridge electrode and the second bridge electrode,

in the step (f) of the above-mentioned method,

the second bridging electrode is bonded to the second connection portion via a solder material,

the first insulating layer and the fourth insulating layer are bonded to each other.

11. A semiconductor module (after modification) is provided with:

a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip;

a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip;

a first connection portion electrically connected to the first die electrode;

A second connection portion electrically connected to the second die electrode;

a bridge having a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion; and

a first encapsulant encapsulating the first semiconductor die and the second semiconductor die,

the first connection portion includes a first columnar connection portion arranged between the first semiconductor die and the bridge, extending in a direction from one of the first semiconductor die and the bridge to the other,

the second connection portion includes a second columnar connection portion disposed between the second semiconductor die and the bridge, extending in a direction from one of the second semiconductor die and the bridge to the other,

the first bridge electrode and the second bridge electrode are exposed from the first sealing body, and each of the first columnar connection portion and the second columnar connection portion is sealed by the first sealing body.

12. The semiconductor module of claim 11, wherein,

each of the first bridge electrode and the second bridge electrode is sealed by a second sealing body.

13. The semiconductor module of claim 11, wherein,

the first seal includes a plurality of first filler particles,

the second seal includes a plurality of second filler particles,

14. The semiconductor module of claim 11, wherein,

the side surfaces of the first connection portion and the second connection portion are covered with an oxide film.

15. The semiconductor module of claim 11, wherein,

the bridge has:

a chip;

a first insulating layer, a second insulating layer, and a third insulating layer sequentially stacked on the chip; and

a wiring sandwiched between the second insulating layer and the third insulating layer, connected to each of the first bridge electrode and the second bridge electrode,

the thickness of the first insulating layer is thicker than the thickness of the second insulating layer.

16. An electronic device is provided with:

a first die having a first electrode;

a second die having a second electrode;

a first connection part electrically connected to the first electrode;

a second connection part electrically connected to the second electrode; and

A bridge electrically connected to the first connection portion and the second connection portion,

the first connection has a columnar connection from the bridge to the first die.

17. The electronic device of claim 16, wherein,

the columnar connection portion has: a first columnar connection from the bridge to the first electrode; and a second columnar connection portion connected to an end portion of the first columnar connection portion, from the end portion of the first columnar connection portion to the first electrode,

the cross-sectional area of the portion of the first columnar connection portion connected to the second columnar connection portion is larger than the cross-sectional area of the portion of the second columnar connection portion connected to the first columnar connection portion.

18. The electronic device of claim 16 (after modification), wherein,

the semiconductor device further includes a sealing member that seals the first die, the second die, the first connection portion, and the second connection portion in an integrated manner.

19. The electronic device of claim 16 (after modification), wherein,

the device further comprises: a first sealing member that seals the first die and the second die in an integrated manner; and a second sealing member that seals the first connecting portion and the second connecting portion in an integrated manner.

20. The electronic device of claim 16, wherein,

the bridge is connected to the columnar connection portion via solder.

21. The electronic device of claim 16, wherein,

the first die is connected to the first connection by hybrid bonding,

the second die is connected to the second connection by hybrid bonding,

the first die and the second die are integral and encapsulated by an encapsulation member.

22. An electronic module is provided, which comprises a first electronic module and a second electronic module,

the device is provided with: the electronic device of claim 16;

a wiring layer in which wiring is provided; and

and a connection unit electrically connecting the wiring to the electronic device.

23. The electronic module of claim 22, wherein,

the first die has a third electrode with a third connection electrically connected,

the first die, the third electrode, and the third connection are integral and sealed by a sealing member,

the third connection portion penetrates and connects the sealing member to the wiring layer.

24. A method of manufacturing an electronic device (after modification), comprising:

a forming step of forming a first connection portion and a second connection portion including a columnar connection portion protruding from a support body on the support body;

A die coupling step of coupling a first electrode of a first die to the first connection portion and coupling a second electrode of a second die to the second connection portion;

a sealing step of sealing the first die, the second die, and the first connection portion with resin; and

and a bridge coupling step of coupling a bridge to the lower part of the first connection part and the lower part of the second connection part.

25. The method for manufacturing an electronic device according to claim 24 (after modification), wherein,

the first connecting portion has a first columnar connecting portion and a second columnar connecting portion, and the forming step includes:

forming the first connection portion on the support body so that the first connection portion protrudes from the support body toward the first die; and

a step of forming a second connection portion on the first connection portion so that the second columnar connection portion protrudes from the first columnar connection portion toward the first die,

the cross-sectional area of the portion of the first columnar connection portion connected to the second columnar connection portion is larger than the cross-sectional area of the portion of the second columnar connection portion connected to the first columnar connection portion,

The die coupling process includes a process of connecting the first die to the second cylindrical connection.

Claims

1. A method of manufacturing a semiconductor module is provided,

comprising the following steps: a step (a) of forming, on a first surface of a first support body, a first connection portion including a first columnar connection portion extending in an out-of-plane direction of the first surface, and a second connection portion including a second columnar connection portion extending in the out-of-plane direction of the first surface;

the first seal includes a plurality of first filler particles,

the second seal includes a plurality of second filler particles,

in the step (b) of the above-mentioned process,

in the step (e) of the above-mentioned process,

in the step (e), the step of preparing the bridge further includes:

a step (e 3) of removing the second support after the step (e 2);

8. A method of manufacturing a semiconductor module is provided,

comprising the following steps: a step (a) of forming a first opening and a second opening in a first insulating layer on a first surface of a first support after the first insulating layer is formed;

in the step (c) of the above-mentioned process,

in the step (b) of the above-mentioned process,

in the step (f) of the above-mentioned method,

11. A semiconductor device, which is a semiconductor device,

the device is provided with: a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip;

a first connection portion electrically connected to the first die electrode;

a second connection portion electrically connected to the second die electrode;

the first connection portion includes a second columnar connection portion disposed between the first semiconductor die and the bridge, extending in a direction from one of the first semiconductor die and the bridge to the other,

12. The semiconductor module of claim 11, wherein,

13. The semiconductor module of claim 11, wherein,

the first seal includes a plurality of first filler particles,

the second seal includes a plurality of second filler particles,

14. The semiconductor module of claim 11, wherein,

15. The semiconductor module of claim 11, wherein,

the bridge has:

a chip;

16. An electronic device, such as a portable electronic device,

the device is provided with: a first die having a first electrode;

a second die having a second electrode;

a first connection part electrically connected to the first electrode;

a second connection part electrically connected to the second electrode; and

17. The electronic device of claim 16, wherein,

18. The electronic device of claim 16, wherein,

the semiconductor device further includes a sealing member that seals the first die and the second die in an integrated manner.

19. The electronic device of claim 16, wherein,

the bridge includes a chip.

20. The electronic device of claim 16, wherein,

the bridge is connected to the columnar connection portion via solder.

21. The electronic device of claim 16, wherein,

The first die is connected to the first connection by hybrid bonding,

the second die is connected to the second connection by hybrid bonding,

the device is provided with: the electronic device of claim 16;

a wiring layer in which wiring is provided; and

23. The electronic module of claim 22, wherein,

24. A method for manufacturing an electronic device, comprising,

comprising the following steps: a forming step of forming, on a support, a first connection portion and a second connection portion including columnar connection portions protruding from the columnar support;

25. The method for manufacturing an electronic device according to claim 24, wherein,

the first connecting part is provided with a columnar first columnar connecting part and a columnar second columnar connecting part,

the forming step includes: forming the first connection portion on the support body so that the first connection portion protrudes from the support body toward the first die; and a step of forming a second connection portion on the first connection portion so that the second columnar connection portion protrudes from the first columnar connection portion toward the first die,