CN117767943A - Sinc filter and electronic equipment - Google Patents
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- CN117767943A CN117767943A CN202311672233.1A CN202311672233A CN117767943A CN 117767943 A CN117767943 A CN 117767943A CN 202311672233 A CN202311672233 A CN 202311672233A CN 117767943 A CN117767943 A CN 117767943A
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Abstract
The application provides a Sinc filter and electronic equipment, and relates to the technical field of digital-to-analog conversion and digital filtering thereof. The Sinc filter is applied to a periodic reset system and comprises an integrator, a decimator and a comb, wherein the integrator, the decimator and the comb are sequentially connected; the integrator comprises a plurality of cascaded integrating units, each integrating unit comprises an adder and a first register which are connected with each other, and the first register is positioned on the delay branch; in the first n-stage integration unit, the data bit width of the first register is smaller than the standard value of the Hogenaure structure, and the standard value is determined according to the bit width of the output signal of the Sinc filter, wherein n is more than or equal to 1. The Sinc filter and the electronic device have the advantage of reducing the consumption of resources and the area.
Description
Technical Field
The application relates to the technical field of digital-to-analog conversion and digital filtering thereof, in particular to a Sinc filter and electronic equipment.
Background
In a digital-analog hybrid chip, digital circuits in the same chip often generate strong interference to analog circuits, and the interference can bring about the loss of the performance of the analog circuits. A conventional nyquist sampling rate analog-to-digital converter (ADC) is difficult to achieve with high accuracy in such an environment.
For this reason, research and development of high-precision ADCs have become ADC hot spots in recent years, and ADCs employing oversampling and sigma-delta structures are representative of this field in that they have significant advantages in terms of high precision. This structure reduces the requirements for analog circuitry, however, greatly increases the complexity of the digital circuitry. The digital decimation filter has a large number of arithmetic circuits as a necessary module, and its physical implementation will consume a significant amount of hardware resources, especially when the bit width and the order are high, and will typically occupy a large portion of the entire ADC chip.
In summary, the filter in the prior art has the problems of serious resource consumption and large occupied area.
Disclosure of Invention
The purpose of the application is to provide a Sinc filter and electronic equipment, so as to solve the problems of serious resource consumption and large occupied area of the filter in the prior art.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in one aspect, an embodiment of the present application provides a Sinc filter, applied to a period reset system, where the Sinc filter includes an integrator, a decimator, and a comb, where the integrator, the decimator, and the comb are sequentially connected;
the integrator comprises a plurality of cascaded integrating units, wherein each integrating unit comprises an adder and a first register which are connected with each other, and the first register is positioned on a delay branch; wherein,
in the first n-stage integration unit, the data bit width of the first register is smaller than the standard value of the Hogenaure structure, and the standard value is determined according to the bit width of the output signal of the Sinc filter, wherein n is more than or equal to 1.
Optionally, in the first n-stage integrating unit, the data bit width of the first register satisfies the formula:
Yn＝Q*Log 2 (R*N)
wherein Yn represents the data bit width of the first register in the nth stage integration unit, Q represents the number of stages of the integration unit, R represents the downsampling rate, and N represents the number of stages of the Sinc filter.
Alternatively, the standard value of the Hogenaure structure satisfies the formula:
Wj＝B max -B j
wherein Bmax represents the intermediate quantity, N represents the number of stages of the Sinc filter, R represents the downsampling rate, bin represents the input quantity, bj represents the number of bit widths of the j-th low-order truncations, fj represents the sum of error variances of the previous j-th order, and σT 2N+1 Representing the variance of the error source of the last stage, wj represents the standard value of the data bit width of the first register of the jth stage integration unit in the Hogenaure structure, and the sign is thatRepresenting the rounding up, the sign->Representing a rounding down.
Optionally, when the integrator includes four integrating units, the data bit width of the first register in the first integrating unit is 16 bits, and the data bit width of the first register in the second integrating unit is 32 bits.
Optionally, a plurality of the integration units are connected in a running water manner.
Optionally, in the integrator, a first register of a previous stage integration unit is connected to an adder of a next stage integration unit, the adder of the first stage integration unit is used for receiving an input signal, and a first register of the last stage integration unit is connected to the decimator.
Optionally, the comb includes a plurality of differential units, the number of the differential units is equal to that of the integral units, each differential unit includes a subtracter and a second register, the second register is located on the delay branch, and the data bit width of the second register of the plurality of differential units is gradually reduced.
Optionally, the comb includes a third register, a full-add module, and a fourth register, where the decimator, the third register, the full-add module, and the fourth register are sequentially connected, and the third register, the full-add module, and the fourth register further respectively receive different control signals, and perform addition or subtraction logic under control of the control signals.
Optionally, the full adder module includes an inverter, a selector and a full adder, a first tap of the third register is connected to a first port of the selector, a second tap of the third register is connected to a second port of the selector through the inverter, and the selector, the full adder and the fourth register are sequentially connected.
On the other hand, the embodiment of the application also provides electronic equipment, which comprises the Sinc filter.
Compared with the prior art, the application has the following beneficial effects:
the application provides a Sinc filter and electronic equipment, wherein the Sinc filter is applied to a period resetting system and comprises an integrator, a decimator and a comb, and the integrator, the decimator and the comb are connected in sequence; the integrator comprises a plurality of cascaded integrating units, each integrating unit comprises an adder and a first register which are connected with each other, and the first register is positioned on the delay branch; in the first n-stage integration unit, the data bit width of the first register is smaller than the standard value of the Hogenaure structure, and the standard value is determined according to the bit width of the output signal of the Sinc filter, wherein n is more than or equal to 1. In the Sinc filter provided by the application, the register bit width of the n-level integration unit is optimized under the application scene of periodic reset, and the unused registers of high-order bits are removed, so that the consumption resource and area of the whole Sinc filter are reduced.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a 4-stage filter in the prior art.
Fig. 2 is a schematic diagram of another circuit structure of a 4-stage filter in the prior art.
Fig. 3 is a schematic circuit structure of a first 4-order Sinc filter according to an embodiment of the disclosure.
Fig. 4 is a schematic diagram of a second circuit structure of a 4-order Sinc filter according to an embodiment of the disclosure.
Fig. 5 is a schematic diagram of a third circuit structure of a 4-order Sinc filter according to an embodiment of the present application.
Fig. 6 is a timing chart corresponding to the control signal in fig. 5 according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As described in the background, currently, digital decimation filters (Sinc filters) have a large number of arithmetic circuits, and their physical implementation will severely consume hardware resources when both bit width and order are high, and will typically occupy a large portion of the area of the entire ADC chip.
In the following, a 4 th order Sinc filter is taken as an example, and the resource consumption is described, and for convenience of understanding, in this application, the 4 th order Sinc filter is taken as an example, but it should be understood that, in practical application, the order of the Sinc filter is not limited, for example, the Sinc filter may be 5 th order or 6 th order. Referring to fig. 1, fig. 1 shows a structure diagram of a 4-order filter, where the Sinc filter includes an integrator, a decimator and a differentiator, the decimator with a decimation rate R is indicated in the middle, the integrator formed by an adder and a register is left of the decimator, the differentiator formed by a subtractor and a register is right of the decimator, and the order of the filter refers to the number of the integrator and the differentiator. In this example, the decimator has 4 cascaded integrators to the left and 4 cascaded differentiators to the right, thus representing a 4-order filter.
As can be seen, the filter itself consumes 57×8=456 register resources without considering other control logic, and the large bit width adder circuit (the right subtractor can be considered as a complement to the adder by one number, so in a specific circuit implementation, an adder implementation can also be used) is 8.
The above-described circuit is enormous both for the resource consumption of the registers and the consumption of the adders. In view of this situation, hogenauer proposed a new structure in 1981, as shown in fig. 2, to improve the Sinc filter by using the Hogenauer "clipping" theory, not only saves the computing hardware resources, but also effectively improves the performance of the Sinc filter. Specifically, for the filter shown in fig. 1, each integrator and the differentiator consume 57 data-bit wide registers, and after "pruning" theoretical optimization, the first integrator consumes 57 data-bit wide registers, the second integrator consumes 56 data-bit wide registers, the third integrator consumes 43 data-bit wide registers, the fourth integrator consumes 30 data-bit wide registers, the first differentiator consumes 24 data-bit wide registers, the second differentiator consumes 23 data-bit wide registers, the third differentiator consumes 22 data-bit wide registers, and the fourth differentiator consumes 21 data-bit wide registers, so that the optimized registers consume 57+56+43+30+24+23+22+21=262 registers, reducing the consumption of registers and reducing the certain occupied area of the filter.
However, for the Hogenauer architecture described above, register resource consumption is still excessive and the number of adders (still 8) is not reduced. The combinational logic used throughout the circuit may be time-sequential. In addition, for the periodic reset scene, for example, when the digital filtering processing is performed on the Sigma-Detal ADC modulator with the reset signal, certain resource waste exists, and certain optimizing space is provided.
In view of the above, in order to solve the above problems, the present application provides a Sinc filter, and the Sinc filter provided in the present application is exemplified below:
as an alternative implementation, the Sinc filter includes an integrator, a decimator, and a comb, which are connected in sequence; the integrator comprises a plurality of cascaded integrating units, each integrating unit comprises an adder and a first register which are connected with each other, and the first register is positioned on the delay branch; in the first n-stage integration unit, the data bit width of the first register is smaller than the standard value of the Hogenaure structure, and the standard value is determined according to the bit width of the output signal of the Sinc filter, wherein n is more than or equal to 1.
In particular, the applicant has found that for a use scenario of periodic reset (periodically resetting), for example when applied to digital filtering processing of Sigma-total ADC modulators with reset signals, the maximum input data does not exceed 65536 and there is no case where the input data is all 1, so there is still a significant waste of register resources for the filter structure shown in fig. 2. In view of this, the applicant has re-optimized the filter circuit structure shown in fig. 2, reducing the register bit width of the first n-stage integrating unit in the integrator, and removing the unused registers of the high order, thereby reducing the number of registers in the whole Sinc filter and reducing the register consumption.
It should be noted that, in one implementation, in the optimization of the Sinc filter, only the first n-stage integrating unit is optimized, the latter-stage integrating unit and the comb are not optimized, and when the integrating unit is optimized, the bit width of the register in the first n-stage integrating unit is set to satisfy the minimum bit width in the period reset scenario.
As a possible implementation manner, in the present application, the number of stages that need to be optimized may be determined by means of comparison. Specifically, the number of optimized registers can be compared with the number of Hogenaure structures, and the smaller value of the number of the optimized registers is taken as the data bit width of the first register in each stage of integration unit.
Wherein, the standard value of Hogenaure structure satisfies the formula:
Wj＝B max -B j
wherein Bmax represents the intermediate quantity, N represents the number of stages of the Sinc filter, R represents the downsampling rate, bin represents the input quantity, bj represents the number of bit widths of the j-th low-order truncations, fj represents the sum of error variances of the previous j-th order, and σT 2N+1 Representing the variance of the error source of the last stage, wj representing the standard value of the data bit width of the first register in the j-th stage integration unit in the Hogenaure structure; sign symbolRepresenting the rounding up, the sign->Representing a rounding down.
From this formula, it can be determined that in the Hogenaure structure, the data bit width of the first register in the first stage integration unit is 57, the data bit width of the first register in the second stage integration unit is 56, the data bit width of the first register in the third stage integration unit is 43, and the data bit width of the first register in the fourth stage integration unit is 30 (the structure shown in fig. 2).
As one implementation, in the first n-stage integrating unit, the data bit width of the first register satisfies the formula:
Yn＝Q*Log 2 (R*N)
wherein Yn represents the data bit width of the first register in the nth stage integration unit, Q represents the number of stages of the integration unit, R represents the downsampling rate, and N represents the number of stages of the Sinc filter.
For the four-stage filter, the R value is 16348, and it can be determined from the formula that the data bit width of the first register in the first-stage integrating unit is 16, the data bit width of the first register in the second-stage integrating unit is 32, the data bit width of the first register in the third-stage integrating unit is 48, and the data bit width of the first register in the fourth-stage integrating unit is 64.
The data bit width determined in this way is compared with the standard value of the Hogenaure structure and a smaller value is selected. Referring to fig. 3, for a 4-order Sinc filter, it can be understood that the registers in the first integration unit and the second integration unit are optimized, where the data bit width of the first register in the first integration unit is 16 bits, the data bit width of the first register in the second integration unit is 32 bits, and the data bit widths of the first registers in the third integration unit and the fourth integration unit are still the same as those in the prior art, that is, 43 bits and 30 bits, respectively, so as to implement optimization of the filter.
On this basis, the optimized register consumption is 16+32+43+30+24+23+22+21, namely 211, and compared with the circuit structure shown in fig. 2, the optimized register is 51, so that the register consumption is reduced, and meanwhile, the size of the Sinc filter is also reduced.
It should be noted that the number of the optimized integration units may be different for the filters with different orders, and the above-mentioned 4-order filter optimizes only the register data bit width of the previous two-stage integration unit, but also optimizes the register data bit width of the previous three-stage integration unit for the 5-order filter or the 6-order filter. In the present application, the value of n may vary according to the actual situation. When the register data bit width determined by the formula yn=q×log2 (r×n) is smaller than the standard value of the Hogenaure structure in the first two-stage integration unit, and when the register data bit width in the third-stage integration unit is larger than the standard value of the corresponding stage number of the Hogenaure structure, n=2, and only the data bit width of the register in the first two-stage integration unit is optimized; and if the data bit width of the register in the first three-stage integration unit is smaller than the standard value of the corresponding stage number of the Hogenaure structure, and if the data bit width of the register in the fourth-stage integration unit is larger than the standard value of the Hogenaure structure, n=3, optimizing the data bit width of the register in the third-stage integration unit, and the like.
Of course, in another implementation manner, besides optimizing the first n stages of integration units, other optimization manners may be combined, for example, for the time sequence problem possibly caused by the overlong combinational logic, the time sequence problem may be eliminated by adding flowing water into the circuits of the integration units of each stage, and the cascade of the combinational logic is cut off to optimize the time sequence.
Specifically, referring to fig. 4, a first register of a previous stage integration unit is connected to an adder of a next stage integration unit, the adder of the first stage integration unit is configured to receive an input signal, and a first register of the last stage integration unit is connected to the decimator.
In the circuit structure shown in fig. 3, the adders are cascaded, and the registers are only in delay branches, so that during data processing, the adders need to perform data processing in the same period, and when the order of the Sinc filter is large, a timing problem may occur. By introducing a pipelining mode, the delay branch is introduced between every two adders, so that data processing can be performed in different periods for each integration unit, cascading between adjacent integration units is cut off, time sequence is optimized, and the time sequence problem caused by overlong combinational logic is avoided.
And the stability of the whole Sinc filter can be ensured by introducing a pipelining connection after optimizing the register of the previous n-stage integration unit.
Furthermore, as for the comb of the Sinc filter, a comb of the prior art can be used, which can also be optimized.
In one implementation, when a prior art comb is used, the comb includes a plurality of differential units, the number of differential units is equal to the number of integral units, each differential unit includes a subtractor and a second register connected to each other, the second register is located on the delay branch, and the data bit widths of the second registers of the plurality of differential units gradually decrease. As in fig. 4, the number of differential units includes four, whose register bit widths are 24 bits, 23 bits, 22 bits, and 21 bits, respectively.
In another implementation, the comb may be optimized, as an implementation, referring to fig. 5, where the comb includes a third register, a full-add module, and a fourth register, and the decimator, the third register, the full-add module, and the fourth register are sequentially connected, and the third register, the full-add module, and the fourth register further receive different control signals, respectively, and perform addition or subtraction logic under control of the control signals.
The full adder module comprises an inverter, a selector and a full adder, wherein a first tap of a third register is connected with a first port of the selector, a second tap of the third register is connected with a second port of the selector through the inverter, and the selector, the full adder and a fourth register are sequentially connected. The third register is the same as the fourth register in data bit width.
In the circuit structure shown in fig. 5, the control signals include 4 control signals, which are load, sub, store and clear signals, respectively, wherein the load signal is used for controlling the third register, the sub signal is used for controlling the selector, and the store and clear signals are used for controlling the fourth register. It will be appreciated that by setting the circuit configuration, the selector can select the data of the third register or select its complement data via the inverter to perform the addition logic with the adder, and when the complement of the data of the third register is selected, the subtraction logic is essentially performed.
Compared with the circuit structure shown in fig. 4, the optimized comb uses the equivalent substitution of the circuit structure of the full adder and the two-stage register, and combines the control of the control signal load, sub, store and the clear signal to reduce the register from the previous 4 stages to 2 stages and the adder from the previous 4 stages to 1 stage, so that the circuit structure reduces the use of the register and the adder, reduces the consumption of resources and occupies a smaller area.
Furthermore, as can be seen, the circuit structure is also optimized in order, with 2 stages of pipeline being introduced in the comb, so that the combinational logic is no longer cascaded, which introduces a total of 6 stages of pipeline for the entire Sinc filter. Referring to fig. 6, fig. 6 shows a timing chart of control signals, and by matching the control signals, the calculation task of the comb formed by the previous 4-stage adder can be completed, and the precision is higher than that of the Hogenauer structure.
In conclusion, the number of registers in the first n-stage integration units is reduced based on the use scene of periodic reset; meanwhile, on the premise of not increasing hardware resources, the integrator chops the combinational logic cascade, solves the time sequence problem possibly caused by overlarge combinational logic time delay, and optimizes the circuit time sequence; in addition, the comb device is structurally optimized, so that the number of registers is reduced, the number of adders is reduced, and meanwhile, the sequential optimization is realized by inserting flow.
Through the verification of the applicant, compared with the traditional Hogenauer structure filter, the Sinc filter provided by the application has the advantages that the register resource is optimized to 37.1% by 100%, 3 adders are saved by the combinational logic, and the circuit area is greatly reduced; meanwhile, 6-level pipelining is inserted into the whole calculated data chain, so that the time sequence is greatly improved.
Based on the implementation manner, the application also provides electronic equipment, which comprises the Sinc filter.
It should be noted that the application is not limited to a specific application field of the Sinc filter, for example, the application may be applied to a communication field, and the electronic device may be a wireless transceiver.
In summary, the present application provides a Sinc filter and an electronic device, where the Sinc filter is applied to a period resetting system, the Sinc filter includes an integrator, a decimator, and a comb, and the integrator, the decimator, and the comb are sequentially connected; the integrator comprises a plurality of cascaded integrating units, each integrating unit comprises an adder and a first register which are connected with each other, and the first register is positioned on the delay branch; in the first n-stage integration unit, the data bit width of the first register is smaller than a standard value, and the standard value is determined according to the bit width of an output signal of the Sinc filter, wherein n is more than or equal to 1. In the Sinc filter provided by the application, the register bit width of the n-level integration unit is optimized under the application scene of periodic reset, and the unused registers of high-order bits are removed, so that the consumption resource and area of the whole Sinc filter are reduced.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A Sinc filter, characterized in that it is applied to a periodic reset system, the Sinc filter comprising an integrator, a decimator and a comb, the integrator, decimator and comb being connected in sequence;
the integrator comprises a plurality of cascaded integrating units, wherein each integrating unit comprises an adder and a first register which are connected with each other, and the first register is positioned on a delay branch; wherein,
in the first n-stage integration unit, the data bit width of the first register is smaller than the standard value of the Hogenaure structure, and the standard value is determined according to the bit width of the output signal of the Sinc filter, wherein n is more than or equal to 1.
2. The Sinc filter of claim 1 wherein in the first n-stage integrator unit, the data bit width of the first register satisfies the formula:
Yn＝Q*Log 2 (R*N)
wherein Yn represents the data bit width of the first register in the nth stage integration unit, Q represents the number of stages of the integration unit, R represents the downsampling rate, and N represents the number of stages of the Sinc filter.
3. The Sinc filter of claim 1 wherein the standard value of the Hogenaure structure satisfies the formula:
Wj＝B max -B j
wherein Bmax represents an intermediate quantity, N represents the number of stages of the Sinc filter, R represents the downsampling rate, B in Represents the input quantity, bj represents the number of bit widths of the j-th level low-order truncations, fj represents the sum of error variances of the previous j-level, σT 2N+1 Representing the variance of the error source of the last stage, wj represents the standard value of the data bit width of the first register of the j-th stage integration unit in the Hogenaure structure; sign symbolRepresenting the rounding up, the sign->Representing a rounding down.
4. The Sinc filter of claim 1 wherein when the integrator comprises four integrator units, the first register in the first integrator unit has a data bit width of 16 bits and the second integrator unit has a data bit width of 32 bits.
5. The Sinc filter of claim 1 wherein a plurality of the integration units are connected in a pipelined fashion.
6. The Sinc filter of claim 5 wherein in the integrator, a first register of a preceding stage integrator unit is connected to an adder of a following stage integrator unit, the adder of the first stage integrator unit is configured to receive an input signal, and a first register of a final stage integrator unit is connected to the decimator.
7. The Sinc filter of claim 1 wherein the comb comprises a plurality of differential units equal in number to the number of integral units, each of the differential units including a subtractor and a second register interconnected, the second register being located on a delay branch, the second registers of the plurality of differential units having progressively lower data bit widths.
8. The Sinc filter of claim 1 wherein the comb comprises a third register, a full-add module, and a fourth register, the decimator, the third register, the full-add module, and the fourth register being connected in sequence, the third register, the full-add module, and the fourth register also each receiving a different control signal and performing addition or subtraction logic under control of the control signals.
9. The Sinc filter of claim 8, wherein the full-adder module comprises an inverter, a selector, and a full adder, a first tap of the third register being connected to a first port of the selector, a second tap of the third register being connected to a second port of the selector through the inverter, the selector, the full adder, and the fourth register being connected in sequence.
10. An electronic device, characterized in that it comprises a Sinc filter according to any of claims 1 to 9.
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| CN118013592A (en) * | 2024-04-10 | 2024-05-10 | 成都时域半导体有限公司 | Message digest generation circuit and method |
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| CN118013592A (en) * | 2024-04-10 | 2024-05-10 | 成都时域半导体有限公司 | Message digest generation circuit and method |
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