CN117767941A - Phase-locked loop circuit and chip based on low-dropout linear voltage regulator circuit - Google Patents
Phase-locked loop circuit and chip based on low-dropout linear voltage regulator circuit Download PDFInfo
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- CN117767941A CN117767941A CN202311732915.7A CN202311732915A CN117767941A CN 117767941 A CN117767941 A CN 117767941A CN 202311732915 A CN202311732915 A CN 202311732915A CN 117767941 A CN117767941 A CN 117767941A
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Abstract
The embodiment of the application relates to a phase-locked loop circuit based on a low dropout linear voltage regulator circuit. The phase-locked loop circuit includes: the device comprises a frequency output module, a charge module, a filtering module with a preset operational amplifier and a low dropout linear voltage regulator circuit; the low dropout linear regulator circuit includes: the first voltage output module and the second voltage output module are connected with each other; a first voltage output module configured to: providing a driving voltage to the frequency output module and the charge module; a second voltage output module configured to: a reference voltage is provided to a preset operational amplifier. The phase-locked loop circuit outputs the driving voltage through the first voltage output module and outputs the reference voltage through the second voltage output module, so that the driving voltage and the reference voltage with lower noise are provided for the phase-locked loop circuit, and further phase noise generated by the phase-locked loop circuit due to the fact that additional reference voltage is introduced is avoided.
Description
Technical Field
The invention relates to the technical field of feedback control circuits, in particular to a phase-locked loop circuit and a chip based on a low dropout linear voltage regulator circuit.
Background
A phase locked loop (Phase Locked Loop, PLL) circuit is a negative feedback control circuit that uses a voltage generated by phase synchronization to detune a voltage controlled oscillator to generate a target frequency. PLL circuits are widely used in integrated circuits for the processing of clock signals. In many cases, the output clock signal of the PLL needs to have a precise frequency.
In general, a PLL circuit includes: a phase frequency detector (Phase Frequency Detector, PFD), a Charge Pump (CP), a Loop Filter (LPF), and a Voltage controlled oscillator (Voltage-Controlled Oscillator, VCO).
Currently, in order to simplify the structure of a PLL circuit, a low dropout linear regulator circuit is generally used to supply a supply voltage and a drive current to the PLL circuit.
On the basis of the low dropout linear regulator circuit, the active LPF requires an additional reference voltage than the passive LPF, but if the noise of the reference voltage is high, the noise of the reference voltage is introduced into the PLL circuit, thereby causing the PLL circuit to generate phase noise.
Disclosure of Invention
The phase-locked loop circuit and the chip based on the low dropout linear voltage regulator circuit can overcome at least part of defects in the prior art.
In a first aspect, embodiments of the present application provide a phase locked loop circuit based on a low dropout linear regulator circuit. The phase-locked loop circuit includes: the device comprises a frequency output module, a charge module, a filtering module with a preset operational amplifier and a low dropout linear voltage regulator circuit; the low dropout linear regulator circuit includes: the first voltage output module and the second voltage output module are connected with each other; the first voltage output module is respectively connected with the frequency output module and the charge module, and is configured to: providing a driving voltage to the frequency output module and the charge module; the second voltage output module is connected with a preset operational amplifier in the filtering module, and is configured to: providing a reference voltage to the preset operational amplifier.
Optionally, the first voltage output module includes: the constant voltage power supply, the first P-type MOS tube, the second P-type MOS tube, the first N-type MOS tube, the second N-type MOS tube and the third N-type MOS tube; the source electrode of the first P-type MOS tube, the source electrode of the second P-type MOS tube and the drain electrode of the first N-type MOS tube are all connected with the constant voltage power supply; the grid electrode of the first P type MOS tube is connected with the grid electrode of the second P type MOS tube, and the drain electrode of the first P type MOS tube is respectively connected with the grid electrode of the first P type MOS tube and the drain electrode of the second N type MOS tube; the drain electrode of the second P-type MOS tube is respectively connected with the grid electrode of the first N-type MOS tube and the drain electrode of the third N-type MOS tube; the source electrode of the first N-type MOS tube is respectively connected with the grid electrode of the second N-type MOS tube and the grid electrode of the third N-type MOS tube and forms a first voltage output end, and the first voltage output end is used for outputting the driving voltage; and the source electrode of the second N-type MOS tube and the source electrode of the third N-type MOS tube are respectively connected with the second voltage output module.
Optionally, the second voltage output module includes: the first resistor, the fourth N-type MOS tube and the fifth N-type MOS tube; the drain electrode and the grid electrode of the fourth N-type MOS tube are connected with the source electrode of the second N-type MOS tube, the source electrode of the fourth N-type MOS tube is connected with the first end of the first resistor, and the second end of the first resistor is connected to the ground; the drain electrode and the grid electrode of the fifth N-type MOS tube are connected with the source electrode of the third N-type MOS tube, the grid electrode of the fifth N-type MOS tube forms a second voltage output end, and the second voltage output end is used for outputting the reference voltage; and the source electrode of the fifth N-type MOS tube is connected to the ground.
Optionally, the fourth N-type MOS transistor has: a first transistor width and a first channel length; the fifth N-type MOS transistor comprises: a second transistor width and a second channel length; the ratio between the first transistor width and the first channel length is a first ratio; the ratio between the second transistor width and the second channel length is a second ratio; the first ratio is a positive integer multiple of the second ratio.
Optionally, the preset operational amplifier has: the device comprises an inverting input end, a non-inverting input end, a signal output end, a power supply input end and a grounding end; the non-inverting input end is connected with the second voltage output end and is used for receiving the reference voltage; the power input end is connected with the constant voltage power supply and is used for receiving electric energy provided by the constant voltage power supply; the inverting input end is connected with the charge module and is used for receiving the current output by the charge module; the signal output end is connected with the frequency output module and is used for outputting the voltage signal output by the preset operational amplifier to the frequency output module; the ground terminal is connected to ground.
Optionally, the filtering module further includes: the second resistor, the third resistor, the first capacitor, the second capacitor and the third capacitor; the first end of the second resistor is connected with the charge module, and the second end of the second resistor is connected with the inverting input end; a first end of the first capacitor is connected with a first end of the second resistor, and a second end of the first capacitor is connected to ground; the first end of the third resistor is connected with the inverting input end, the second end of the third resistor is connected with the first end of the second capacitor, and the second end of the second capacitor is connected with the signal output end; the first end of the third capacitor is connected with the first end of the third resistor and the inverting input end respectively, and the second end of the third capacitor is connected with the second end of the second capacitor and the signal output end respectively.
Optionally, the frequency output module includes: a voltage controlled oscillator, a fourth resistor and a fifth resistor; the first end of the fourth resistor is connected with the first voltage output end, and the second end of the fourth resistor is respectively connected with the voltage-controlled oscillator and the first end of the fifth resistor; and the second end of the fifth resistor is connected with the filtering module.
Optionally, when the filtering module does not output a voltage signal to the frequency output module, the fundamental frequency signal output by the frequency output module is determined according to the voltage division of the voltage through the voltage-controlled oscillator by the fourth resistor and the fifth resistor.
Optionally, the fifth resistor is a resistor with an adjustable resistance value, and when the filtering module outputs the voltage signal to the frequency output module, the voltage signal output by the filtering module is dynamically divided by the fifth resistor, and the voltage passing through the voltage-controlled oscillator is dynamically adjusted, so that the frequency signal output by the frequency output module is dynamically adjusted.
In a second aspect, embodiments of the present application provide a chip comprising a phase-locked loop circuit as described above.
At least one advantageous aspect of the phase-locked loop circuit based on the low dropout linear regulator circuit provided by the embodiments of the present application is: the driving voltage is output through the first voltage output module, and the reference voltage is output through the second voltage output module, so that the driving voltage and the reference voltage with lower noise are provided for the phase-locked loop circuit, and further phase noise generated by the phase-locked loop circuit due to the fact that additional reference voltage is introduced is avoided.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a functional block diagram of a chip provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of a low dropout linear regulator circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a phase-locked loop circuit based on a low dropout linear regulator circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an embodiment in which the rising edge of the reference signal is ahead of the rising edge of the frequency signal output by the frequency output module according to the embodiment of the present application;
fig. 5 is a schematic diagram of an embodiment in which a rising edge of a frequency signal output by the frequency output module provided in the embodiment of the present application leads a rising edge of a reference signal.
Detailed Description
In order that the invention may be readily understood, a more particular description thereof will be rendered by reference to specific embodiments that are illustrated in the appended drawings. It will be understood that when an element is referred to as being "fixed" to another element, it can be directly on the other element or one or more intervening elements may be present therebetween. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or one or more intervening elements may be present therebetween. The terms "upper," "lower," "inner," "outer," "bottom," and the like as used in this specification are used in an orientation or positional relationship based on that shown in the drawings, merely to facilitate the description of the invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items.
In addition, the technical features mentioned in the different embodiments of the invention described below can be combined with one another as long as they do not conflict with one another.
Fig. 1 is a functional block diagram of a chip provided in an embodiment of the present application. As shown in fig. 1, the chip includes a phase-locked loop circuit based on a low dropout linear regulator circuit, which may include: the charge module 10, the filter module 20, the frequency output module 30, and the low dropout linear regulator circuit 40 may further include: a frequency division module 50 and a phase discrimination module 60.
The charge module 10 is connected to the phase detection module 60, and the charge module 10 is configured to output a corresponding current according to the phase difference signal output by the phase detection module 60, which should be noted that the charge module 10 may output different currents according to different phase difference signals. Thus, the charge module 10 is configured to: the corresponding current is output according to the phase difference signal output by the phase detection module 60.
The filtering module 20 is connected to the charge module 10, and the filtering module 20 is configured to receive the current output by the charge module 10, convert the current output by the charge module 10 into a voltage signal, and output the voltage signal to the frequency output module 30. Wherein the filtering module 20 has: the operational amplifier 210 is preset. The preset operational amplifier 210 is connected to the charge module 10.
The frequency output module 30 is connected to the filtering module 20, the frequency dividing module 50 and the next stage circuit 70, wherein the frequency output module 30 is connected to the preset operational amplifier 210. The frequency output module 30 is configured to receive the voltage signal output by the filtering module 20, output a corresponding frequency signal according to the received voltage signal, and transmit the output frequency signal to the next stage circuit 70 and the frequency dividing module 50, and it should be noted that the frequency output module 30 can output corresponding different frequency signals according to different voltage signals, so as to realize output of multiple frequency signals.
The frequency dividing module 50 is configured to convert the frequency signal output by the frequency output module 30 into a frequency signal having the same frequency as a reference signal with a preset frequency, where the reference signal with the preset frequency may be a reference signal with a preset frequency output by a preset clock oscillator, and the preset frequency may be 200 megahertz (MHz), or 300 megahertz (MHz), by way of example and not limitation, and the specific preset frequency may be set according to an actual application scenario.
The phase detection module 60 is connected to the frequency division module 50, and the frequency division module 50 converts the frequency signal output by the frequency output module 30 into a frequency signal having the same frequency as the reference signal with the preset frequency, so that the phase detection module 60 only needs to compare whether the frequency signal output by the frequency output module 30 has a phase difference with the reference signal.
The low dropout linear regulator circuit 40 includes: a first voltage output module 410 and a second voltage output module 420 are connected to each other.
The first voltage output module 410 is connected to the frequency output module 30 and the charge module 10, and the first voltage output module 410 is configured to: the driving voltage is supplied to the frequency output module 30 and the charge module 10.
The second voltage output module 420 is connected to the preset operational amplifier 210 in the filtering module 20, and the second voltage output module 420 is configured to: the reference voltage is supplied to the preset operational amplifier 210.
At least one advantageous aspect of the phase-locked loop circuit based on the low dropout linear regulator circuit provided by the embodiments of the present application is: the driving voltage is output through the first voltage output module, and the reference voltage is output through the second voltage output module, so that the driving voltage and the reference voltage with lower noise are provided for the phase-locked loop circuit, and further phase noise generated by the phase-locked loop circuit due to the fact that additional reference voltage is introduced is avoided.
Fig. 2 is a schematic diagram of a low dropout linear regulator circuit according to an embodiment of the present disclosure.
In some embodiments, as shown in fig. 2, the first voltage output module 410 includes: constant voltage power supply AVDD, first P type MOS pipe MP1, second P type MOS pipe MP2, first N type MOS pipe MN1, second N type MOS pipe MN2 and third N type MOS pipe MN3.
The source electrode of the first P-type MOS tube MP1, the source electrode of the second P-type MOS tube MP2 and the drain electrode of the first N-type MOS tube MN1 are all connected with the constant voltage power supply AVDD.
The grid electrode of the first P type MOS tube MP1 is connected with the grid electrode of the second P type MOS tube MP2, and the drain electrode of the first P type MOS tube MP1 is respectively connected with the grid electrode of the first P type MOS tube MP1 and the drain electrode of the second N type MOS tube MN 2.
The drain electrode of the second P-type MOS tube MP2 is respectively connected with the grid electrode of the first N-type MOS tube MN1 and the drain electrode of the third N-type MOS tube MN3.
The source electrode of the first N-type MOS transistor MN1 is connected to the gate electrode of the second N-type MOS transistor MN2 and the gate electrode of the third N-type MOS transistor MN3, respectively, to form a first voltage output terminal vddpl, where the first voltage output terminal vddpl is configured to output a driving voltage.
The source of the second N-type MOS transistor MN2 and the source of the third N-type MOS transistor MN3 are respectively connected to the second voltage output module 420.
It should be noted that, the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are used as current mirror loads, the input ends of the current mirror loads (the source electrode of the first P-type MOS transistor MP1 and the source electrode of the second P-type MOS transistor MP 2) are connected to a voltage source (constant voltage power AVDD), and the output ends (the drain electrode of the first P-type MOS transistor MP1 and the drain electrode of the second P-type MOS transistor MP 2) are connected to load parts (MN 1, MN2 and MN 3). When the resistance of the load portion changes, the current mirror load will adjust the output current to keep the current constant.
In some embodiments, as shown in fig. 2, the second voltage output module 420 includes: the first resistor R1, the fourth N-type MOS transistor MN4 and the fifth N-type MOS transistor MN5.
The drain electrode and the gate electrode of the fourth N-type MOS transistor MN4 are both connected to the source electrode of the second N-type MOS transistor MN2, the source electrode of the fourth N-type MOS transistor MN4 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the ground GND.
The drain electrode and the gate electrode of the fifth N-type MOS tube MN5 are connected with the source electrode of the third N-type MOS tube MN3, and the gate electrode of the fifth N-type MOS tube MN5 forms a second voltage output end VREF which is used for outputting a reference voltage. The source of the fifth N-type MOS transistor MN5 is connected to the ground.
In some embodiments, as shown in fig. 2, the fourth N-type MOS transistor MN4 has: a first transistor width W1 and a first channel length L1; the fifth N-type MOS transistor MN5 has: a second transistor width W2 and a second channel length L2; the ratio between the first transistor width W1 and the first channel length L1 is a first ratio W1/L1; the ratio between the second transistor width W2 and the second channel length L2 is a second ratio W2/L2; the first ratio W1/L1 is a positive integer multiple of the second ratio W2/L2.
In some embodiments, the reference voltage is half the drive voltage.
It should be noted that, the second N-type MOS transistor MN2 and the third N-type MOS transistor MN3 are equivalent to input pair transistors, and when the low dropout linear voltage regulator circuit works normally, the voltage of the source electrode in the second N-type MOS transistor MN2 is equal to the voltage of the second voltage output terminal VREF, so that the voltages applied to the two ends of the resistor R1 are: vr1 = Vgs5-Vgs4, the current through resistor R1 is: ir1=Vr1/R1, wherein Vr1 is used for indicating the voltage at two ends of the resistor R1, vgs5 is used for indicating the voltage difference between the gate and the source in the fifth N-type MOS tube MN5, vgs4 is used for indicating the voltage difference between the gate and the source in the fourth N-type MOS tube MN4, ir1 is used for indicating the current passing through the resistor R1, and Rr1 is used for indicating the resistance value of the resistor R1. Because the current mirrors of the first P-type MOS tube MP1 and the second P-type MOS tube MP2 act, the current value of the circuit on the side where the fifth N-type MOS tube MN5 is positioned is Ir1.
In summary, the driving voltage output by the first voltage output terminal vddpl is: vgs2+vgs5, wherein Vgs2 is used to indicate the voltage difference between the gate and the source in the second N-type MOS transistor MN 2.
The voltage at the second voltage output terminal VREF is: vgs5, it should be noted that by adjusting the second ratio W2/L2 between the second transistor width W2 and the second channel length L2 in the fifth N-type MOS transistor MN5, a reference voltage with low noise can be obtained.
It should be noted that, the first N-type MOS transistor MN1 is a large-sized driving transistor with driving capability, and not only can be used as a bias point of the respective gates of the second N-type MOS transistor MN2 and the third N-type MOS transistor MN3, but also can provide a driving voltage (Vgs 2+vgs 5).
At least one advantageous aspect of the phase-locked loop circuit based on the low dropout linear regulator circuit provided by the embodiments of the present application is: the driving voltage is output through the first voltage output module, and the reference voltage is output through the second voltage output module, so that the driving voltage and the reference voltage with lower noise are provided for the phase-locked loop circuit, and further phase noise generated by the phase-locked loop circuit due to the fact that additional reference voltage is introduced is avoided.
Fig. 3 is a schematic diagram of a phase-locked loop circuit based on a low dropout linear regulator circuit according to an embodiment of the present application.
In some embodiments, as shown in fig. 3, the preset operational amplifier 210 has: an inverting input 211, a non-inverting input 212, a signal output 213, a power input 214, and a ground 215.
The non-inverting input terminal 212 is connected to the second voltage output terminal VREF, and the non-inverting input terminal 212 is configured to receive a reference voltage.
The power input terminal 214 is connected to the constant voltage power AVDD, and the power input terminal 214 is configured to receive the electric energy provided by the constant voltage power AVDD.
The inverting input terminal 211 is connected to the charge module 10, and the inverting input terminal 211 is used for receiving the current output by the charge module 10.
The signal output end 213 is connected to the frequency output module 30, and the signal output end 213 is configured to output a voltage signal output by the preset operational amplifier 210 to the frequency output module 30; the ground terminal 215 is connected to ground GND.
In some embodiments, as shown in fig. 3, the filtering module 20 further includes: the second resistor R2, the third resistor R3, the first capacitor C1, the second capacitor C2 and the third capacitor C3.
The first end of the second resistor R2 is connected to the charge module 10, and the second end of the second resistor R2 is connected to the inverting input 211.
The first end of the first capacitor C1 is connected to the first end of the second resistor R2, and the second end of the first capacitor C1 is connected to the ground GND.
The first end of the third resistor R3 is connected to the inverting input terminal 211, the second end of the third resistor R3 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the signal output terminal 213.
The first end of the third capacitor C3 is connected to the first end of the third resistor R3 and the inverting input terminal 211, and the second end of the third capacitor C3 is connected to the second end of the second capacitor C2 and the signal output terminal 213.
In some embodiments, as shown in fig. 3, the frequency output module 30 includes: a Voltage Controlled Oscillator (VCO), a fourth resistor R4 and a fifth resistor R5.
The first end of the fourth resistor R4 is connected to the first voltage output end vddpl, and the second end of the fourth resistor R4 is connected to the first ends of the voltage-controlled oscillator (VCO) and the fifth resistor R5, respectively; the second terminal of the fifth resistor R5 is connected to the filter module 20.
In some embodiments, as shown in fig. 3, a second terminal of the fifth resistor R5 is connected to the signal output terminal 213.
In some embodiments, as shown in fig. 3, a Voltage Controlled Oscillator (VCO) is connected to the frequency dividing module 50 and the next stage circuit 70, respectively.
It should be noted that, the Voltage-controlled oscillator (VCO) can output signals corresponding to different frequencies according to different Voltage signals, so as to realize output of multiple frequency signals.
In some embodiments, when the filtering module 20 does not output the voltage signal to the frequency output module 30, the fundamental frequency signal output by the frequency output module 30 is determined according to the voltage division of the voltage through the Voltage Controlled Oscillator (VCO) by the fourth resistor R4 and the fifth resistor R5. It can be understood that: when the filtering module 20 does not output the voltage signal to the frequency output module 30, only the first voltage output terminal vddpl provides a voltage to the frequency output module 30, and the voltage is divided by the fourth resistor R4 and the fifth resistor R5, so that the voltage-controlled oscillator (VCO) obtains the divided voltage Vddosc, and the voltage Vddosc is input to the voltage-controlled oscillator (VCO), so as to obtain the corresponding fundamental frequency signal.
In some embodiments, the fifth resistor R5 is a resistor with an adjustable resistance value, and when the filtering module 20 outputs the voltage signal to the frequency output module 30, the voltage signal output by the filtering module 20 is dynamically divided by the fifth resistor R5, and the voltage through the Voltage Controlled Oscillator (VCO) is dynamically adjusted, so that the frequency signal output by the frequency output module 30 is dynamically adjusted. It can be understood that: when the filtering module 20 outputs the voltage signal to the frequency output module 30, the resistance value of the fifth resistor R5 is dynamically adjusted, so that the voltage signal output by the filtering module 20 is dynamically adjusted, so as to output different voltage signals, and the voltage-controlled oscillator (VCO) outputs a corresponding frequency signal according to the different voltage signals, so as to dynamically adjust the frequency signal output by the frequency output module 30.
In some embodiments, as shown in fig. 3, the charge module 10 is a charge pump 10, and the charge pump 10 may include: a first current source 110, a second current source 120, a first switch 130, and a second switch 140.
Wherein the first switch 130 and the second switch 140 are connected to each other and formed with a connection node J.
The current input terminal of the first current source 110 is connected to the first voltage output terminal vddpl, and the current output terminal of the first current source 110 is connected to the first switch 130.
The current input terminal of the second current source 120 is connected to the second switch 140, and the current output terminal of the second current source 120 is connected to the ground GND.
In some embodiments, as shown in fig. 3, the connection node J is connected to a first capacitor C1 in the filter module 20.
It should be noted that, since the frequency of the frequency signal output by the frequency output module 30 is the same as the frequency of the reference signal, the frequency output module outputs:
(1) When the rising edge of the reference signal leads the rising edge of the frequency signal output by the frequency output module 30, as shown in fig. 4, fig. 4 is a schematic diagram showing an embodiment in which the rising edge of the reference signal leads the rising edge of the frequency signal output by the frequency output module, the charge module 10 receives the first phase difference signal output by the phase detection module 60, so that the first switch 130 is closed, and the second switch 140 is kept open, so that the voltage output by the first voltage output terminal vdpll charges the first capacitor C1 through the first current source 110.
(2) When the rising edge of the frequency signal output by the frequency output module 30 leads the rising edge of the reference signal, as shown in fig. 5, fig. 5 is a schematic diagram showing an embodiment in which the rising edge of the frequency signal output by the frequency output module provided by the embodiment of the present application leads the rising edge of the reference signal, the charge module 10 receives the second phase difference signal output by the phase detection module 60, so that the second switch 140 is closed, and the first switch 130 is kept open, so that the first capacitor C1 discharges through the second current source 120.
In some embodiments, as shown in fig. 3, the phase detection module 60 may be a phase frequency detector (Phase Frequency Detector, PFD) that is capable of comparing the frequency signal output by the frequency output module 30 to a reference signal in frequency and phase.
At least one advantageous aspect of the phase-locked loop circuit based on the low dropout linear regulator circuit provided by the embodiments of the present application is: the driving voltage is output through the first voltage output module, and the reference voltage is output through the second voltage output module, so that the driving voltage and the reference voltage with lower noise are provided for the phase-locked loop circuit, and further phase noise generated by the phase-locked loop circuit due to the fact that additional reference voltage is introduced is avoided.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the invention, the steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A phase locked loop circuit based on a low dropout linear voltage regulator circuit, the phase locked loop circuit comprising: the device comprises a frequency output module, a charge module, a filtering module with a preset operational amplifier and a low dropout linear voltage regulator circuit;
the low dropout linear regulator circuit includes: the first voltage output module and the second voltage output module are connected with each other;
the first voltage output module is respectively connected with the frequency output module and the charge module, and is configured to: providing a driving voltage to the frequency output module and the charge module;
the second voltage output module is connected with a preset operational amplifier in the filtering module, and is configured to: providing a reference voltage to the preset operational amplifier.
2. The phase-locked loop circuit of claim 1, wherein the first voltage output module comprises: the constant voltage power supply, the first P-type MOS tube, the second P-type MOS tube, the first N-type MOS tube, the second N-type MOS tube and the third N-type MOS tube;
the source electrode of the first P-type MOS tube, the source electrode of the second P-type MOS tube and the drain electrode of the first N-type MOS tube are all connected with the constant voltage power supply;
the grid electrode of the first P type MOS tube is connected with the grid electrode of the second P type MOS tube, and the drain electrode of the first P type MOS tube is respectively connected with the grid electrode of the first P type MOS tube and the drain electrode of the second N type MOS tube;
the drain electrode of the second P-type MOS tube is respectively connected with the grid electrode of the first N-type MOS tube and the drain electrode of the third N-type MOS tube;
the source electrode of the first N-type MOS tube is respectively connected with the grid electrode of the second N-type MOS tube and the grid electrode of the third N-type MOS tube and forms a first voltage output end, and the first voltage output end is used for outputting the driving voltage;
and the source electrode of the second N-type MOS tube and the source electrode of the third N-type MOS tube are respectively connected with the second voltage output module.
3. The phase-locked loop circuit of claim 2, wherein the second voltage output module comprises: the first resistor, the fourth N-type MOS tube and the fifth N-type MOS tube;
the drain electrode and the grid electrode of the fourth N-type MOS tube are connected with the source electrode of the second N-type MOS tube, the source electrode of the fourth N-type MOS tube is connected with the first end of the first resistor, and the second end of the first resistor is connected to the ground;
the drain electrode and the grid electrode of the fifth N-type MOS tube are connected with the source electrode of the third N-type MOS tube, the grid electrode of the fifth N-type MOS tube forms a second voltage output end, and the second voltage output end is used for outputting the reference voltage;
and the source electrode of the fifth N-type MOS tube is connected to the ground.
4. The phase-locked loop circuit of claim 2, wherein the fourth N-type MOS transistor has: a first transistor width and a first channel length;
the fifth N-type MOS transistor comprises: a second transistor width and a second channel length;
the ratio between the first transistor width and the first channel length is a first ratio;
the ratio between the second transistor width and the second channel length is a second ratio;
the first ratio is a positive integer multiple of the second ratio.
5. A phase locked loop circuit as claimed in claim 3, wherein said preset operational amplifier has: the device comprises an inverting input end, a non-inverting input end, a signal output end, a power supply input end and a grounding end;
the non-inverting input end is connected with the second voltage output end and is used for receiving the reference voltage;
the power input end is connected with the constant voltage power supply and is used for receiving electric energy provided by the constant voltage power supply;
the inverting input end is connected with the charge module and is used for receiving the current output by the charge module;
the signal output end is connected with the frequency output module and is used for outputting the voltage signal output by the preset operational amplifier to the frequency output module;
the ground terminal is connected to ground.
6. The phase-locked loop circuit of claim 5, wherein the filtering module further comprises: the second resistor, the third resistor, the first capacitor, the second capacitor and the third capacitor;
the first end of the second resistor is connected with the charge module, and the second end of the second resistor is connected with the inverting input end;
a first end of the first capacitor is connected with a first end of the second resistor, and a second end of the first capacitor is connected to ground;
the first end of the third resistor is connected with the inverting input end, the second end of the third resistor is connected with the first end of the second capacitor, and the second end of the second capacitor is connected with the signal output end;
the first end of the third capacitor is connected with the first end of the third resistor and the inverting input end respectively, and the second end of the third capacitor is connected with the second end of the second capacitor and the signal output end respectively.
7. The phase-locked loop circuit of claim 2, wherein the frequency output module comprises: a voltage controlled oscillator, a fourth resistor and a fifth resistor;
the first end of the fourth resistor is connected with the first voltage output end, and the second end of the fourth resistor is respectively connected with the voltage-controlled oscillator and the first end of the fifth resistor;
and the second end of the fifth resistor is connected with the filtering module.
8. The phase-locked loop circuit of claim 7, wherein the fundamental frequency signal output by the frequency output module is determined from dividing the voltage across the voltage controlled oscillator by the fourth resistor and the fifth resistor when the filtering module is not outputting a voltage signal to the frequency output module.
9. The pll circuit of claim 7, wherein the fifth resistor is a resistor with an adjustable resistance, and when the filtering module outputs a voltage signal to the frequency output module, the voltage signal output by the filtering module is dynamically divided by the fifth resistor, and the voltage through the voltage-controlled oscillator is dynamically adjusted, so that the frequency signal output by the frequency output module is dynamically adjusted.
10. A chip comprising a phase locked loop circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311732915.7A CN117767941A (en) | 2023-12-15 | 2023-12-15 | Phase-locked loop circuit and chip based on low-dropout linear voltage regulator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311732915.7A CN117767941A (en) | 2023-12-15 | 2023-12-15 | Phase-locked loop circuit and chip based on low-dropout linear voltage regulator circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117767941A true CN117767941A (en) | 2024-03-26 |
Family
ID=90311789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311732915.7A Pending CN117767941A (en) | 2023-12-15 | 2023-12-15 | Phase-locked loop circuit and chip based on low-dropout linear voltage regulator circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117767941A (en) |
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2023
- 2023-12-15 CN CN202311732915.7A patent/CN117767941A/en active Pending
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