CN117767519A - Super capacitor circuit, charging and discharging method and power concentrator super capacitor system - Google Patents

Abstract

The application provides a super capacitor circuit, a charging and discharging method and a power concentrator super capacitor system, wherein the super capacitor circuit comprises: a plurality of supercapacitors and a plurality of switch sets; each super capacitor is correspondingly connected with a switch group; two adjacent super capacitors are connected through a switch group; the switch group is configured to control the series connection or parallel connection of a plurality of super capacitors by opening or closing each switch in the switch group; the super capacitor circuit discharges when a plurality of super capacitors are connected in series, and the super capacitor circuit charges when a plurality of super capacitors are connected in parallel. According to the method, the connection mode of the corresponding super capacitor is controlled by controlling the opening or closing of each switch in the switch group, so that the super capacitor is charged when connected in parallel and discharged when connected in series. When charging, mutually independent charging can reduce the voltage consistency requirement, and a voltage equalizing circuit is not required to be arranged. When discharging, each super capacitor can release lower voltage, and the capacity requirement on a single super capacitor can be reduced.

Description

Super capacitor circuit, charging and discharging method and power concentrator super capacitor system

Technical Field

The application relates to the field of energy storage power supplies, in particular to a super capacitor circuit, a charging and discharging method and a power concentrator super capacitor system.

Background

Supercapacitors are electrochemical devices capable of rapidly storing and supplying high power electricity, with higher energy density and lower voltage limits. In the practical application process, the super capacitor is possibly limited by the fact that the rated voltage of the self monomer is low, and the practical application requirement is difficult to meet.

It is common practice to form a super capacitor group by connecting a plurality of super capacitors in series to increase the voltage level of the super capacitor. However, in this way, the requirement for consistency of the super voltages in the super capacitor group is high, and a voltage equalizing circuit is generally arranged to ensure the consistency of the voltages of the super capacitors, so that the cost is high.

Disclosure of Invention

In view of the foregoing, an objective of the embodiments of the present application is to provide a supercapacitor circuit, a charging and discharging method, and a supercapacitor system of a power concentrator, which can reduce the cost of the supercapacitor circuit.

In a first aspect, an embodiment of the present application provides a supercapacitor circuit, including: a plurality of supercapacitors and a plurality of switch sets; each super capacitor is correspondingly connected with at least one switch group; two adjacent super capacitors are connected through the switch group; wherein the plurality of switch groups are configured to control the plurality of super capacitors to be connected in series or in parallel by opening or closing each switch in each of the plurality of switch groups; the super capacitor circuit discharges when the plurality of super capacitors are connected in series, and the super capacitor circuit charges when the plurality of super capacitors are connected in parallel.

In the implementation process, through setting up a plurality of switch groups, and each super capacitor is connected at least one switch group correspondingly, can control the connection mode that corresponding super capacitor inserts in the super capacitor circuit through opening or closing of each switch in the control switch group to make a plurality of super capacitors charge when parallelly connected, discharge when establishing ties. That is, when the super capacitors in the super capacitor circuit are charged, the super capacitors are charged independently, so that the voltage consistency requirement on each super capacitor can be reduced, a voltage equalizing circuit is not required, the super capacitor circuit structure is reduced, and the cost of the super capacitor circuit is reduced. In addition, when a plurality of super capacitors in the super capacitor circuit are discharged, each super capacitor can release lower voltage, the capacity requirement on a single super capacitor can be reduced, the cost of the single super capacitor is reduced, and the overall cost of the super capacitor circuit is further reduced.

In one embodiment, the switch set includes: a first switch, a second switch, and a third switch; the first end of the first switch and the first end of the second switch are connected with the positive electrode of the previous adjacent super capacitor; the first end of the third switch is connected with the first end of the third switch corresponding to the previous adjacent super capacitor and grounded; the second end of the first switch is connected with the positive electrode of the corresponding super capacitor; the second end of the second switch and the second end of the third switch are connected with the cathodes of the corresponding super capacitors; the first switch, the second switch and the third switch are configured to be opened and closed through the first switch, so as to switch the connection modes of the corresponding super capacitors.

In the implementation process, due to the fact that the switch is simple in structure and low in cost, through the fact that the first switch, the second switch and the third switch are arranged in each switch group, the corresponding super capacitor, other super capacitors and the connection mode of the super capacitor circuit can be switched through switching the opening and closing states of the first switch, the second switch and the third switch, and then the connection mode of the super capacitors in the super capacitor circuit is switched, complexity of the super capacitor circuit can be reduced, and meanwhile cost is reduced. In addition, the first switch, the second switch and the third switch are matched to cut off the abnormal super capacitor from the super capacitor circuit, so that the abnormal super capacitor is prevented from affecting other normal super capacitors, and the overall stability and safety of the circuit are improved.

In one embodiment, only the third switch is included in the switch group corresponding to the first supercapacitor; the first end of the third switch corresponding to the first super capacitor is connected with the first end of the third switch corresponding to the next adjacent super capacitor and grounded; the second end of the third switch corresponding to the first super capacitor is connected with the negative electrode of the first super capacitor; the third switch corresponding to the first super capacitor is configured to be opened and closed through the third switch so as to switch the connection mode of the first super capacitor.

In the implementation process, for the first super capacitor, only whether the super capacitor circuit is connected or not is considered, and the connection mode with other super capacitors is not needed, so that only the third switch is needed to control the connection of the first super capacitor to be connected or disconnected with the super capacitor, the switch setting of the first switch group corresponding to the first super capacitor is reduced, and the cost of the first switch group is further reduced.

In one embodiment, further comprising: a plurality of voltage sampling circuits; each voltage sampling circuit is arranged at two ends of each super capacitor in parallel; the voltage sampling circuit is configured to detect whether the corresponding super capacitor is abnormal or not.

In the implementation process, the corresponding voltage sampling circuit is arranged for each super capacitor so as to be used for collecting the voltage of each super capacitor, and further judging whether the corresponding super capacitor is abnormal or not so as to monitor whether each super capacitor is abnormal or not, thereby being beneficial to disconnecting the fault super capacitor in time and improving the overall stability and safety of the super capacitor circuit.

In one embodiment, the voltage sampling circuit includes: a first resistor, a second resistor and a capacitor; the first end of the first resistor is connected with the anode of the corresponding super capacitor; the first end of the second resistor is connected with the second end of the first resistor and the first end of the capacitor; the second end of the capacitor is connected with the negative electrode of the corresponding super capacitor and the second end of the capacitor and grounded; the first resistor and the second resistor are configured to divide the voltage on the corresponding super capacitor.

In the implementation process, the voltage on the corresponding super capacitor is divided by the first resistor and the second resistor, so that the voltage of the super capacitor can be divided into a voltage range which can be processed by the ADC sampling module, the ADC sampling module is prevented from being damaged due to overhigh voltage, and the safety and the stability of the voltage sampling circuit are improved.

In one embodiment, further comprising: a plurality of constant current voltage limiting circuits; the first end of each constant-current voltage limiting circuit is connected with an external power supply, and the second end of each constant-current voltage limiting circuit is connected with the anode of a corresponding super capacitor; the constant current voltage limiting circuit is configured to limit voltage and current entering the corresponding super capacitor.

In the implementation process, by arranging the constant-current voltage limiting circuits, each constant-current voltage limiting circuit is correspondingly connected with one super capacitor, each super capacitor can keep constant charging current and charging voltage when being charged, and the charging safety and stability of the super capacitor are improved.

In a second aspect, embodiments of the present application further provide a power concentrator supercapacitor system, including: a power switching circuit and a supercapacitor circuit according to the first aspect, or any one of the possible implementation manners of the first aspect; one end of the super capacitor circuit is connected with an external power supply; one end of the power supply switching circuit is connected with the other end of the super capacitor circuit and the external power supply; the other end of the power supply switching circuit is connected with a power concentrator; the power supply switching circuit is configured to switch the super capacitor circuit or the external power supply to supply power to the power concentrator.

In the implementation process, the power supply switching circuit is used for supplying power to the power concentrator under different conditions by switching the external power supply and the super capacitor circuit, so that the power supply stability of the power concentrator is improved by supplying power to the power concentrator through the super capacitor circuit when the external power supply is abnormal.

In a third aspect, an embodiment of the present application further provides a charging and discharging method of a supercapacitor circuit, including: determining an abnormal supercapacitor of the plurality of supercapacitors in the supercapacitor circuit of the first aspect, or any one of the possible implementations of the first aspect; the abnormal super capacitor is controlled to be disconnected by controlling the switch in the switch group corresponding to the abnormal super capacitor to be disconnected or closed; according to the working state of the super capacitor circuit, each switch in the switch group corresponding to the normal super capacitor except the abnormal super capacitor is controlled to be opened or closed so as to control the normal super capacitor to be connected in series or in parallel; the super capacitor circuit discharges when the normal super capacitors are connected in series, and charges when the normal super capacitors are connected in parallel.

In the implementation process, when the super capacitor circuit is charged or discharged, the abnormal condition of each super capacitor in the super capacitor circuit is determined, and the abnormal super capacitor is cut off from the super capacitor circuit, so that the influence of the abnormal super capacitor on other normal super capacitors in the super capacitor circuit is prevented, and the safety and stability of the super capacitor circuit are improved.

In one embodiment, when the supercapacitor circuit needs to be switched to the charging state, the determining an abnormal supercapacitor among a plurality of supercapacitors in the supercapacitor circuit includes: the plurality of super capacitors are controlled to be connected in parallel by switching on or off each switch in the switch group; and determining abnormal super-capacitors in the plurality of super-capacitors according to the voltage information of each super-capacitor in parallel connection.

In the implementation process, whether each super capacitor is an abnormal super capacitor is judged when each super capacitor in the super capacitor circuit is in a parallel state, so that the abnormal condition judgment of each super capacitor is independent and is not influenced, and the judgment accuracy can be improved. In addition, whether each super capacitor is an abnormal super capacitor or not is judged in parallel connection, so that the abnormal condition of each super capacitor can be judged at the same time, and the abnormal judgment efficiency is improved.

In one embodiment, when the supercapacitor circuit needs to be switched to the discharging state, the determining an abnormal supercapacitor among a plurality of supercapacitors in the supercapacitor circuit includes: and determining the abnormal super capacitor in the charging state as the abnormal super capacitor in the discharging state.

In the implementation process, before the super capacitor circuit discharges, whether each super capacitor is an abnormal super capacitor or not is detected through the abnormal condition marked when each super capacitor is charged, so that the abnormal super capacitor is prevented from being connected into the super capacitor circuit, the work of other normal super capacitors is influenced, and the safety and stability of the super capacitor circuit are improved.

In a fourth aspect, embodiments of the present application further provide an electronic device, including: a processor, a memory storing machine-readable instructions executable by the processor, which when executed by the processor, perform the steps of the method of the third aspect, or any of the possible implementations of the third aspect.

In a fifth aspect, embodiments of the present application further provide a computer readable storage medium, where a computer program is stored, where the computer program is executed by a processor to perform the steps of the method for charging and discharging a supercapacitor circuit according to the third aspect, or any one of the possible embodiments of the third aspect.

In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic circuit diagram of a supercapacitor circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic circuit diagram of a supercapacitor circuit as a backup power supply of a power concentrator according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit diagram of a super capacitor circuit provided with a voltage sampling circuit and a constant current voltage limiting circuit according to an embodiment of the present application;

fig. 4 is a schematic diagram of a power concentrator supercapacitor system provided in an embodiment of the present application;

fig. 5 is a flowchart of a charging and discharging method of a supercapacitor circuit according to an embodiment of the present application;

fig. 6 is a flowchart of charging a supercapacitor circuit according to an embodiment of the present disclosure;

Fig. 7 is a discharge flow chart of the supercapacitor circuit according to the embodiment of the present application;

fig. 8 is a schematic diagram of a functional module of a charging and discharging device of a supercapacitor circuit according to an embodiment of the present application;

fig. 9 is a block schematic diagram of an electronic device according to an embodiment of the present application.

Description of the drawings: the power supply system comprises a 20-power concentrator, a 30-power supply switching circuit, a 100-super capacitor, a 200-switch group, a 300-voltage sampling circuit, a 310-first resistor, a 320-second resistor, a 330-capacitor, a 400-constant current voltage limiting circuit, a 501-determining module, a 502-first control module, a 503-second control module, 900-electronic equipment, a 911-memory and a 913-processor.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

The electricity meter reading concentrator is used as an on-site electricity consumption information acquisition device in an electricity consumption information acquisition system, and needs to be capable of timely and accurately acquiring various running states. Even in the event of an ac power outage, it is desirable to be able to communicate information to the remote management system in a timely manner. Supercapacitors are often used today for backup power systems for concentrators.

When the power supply of the main power source (such as mains supply, generator supply and the like) is normal, the main power source directly supplies power to the central processing unit, the memory, the communication unit and other elements of the power concentrator. When the main power supply fails, the power supply switching circuit is switched to the super capacitor group to supply power for the power concentrator. The super capacitor group generally comprises two super capacitors and a voltage equalizing circuit, and the voltage equalizing circuit is used for guaranteeing the voltage consistency of the two super capacitors and avoiding influencing the service life of the super capacitors due to the voltage inconsistency.

The inventor of the application finds that the prior super capacitor bank structure has the following defects in actual use:

1. each super capacitor in the super capacitor group cannot be fully utilized. For example, the voltage of two super capacitors connected in series is 5.4V, and when the voltage is reduced to a certain extent (for example, lower than 3V), the super capacitor group cannot continue to supply power.

2. The super capacitor group has higher voltage consistency requirements on each super capacitor, and a voltage equalizing circuit is usually required to be arranged in order to ensure that the voltages of the two super capacitors are consistent.

3. When one super capacitor in the super capacitor group has larger attenuation or fails, the whole super capacitor group is affected, and the reliability of the super capacitor group is further affected.

In view of this, the present application proposes a supercapacitor circuit, by setting a plurality of switch groups, and each supercapacitor is correspondingly connected with at least one switch group, and the connection mode of the corresponding supercapacitor in the supercapacitor circuit can be controlled by controlling the opening or closing of each switch in the switch group, so that the plurality of supercapacitors are charged when being connected in parallel, and discharged when being connected in series. That is, when the super capacitors in the super capacitor circuit are charged, the super capacitors are charged independently, so that the voltage consistency requirement on each super capacitor can be reduced, a voltage equalizing circuit is not required, the super capacitor circuit structure is reduced, and the cost of the super capacitor circuit is reduced. In addition, when a plurality of super capacitors in the super capacitor circuit are discharged, each super capacitor can release lower voltage, the capacity requirement on a single super capacitor can be reduced, the cost of the single super capacitor is reduced, and the overall cost of the super capacitor circuit is further reduced.

Referring to fig. 1, a schematic circuit diagram of a supercapacitor circuit provided in an embodiment of the present application includes: a plurality of supercapacitors 100 and a plurality of switch banks 200.

The super capacitor 100 is an energy storage element between the capacitor 330 and the battery, and the super capacitor 100 has the characteristic of rapid charge and discharge of the capacitor 330 and has an energy storage mechanism of an electrochemical battery. Each super capacitor 100 is correspondingly connected with at least one switch group 200; adjacent two supercapacitors 100 are connected by a switch bank 200.

One or more switches may be included in each switch bank 200 herein. The plurality of switch banks 200 are configured to control the plurality of supercapacitors 100 in series or parallel by opening or closing individual switches in the plurality of switch banks 200.

Alternatively, each switch in the switch group 200 may be an analog switch, a triode, a relay, or the like, and the switches in the switch group 200 may be selected according to actual situations.

The number of switches, the types of switches, the connection modes of the switches in the plurality of switch groups 200 may be the same or different, or may be partially the same, and the number of switches, the types of switches, the connection modes of the switches in each switch group 200 may be adjusted according to actual situations.

It should be appreciated that each switch bank 200 is configured to control the access to, or disconnection of, the supercapacitor circuit by each respective supercapacitor 100. When a certain switch group 200 controls the corresponding super capacitor 100 to access the super capacitor circuit, the switch group 200 can also control the connection mode of the super capacitor 100 and other super capacitors 100 in the super capacitor circuit by controlling the corresponding switch in the switch group 200 to be opened or closed.

In one embodiment, as shown in fig. 1, the super capacitor circuit can be directly used as a main power supply of the electric equipment, and the super capacitor circuit supplies power to the electric equipment in a normal state.

In another embodiment, as shown in fig. 2, the super capacitor circuit is used as a backup power source of the electric device, and when the main power of the electric device normally supplies power to the electric device, the external power source charges each super capacitor 100 in the super capacitor circuit. If the remaining power of each super capacitor 100 in the super capacitor circuit reaches the power threshold, the charging is stopped, and the super capacitor circuit waits. When the main power supply of the electric equipment is abnormal, the electric equipment is powered by controlling part or all of the super capacitors 100 in the super capacitor circuit.

The super capacitor circuit discharges when the super capacitors 100 are connected in series, and charges when the super capacitors 100 are connected in parallel.

Alternatively, the individual supercapacitors 100 in the supercapacitor circuit may all be connected in series, all be connected in parallel, some be connected in series, some be connected in parallel, etc. The connection mode of each super capacitor 100 in the super capacitor circuit can be adjusted according to actual situations.

For example, if all the supercapacitors 100 in the supercapacitor circuit are normal supercapacitors 100, and the remaining power of all the supercapacitors 100 does not reach the power threshold, all the supercapacitors 100 may be controlled to be connected in parallel to charge each supercapacitor 100 respectively.

If some supercapacitors 100 in the supercapacitor circuit are in an abnormal state, the switches in the switch group 200 corresponding to the supercapacitors 100 in the abnormal state can be opened or closed to control the supercapacitors 100 in the abnormal state to be cut off from the supercapacitor circuit. In addition, if the residual electric quantity in all the normal state supercapacitors 100 does not reach the electric quantity threshold, all the normal state supercapacitors 100 can be controlled to be connected in parallel so as to charge each normal state supercapacitor 100 respectively.

If all the supercapacitors 100 in the supercapacitor circuit are normal supercapacitors 100, and only the residual electric quantity in part of the supercapacitors 100 does not reach the electric quantity threshold, the part of the supercapacitors 100 with the residual electric quantity which does not reach the electric quantity threshold can be controlled to be connected in parallel so as to charge each supercapacitor 100 with the residual electric quantity which does not reach the electric quantity threshold.

If all the supercapacitors 100 in the supercapacitor circuit are normal supercapacitors 100 and the power consumption of the electric equipment is large, all the supercapacitors 100 can be controlled to be connected in series so as to supply power to the electric equipment through all the supercapacitors 100.

If all the supercapacitors 100 in the supercapacitor circuit are normal supercapacitors 100 and the power consumption of the electric equipment is small, the partial supercapacitors 100 can be controlled to be connected in series so as to supply power to the electric equipment through the partial supercapacitors 100.

Of course, if all the supercapacitors 100 in the supercapacitor circuit are normal supercapacitors 100 and the power consumption of the electric equipment is smaller, all the supercapacitors 100 can be controlled to be connected in series so as to supply power to the electric equipment through all the supercapacitors 100.

If some supercapacitors 100 in the supercapacitor circuit are in an abnormal state, the switches in the switch group 200 corresponding to the supercapacitors 100 in the abnormal state can be opened or closed to control the supercapacitors 100 in the abnormal state to be cut off from the supercapacitor circuit. In addition, all the supercapacitors 100 in the normal state are controlled to be connected in series so as to supply power to the electric equipment through the supercapacitors 100 in the normal state.

The connection manner of the plurality of supercapacitors 100 in the supercapacitor circuit is merely exemplary, and the connection manner of the supercapacitors 100 in the supercapacitor circuit may be adjusted according to practical situations.

In the above implementation process, by setting a plurality of switch groups 200, and each supercapacitor 100 is correspondingly connected with at least one switch group 200, the connection mode of the corresponding supercapacitor 100 in the supercapacitor circuit can be controlled by controlling the opening or closing of each switch in the switch group 200, so that the plurality of supercapacitors 100 are charged when connected in parallel, and discharged when connected in series. That is, when the super capacitors 100 in the super capacitor circuit are charged, the super capacitors are charged independently, so that the voltage consistency requirement on each super capacitor 100 can be reduced, a voltage equalizing circuit is not required, the super capacitor circuit structure is reduced, and the cost of the super capacitor circuit is reduced. In addition, when a plurality of super capacitors 100 in the super capacitor circuit are discharged, each super capacitor 100 can release lower voltage, the capacity requirement on a single super capacitor 100 can be reduced, the cost of the single super capacitor 100 is reduced, and the overall cost of the super capacitor circuit is further reduced.

In one possible implementation, as shown in fig. 1 and 2, the switch group 200 includes: a first switch, a second switch and a third switch.

Wherein the first end of the first switch and the first end of the second switch are connected to the positive electrode of the previous adjacent super capacitor 100; the first end of the third switch is connected with the first end of the corresponding third switch of the previous adjacent super capacitor 100 and grounded; the second end of the first switch is connected with the anode of the corresponding super capacitor 100; the second end of the second switch and the second end of the third switch are connected to the negative electrode of the corresponding super capacitor 100.

The first, second and third switches herein are configured to be opened and closed therethrough to switch the manner of connection of the respective plurality of supercapacitors 100.

It should be appreciated that for each super capacitor 100 in the super capacitor circuit, the respective connection may include: in series with other supercapacitors 100, in parallel with other supercapacitors 100, and in connection with the supercapacitor circuit is cut off. Different connection modes need to be matched through different switches to switch.

For example, as shown in fig. 1 and 2, if a plurality of supercapacitors 100 in the supercapacitor circuit are in a charged state, the third switches (S1-3, S2-3, S3-3, and S4-3 shown in fig. 1 and 2) in each switch group 200 are closed, and the first switches (S2-1, S3-1, and S4-1 shown in fig. 1 and 2) and the second switches (S2-2, S3-2, and S4-2 shown in fig. 1 and 2) in each switch group 200 are open.

If all supercapacitors 100 in the supercapacitor circuit are in a discharging state, the third switch (S1-3 shown in fig. 1 and 2) in the first switch group 200 is closed, the second switches (S2-2, S3-2 and S4-2 shown in fig. 1 and 2) in the other respective switch groups 200 are closed, and the first switch (S2-1, S3-1 and S4-1 shown in fig. 1 and 2) and the third switch (S2-3, S3-3 and S4-3 shown in the drawings) are open.

If all supercapacitors 100 in the supercapacitor circuit are in a discharging state and the second supercapacitor 100 is abnormal, the third switch (S1-3 shown in fig. 1 and 2) in the first switch group 200 is closed, the first switch (S2-1 shown in fig. 1 and 2) in the second switch group 200 is closed, and the second switch (S2-2 shown in fig. 1 and 2) and the third switch (S2-3 shown in the drawings) are opened. The second switch (S3-2 and S4-2 shown in fig. 1, 2) and the first switch (S3-1 and S4-1 shown in fig. 1, 2) and the third switch (S3-3 and S4-3 shown in fig. 1, 2) of the other respective switch groups 200 are closed.

If all supercapacitors 100 in the supercapacitor circuit are in a discharging state and the first supercapacitor 100 is abnormal, the third switch (S1-3 shown in fig. 1 and 2) in the first switch group 200 is opened, and the third switch (S2-3 shown in fig. 1 and 2) in the second switch group 200 is closed. The second switch (S3-2 and S4-2 shown in fig. 1, 2) and the first switch (S3-1 and S4-1 shown in fig. 1, 2) and the third switch (S3-3 and S4-3 shown in fig. 1, 2) of the other respective switch groups 200 are closed.

The opening and closing manners of the respective switches in the respective switch groups 200 described above are merely exemplary, and the opening and closing manners of the respective switches in the respective switch groups 200 in the supercapacitor circuit may be adjusted according to actual situations.

In the implementation process, due to the simple structure and low cost of the switch, by setting the first switch, the second switch and the third switch in each switch group 200, the connection modes of the corresponding super capacitor 100, other super capacitors 100 and the super capacitor circuit can be switched by switching the open and close states of the first switch, the second switch and the third switch, so that the connection modes of a plurality of super capacitors 100 in the super capacitor circuit can be switched, the complexity of the super capacitor circuit can be reduced, and the cost is reduced. In addition, the abnormal super capacitor 100 can be cut off from the super capacitor circuit through the cooperation of the first switch, the second switch and the third switch, so that the abnormal super capacitor 100 is prevented from affecting other normal super capacitors 100, and the overall stability and safety of the circuit are improved.

In one possible implementation, only the third switch is included in the corresponding switch bank 200 of the first supercapacitor 100.

Wherein, the first end of the third switch corresponding to the first super capacitor 100 is connected to the first end of the third switch corresponding to the next adjacent super capacitor 100 and grounded; the second end of the corresponding third switch of the first super capacitor 100 is connected to the negative electrode of the first super capacitor 100.

The corresponding third switch of the first supercapacitor 100 is configured to be opened and closed to switch the connection mode of the first supercapacitor 100.

The super capacitors 100 in the super capacitor circuit are sequentially arranged in a set order. When a plurality of super capacitors 100 in the super capacitor circuit are connected in series, the super capacitor 100 connected with an external power supply is the first super capacitor 100, and the super capacitor 100 connected with the electric equipment is the tail super capacitor 100.

It should be appreciated that since the first supercapacitor 100 is directly connected to an external power source, no other supercapacitor 100 is in front of the first supercapacitor 100, and the manner of connection (series or parallel) with the preceding supercapacitor 100 need not be considered. Thus, for the first supercapacitor 100, only a switch (i.e., a third switch) for controlling whether the first supercapacitor 100 is connected to the supercapacitor circuit needs to be provided, and the first supercapacitor 100 is controlled to be connected to or disconnected from the supercapacitor circuit by the third switch.

In the implementation process, for the first supercapacitor 100, only whether to access the supercapacitor circuit is needed, and the connection mode with other supercapacitors 100 is not needed, so that only the third switch is needed to be set for controlling the first supercapacitor 100 to access or disconnect from the supercapacitor 100, thereby reducing the switch setting of the first switch group 200 corresponding to the first supercapacitor 100 and further reducing the cost of the first switch group 200.

In one possible implementation, as shown in fig. 3, the supercapacitor circuit further includes: a plurality of voltage sampling circuits 300.

Each voltage sampling circuit 300 is disposed in parallel at two ends of each super capacitor 100.

The voltage sampling circuit 300 herein is configured to detect whether an abnormality exists in the corresponding super capacitor 100.

The voltage sampling circuit 300 includes a voltage dividing circuit and an ADC sampling module. The voltage dividing circuit is used for sampling the divided voltage through the ADC sampling module after the corresponding super capacitor 100 is divided, so as to obtain a corresponding sampling voltage.

It should be understood that, the ADC sampling module is disposed in the central processing unit, when the ADC sampling module collects the sampling voltage of the corresponding super voltage, the central processing unit determines charging information such as the charging voltage, the charging time, the charging capacity 330 and the like of the corresponding super capacitor 100 according to the collected sampling voltage, and draws a charging curve according to the charging information, so as to determine whether the corresponding super capacitor 100 is abnormal.

In the implementation process, the corresponding voltage sampling circuit 300 is set for each super capacitor 100, so as to be used for collecting the voltage of each super capacitor 100, further judging whether the corresponding super capacitor 100 is abnormal or not, so as to monitor whether each super capacitor 100 is abnormal or not, thereby being beneficial to disconnecting the fault super capacitor 100 in time and improving the overall stability and safety of the super capacitor circuit.

In one possible implementation, the voltage sampling circuit 300 includes: a first resistor 310, a second resistor 320, and a capacitor 330.

Wherein, the first end of the first resistor 310 is connected to the positive electrode of the corresponding super capacitor 100; the first end of the second resistor 320 is connected to the second end of the first resistor 310 and the first end of the capacitor 330; a second terminal of the capacitor 330 is connected to the negative electrode of the corresponding super capacitor 100 and the second terminal of the capacitor 330 to ground.

The first resistor 310 and the second resistor 320 are here configured to divide the voltage across the respective super capacitor 100.

It should be appreciated that the rated voltage of the super capacitor 100 is between 2.5V and 5.5V, while the rated voltage of the ADC sampling module is between 0.8V and 1V. Obviously, the rated voltage of the super capacitor 100 has certain deviation from the rated voltage of the ADC sampling module, and the voltage of the super capacitor 100 can be divided into a voltage range which can be processed by the ADC sampling module by arranging a voltage acquisition circuit between the super capacitor 100 and the ADC sampling module, so that the ADC sampling module is prevented from being damaged due to overhigh voltage.

In the implementation process, by setting the first resistor 310 and the second resistor 320 to divide the voltage on the corresponding super capacitor 100, the voltage of the super capacitor 100 can be divided into the voltage range that can be processed by the ADC sampling module, so that the ADC sampling module is prevented from being damaged due to too high voltage, and the safety and stability of the voltage sampling circuit 300 are improved.

In one possible implementation, as shown in fig. 3, the supercapacitor circuit further includes: a plurality of constant current voltage limiting circuits 400.

The first end of each constant-current voltage limiting circuit 400 is connected to an external power source, and the second end of each constant-current voltage limiting circuit 400 is connected to the positive electrode of the corresponding super capacitor 100.

The constant current voltage limiting circuit 400 herein is configured to limit the voltage and current into the corresponding super capacitor 100.

Alternatively, the external power source may be mains power, diesel power, solar power, etc., and the specific power source type of the external power source may be selected according to practical situations.

It should be appreciated that the external power source is typically some high-voltage power source, typically rated at a higher voltage level of 220V, 110V, etc., while the super capacitor 100 has a voltage between 2.5V and 5.5V. Therefore, in order to secure the charging safety of the super capacitor 100, a limiting circuit needs to be provided between the external power source and the super capacitor 100 to limit the charging voltage for charging the super capacitor 100 when the super capacitor 100 is charged by the external power source.

In addition, in order to ensure the charging stability of the super capacitor 100, the charging stability of the super capacitor 100 may be improved by providing a constant current power supply between an external power supply and the super capacitor 100.

In the implementation process, by setting the plurality of constant current voltage limiting circuits 400, and each constant current voltage limiting circuit 400 is correspondingly connected with one super capacitor 100, each super capacitor 100 can maintain constant charging current and sustainable charging voltage when being charged, and the charging safety and stability of the super capacitor 100 are improved.

Referring to fig. 4, a schematic diagram of a super capacitor system of a power concentrator according to an embodiment of the present application includes: the power switching circuit 30 is in accordance with the super capacitor circuit of the above-described embodiments.

One end of the super capacitor circuit is connected with an external power supply; one end of the power supply switching circuit 30 is connected with the other end of the super capacitor circuit and an external power supply; the other end of the power supply switching circuit 30 is connected to the power concentrator 20.

The power switching circuit 30 is here configured to switch the super capacitor circuit or an external power source to power the power concentrator 20.

The super capacitor circuit described above is configured to serve as a backup power source for the power concentrator 20.

It should be appreciated that while the external power source may normally power the power concentrator 20, the external power source may power the power concentrator 20. When the external power supply is in an abnormal condition and cannot supply power to the power concentrator 20, the power supply of the power concentrator 20 is switched from the external power supply to the super capacitor circuit through the power supply switching circuit 30, and the power concentrator 20 is supplied with power through the super capacitor circuit.

In one embodiment, the supercapacitor circuit and external power supply may also be configured to power the power concentrator 20 for a time period.

Illustratively, when the external power source is supplying mains power, the power concentrator 20 may be powered by the external power source during low peak periods of power consumption, while the external power source charges each super capacitor 100 in the super capacitor circuit. During peak power use, the power concentrator 20 may be powered solely by the supercapacitor circuit. The power consumption of the power concentrator 20 is reduced while balancing the power supply system power.

In the above implementation process, by setting the power switching circuit 30, the power switching circuit 30 supplies power to the power concentrator 20 under different conditions by switching the external power supply and the super capacitor circuit, so that when the external power supply is abnormal, the super capacitor circuit can supply power to the power concentrator 20, thereby improving the power supply stability of the power concentrator 20.

Fig. 5 is a flowchart of a charging and discharging method of a supercapacitor according to an embodiment of the present application. The specific flow shown in fig. 5 will be described in detail.

Step S201, determining an abnormal supercapacitor among a plurality of supercapacitors in the supercapacitor circuit in the above embodiment.

Here, the abnormality may include a charge abnormality, a discharge abnormality, a fault, etc., and the abnormality of the supercapacitor may be selected according to the actual situation.

The abnormal super capacitor can be determined by a voltage sampling circuit. In the charging process of the super capacitor, whether the super capacitor is abnormal or not is judged through the charging curve of the super capacitor.

The abnormal curve is a curve drawn by taking charging electricity quantity, charging voltage and charging time as parameters.

The abnormal conditions of the super capacitors in the super capacitor circuit are respectively determined by the corresponding voltage sampling circuit.

Step S202, the abnormal super capacitor is controlled to be disconnected by controlling the switch in the switch group corresponding to the abnormal super capacitor to be opened or closed.

When the super capacitor is in different charge and discharge states, the opened or closed switches in the corresponding switch group are different.

For example, when each super capacitor in the super capacitor circuit is charged in parallel, if a certain super capacitor is an abnormal super capacitor, the super capacitor can be cut off from the super capacitor circuit by switching off the first switch, the second switch and the third switch in the corresponding switch group of the super capacitor. When each super capacitor in the super capacitor circuit is in series discharge, if one super capacitor is an abnormal super capacitor, the first switch can be closed by opening the second switch and the third switch in the corresponding switch group of the super capacitor, so that the super capacitor is cut off from the super capacitor circuit.

When the abnormal super capacitor is the first super capacitor, when the first super capacitor is charged and discharged, a corresponding third switch of the first super capacitor is disconnected, and the first super capacitor is cut off from the super capacitor circuit.

Step S203, according to the working state of the super capacitor circuit, each switch in the switch group corresponding to the normal super capacitor except the abnormal super capacitor is controlled to be opened or closed so as to control the normal super capacitor to be connected in series or in parallel.

The super capacitor circuit discharges when the normal super capacitors are connected in series, and the super capacitor circuit charges when the normal super capacitors are connected in parallel.

For example, as shown in fig. 4, if the second supercapacitor in fig. 4 is an abnormal supercapacitor and a plurality of supercapacitors in the supercapacitor circuit are in a charged state, the first switch (S2-1 shown in fig. 4), the second switch (S2-2 shown in fig. 4) and the third switch (S2-3 shown in fig. 4) in the corresponding switch group of the second supercapacitor are turned off. The third switch (S1-3, S3-3, and S4-3 shown in fig. 4) in each of the other switch groups of the super capacitor is closed, and the first switch (S3-1 and S4-1 shown in fig. 4) and the second switch (S3-2 and S4-2 shown in fig. 4) in each switch group are open.

If the second supercapacitor in fig. 4 is an abnormal supercapacitor and the supercapacitors in the supercapacitor circuit are in a discharging state, the first switch (S2-1 shown in fig. 4) in the corresponding switch group of the second supercapacitor is closed, and the second switch (S2-2 shown in fig. 4) and the third switch (S2-3 shown in fig. 4) in the corresponding switch group of the second supercapacitor are opened. The second switch (S3-2 and S4-2 shown in fig. 4) and the first switch (S3-1 and S4-1 shown in fig. 4) and the third switch (S1-3, S3-3 and S4-3 shown in fig. 4) of the respective switch groups of the other super capacitors are closed.

If the second supercapacitor and the third supercapacitor in fig. 5 are abnormal supercapacitors and the supercapacitors in the supercapacitor circuit are in a charged state, the first switch (S2-1 and S3-1 shown in fig. 5), the second switch (S2-2 and S3-2 shown in fig. 5) and the third switch (S2-3 and S3-3 shown in fig. 5) in the corresponding switch groups of the second supercapacitor and the third supercapacitor are turned off. The third switch (S1-3 and S4-3 shown in fig. 5) in each respective switch group of the other super capacitor is closed, and the first switch (S4-1 shown in fig. 5) and the second switch (S4-2 shown in fig. 5) in each switch group are open.

If the second supercapacitor and the fourth supercapacitor in fig. 6 are abnormal supercapacitors and the supercapacitors in the supercapacitor circuit are in a discharge state, the first switches (S2-1 and S4-1 shown in fig. 6) in the corresponding switch groups of the second supercapacitor and the fourth supercapacitor are closed, and the second switches (S2-2 and S4-2 shown in fig. 6) and the third switches (S2-3 and S4-3 shown in fig. 6) in the corresponding switch groups of the second supercapacitor and the fourth supercapacitor are opened. The second switch (S3-2 shown in fig. 6) and the first switch (S3-1 shown in fig. 6) and the third switch (S1-3 and S3-3 shown in fig. 6) of the respective switch groups of the other super capacitors are closed.

If all supercapacitors in the supercapacitor circuit are in a discharging state and the first supercapacitor is abnormal, a third switch (S1-3 shown in fig. 7) in the first switch group is opened, and a third switch (S2-3 shown in fig. 7) in the second switch group is closed. The second switch (S3-2 and S4-2 shown in fig. 7) and the first switch (S3-1 and S4-1 shown in fig. 7) and the third switch (S3-3 and S4-3 shown in fig. 7) of the other respective switch groups are closed.

The above-mentioned abnormal conditions of the super capacitor are merely exemplary, and the abnormal conditions of the super capacitor in the super capacitor circuit and the opening and closing manners of the switches in the switch groups can be adjusted according to actual conditions.

In the implementation process, when the super capacitor circuit is charged or discharged, the abnormal condition of each super capacitor in the super capacitor circuit is determined, and the abnormal super capacitor is cut off from the super capacitor circuit, so that the influence of the abnormal super capacitor on other normal super capacitors in the super capacitor circuit is prevented, and the safety and stability of the super capacitor circuit are improved.

In one possible implementation, in a case where the supercapacitor circuit needs to be switched to the charging state, step S201 includes: the plurality of super capacitors are controlled to be connected in parallel by switching on or off each switch in the switch group; and determining abnormal super-capacitors in the plurality of super-capacitors according to the voltage information of each super-capacitor in the parallel connection.

It can be understood that when each super capacitor in the super capacitor circuit is charged in parallel, the voltage sampling circuit connected with each super capacitor respectively acquires the voltage information of the corresponding super capacitor, so as to judge whether each super capacitor is abnormal or not according to the voltage information of each super capacitor point.

If an abnormality exists in a certain super capacitor, each switch in the corresponding switch group of the super capacitor is controlled to switch the on-off state, and the abnormal super capacitor is cut off from the super capacitor circuit. And for a normal super capacitor, the normal super capacitor is continuously charged until the super capacitor is full.

Illustratively, as shown in fig. 6, taking the supercapacitor circuit in fig. 4 as an example, the first supercapacitor starts to charge, and the voltage sampling circuit connected to the first supercapacitor detects the charging state of the first supercapacitor and determines whether the first supercapacitor is abnormal according to the charging curve. If the first super capacitor is abnormal, the first switch of the first super capacitor is turned off (S1-3 shown in fig. 4), and if the first super capacitor is judged to be a normal capacitor, charging of the first super capacitor is continued until the charging is finished. And the second super capacitor starts to charge, a voltage sampling circuit connected with the second super capacitor detects the charging state of the second super capacitor, and whether the second super capacitor is abnormal or not is judged through a charging curve. If the second supercapacitor is abnormal, the first switch of the second supercapacitor is turned off (S2-3 shown in fig. 4), and if the second supercapacitor is judged to be a normal capacitor, The charging of the second super capacitor is continued until the end of the filling _…… And repeating until all the supercapacitors in the supercapacitor circuit are detected.

The abnormal conditions of the plurality of supercapacitors in the supercapacitor circuit can be judged at the same time, or can be judged respectively. The abnormal condition of the super capacitor in the super capacitor circuit can be adjusted according to actual conditions.

In the implementation process, whether each super capacitor is an abnormal super capacitor is judged when each super capacitor in the super capacitor circuit is in a parallel state, so that the abnormal condition judgment of each super capacitor is independent and is not influenced, and the judgment accuracy can be improved. In addition, whether each super capacitor is an abnormal super capacitor or not is judged in parallel connection, so that the abnormal condition of each super capacitor can be judged at the same time, and the abnormal judgment efficiency is improved.

In one possible implementation, in a case where the supercapacitor circuit needs to be switched to the discharging state, step S201 includes: and determining the abnormal super capacitor in the charging state as the abnormal super capacitor in the discharging state.

It should be understood that when each super capacitor in the super capacitor circuit is being charged, whether the abnormal condition exists in each super capacitor is judged through the corresponding voltage sampling circuit, and the abnormal super capacitor with the abnormal condition is marked and cut off from the super capacitor circuit.

When the super capacitor circuit needs to be switched to discharge, whether each super capacitor is an abnormal super capacitor or not is detected, and the abnormal super capacitor is short-circuited so as to cut off the abnormal super capacitor from the super capacitor circuit.

For example, as shown in fig. 7, taking the supercapacitor circuit in fig. 4 as an example, detecting whether the first supercapacitor is abnormal, if the first supercapacitor is abnormal, continuing to determine whether the second supercapacitor is abnormal, and if the second supercapacitor is not abnormal, closing the second switch of the second supercapacitor (S2-2 shown in fig. 4); continuing to judge whether the third super capacitor is abnormal, if the third super capacitor is not abnormal, closing a second switch (S3-2 shown in fig. 4) of the third super capacitor, and if the third super capacitor is abnormal, closing a first switch (S3-1 shown in fig. 4) of the third super capacitor; and continuously judging whether the fourth super capacitor is abnormal, if the fourth super capacitor is not abnormal, closing a second switch (S4-2 shown in fig. 4) of the fourth super capacitor, if the fourth super capacitor is abnormal, closing a first switch (S4-1 shown in fig. 4) of the fourth super capacitor, and repeatedly judging each super capacitor in the super capacitor circuit according to the rule until all the super capacitors are judged to be finished.

When judging the abnormal condition of each super capacitor, each super capacitor can be directly judged according to the abnormal condition marked when each super capacitor is charged.

In the implementation process, before the super capacitor circuit discharges, whether each super capacitor is an abnormal super capacitor or not is detected through the abnormal condition marked when each super capacitor is charged, so that the abnormal super capacitor is prevented from being connected into the super capacitor circuit, the work of other normal super capacitors is influenced, and the safety and stability of the super capacitor circuit are improved.

Based on the same application conception, the embodiment of the application also provides a super capacitor circuit charging and discharging device corresponding to the super capacitor circuit charging and discharging method, and because the principle of solving the problem of the device in the embodiment of the application is similar to that of the embodiment of the super capacitor circuit charging and discharging method, the implementation of the device in the embodiment of the application can be referred to the description in the embodiment of the method, and the repetition is omitted.

Fig. 8 is a schematic diagram of a functional module of a charging and discharging device of a supercapacitor according to an embodiment of the present application. Each module in the supercapacitor circuit charging and discharging device in the present embodiment is configured to execute each step in the foregoing method embodiment. The super capacitor circuit charging and discharging device comprises a determining module 501, a first control module 502 and a second control module 503; wherein,

The determining module 501 is configured to determine an abnormal supercapacitor among a plurality of supercapacitors in the supercapacitor circuit in the above embodiment.

The first control module 502 is configured to control the abnormal super capacitor to be disconnected by controlling the switch in the switch group corresponding to the abnormal super capacitor to be opened or closed.

The second control module 503 is configured to control, according to the working state of the supercapacitor circuit, each switch in the switch group corresponding to a normal supercapacitor except for the abnormal supercapacitor to be opened or closed, so as to control the normal supercapacitor to be connected in series or in parallel; the super capacitor circuit discharges when the normal super capacitors are connected in series, and charges when the normal super capacitors are connected in parallel.

In a possible implementation manner, the determining module 501 is specifically configured to: the plurality of super capacitors are controlled to be connected in parallel by switching on or off each switch in the switch group; and determining abnormal super-capacitors in the plurality of super-capacitors according to the voltage information of each super-capacitor in parallel connection.

In a possible implementation manner, the determining module 501 is specifically configured to: and determining the abnormal super capacitor in the charging state as the abnormal super capacitor in the discharging state.

For the convenience of understanding the present embodiment, the following describes in detail an electronic device that executes the method for charging and discharging the supercapacitor circuit disclosed in the embodiments of the present application.

As shown in fig. 9, a block schematic diagram of the electronic device is shown. The electronic device 900 may include a memory 911 and a processor 913. It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 9 is merely illustrative and is not intended to limit the configuration of the electronic device 900. For example, electronic device 900 may also include more or fewer components than shown in FIG. 9, or have a different configuration than shown in FIG. 9.

The memory 911 and the processor 913 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The processor 913 is configured to execute the executable module stored in the memory.

The Memory 911 may be, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc. The memory 911 is configured to store a program, and the processor 913 executes the program after receiving an execution instruction, so that the method executed by the electronic device 900 defined by the process disclosed in any embodiment of the present application may be applied to the processor 913 or implemented by the processor 913.

The processor 913 may be an integrated circuit chip having signal processing capabilities. The processor 913 may be a general-purpose processor, including a central processor (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (digital signal processor, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The electronic device 900 in this embodiment may be used to perform each step in each method provided in the embodiments of the present application.

In addition, the embodiment of the application further provides a computer readable storage medium, and a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the steps of the super capacitor circuit charging and discharging method in the embodiment of the method are executed.

The computer program product of the supercapacitor circuit charging and discharging method provided in the embodiments of the present application includes a computer readable storage medium storing program codes, where the instructions included in the program codes may be used to execute the steps of the supercapacitor circuit charging and discharging method described in the embodiments of the method, and the details of the method embodiments may be referred to herein and are not described herein.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A supercapacitor circuit, comprising: a plurality of supercapacitors and a plurality of switch sets;

each super capacitor is correspondingly connected with at least one switch group;

two adjacent super capacitors are connected through the switch group;

Wherein the plurality of switch groups are configured to control the plurality of super capacitors to be connected in series or in parallel by opening or closing each switch in each of the plurality of switch groups; the super capacitor circuit discharges when the plurality of super capacitors are connected in series, and the super capacitor circuit charges when the plurality of super capacitors are connected in parallel.

2. The supercapacitor circuit according to claim 1, wherein the switch bank comprises: a first switch, a second switch, and a third switch;

the first end of the first switch and the first end of the second switch are connected with the positive electrode of the previous adjacent super capacitor;

the first end of the third switch is connected with the first end of the third switch corresponding to the previous adjacent super capacitor and grounded;

the second end of the first switch is connected with the positive electrode of the corresponding super capacitor;

the second end of the second switch and the second end of the third switch are connected with the cathodes of the corresponding super capacitors;

the first switch, the second switch and the third switch are configured to be opened and closed through the first switch, so as to switch the connection modes of the corresponding super capacitors.

3. The supercapacitor circuit according to claim 2, wherein only the third switch is included in the group of switches corresponding to the first supercapacitor;

The first end of the third switch corresponding to the first super capacitor is connected with the first end of the third switch corresponding to the next adjacent super capacitor and grounded;

the second end of the third switch corresponding to the first super capacitor is connected with the negative electrode of the first super capacitor;

the third switch corresponding to the first super capacitor is configured to be opened and closed through the third switch so as to switch the connection mode of the first super capacitor.

4. A supercapacitor circuit according to any one of claims 1 to 3 further comprising: a plurality of voltage sampling circuits;

each voltage sampling circuit is arranged at two ends of each super capacitor in parallel;

the voltage sampling circuit is configured to detect whether the corresponding super capacitor is abnormal or not.

5. The supercapacitor circuit according to claim 4, wherein the voltage sampling circuit comprises: a first resistor, a second resistor and a capacitor;

the first end of the first resistor is connected with the anode of the corresponding super capacitor;

the first end of the second resistor is connected with the second end of the first resistor and the first end of the capacitor;

the second end of the capacitor is connected with the negative electrode of the corresponding super capacitor and the second end of the capacitor and grounded;

The first resistor and the second resistor are configured to divide the voltage on the corresponding super capacitor.

6. A supercapacitor circuit according to any one of claims 1 to 3 further comprising: a plurality of constant current voltage limiting circuits;

the first end of each constant-current voltage limiting circuit is connected with an external power supply, and the second end of each constant-current voltage limiting circuit is connected with the anode of a corresponding super capacitor;

the constant current voltage limiting circuit is configured to limit voltage and current entering the corresponding super capacitor.

7. A power concentrator supercapacitor system, comprising: power switching circuit the supercapacitor circuit according to any one of claims 1 to 6;

one end of the super capacitor circuit is connected with an external power supply;

one end of the power supply switching circuit is connected with the other end of the super capacitor circuit and the external power supply;

the other end of the power supply switching circuit is connected with a power concentrator;

the power supply switching circuit is configured to switch the super capacitor circuit or the external power supply to supply power to the power concentrator.

8. A method for charging and discharging a supercapacitor circuit, the method comprising:

Determining an abnormal supercapacitor of a plurality of supercapacitors in the supercapacitor circuit of any one of claims 1-6;

the abnormal super capacitor is controlled to be disconnected by controlling the switch in the switch group corresponding to the abnormal super capacitor to be disconnected or closed;

according to the working state of the super capacitor circuit, each switch in the switch group corresponding to the normal super capacitor except the abnormal super capacitor is controlled to be opened or closed so as to control the normal super capacitor to be connected in series or in parallel;

the super capacitor circuit discharges when the normal super capacitors are connected in series, and charges when the normal super capacitors are connected in parallel.

9. The method of claim 8, wherein the determining an abnormal supercapacitor of a plurality of supercapacitors in the supercapacitor circuit if the supercapacitor circuit needs to be switched to a charging state comprises:

the plurality of super capacitors are controlled to be connected in parallel by switching on or off each switch in the switch group;

and determining abnormal super-capacitors in the plurality of super-capacitors according to the voltage information of each super-capacitor in parallel connection.

10. The method of claim 9, wherein the determining an abnormal supercapacitor of the plurality of supercapacitors in the supercapacitor circuit if the supercapacitor circuit needs to be switched to a discharged state comprises:

and determining the abnormal super capacitor in the charging state as the abnormal super capacitor in the discharging state.