CN117766546A - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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Abstract
The disclosure discloses an array substrate, a manufacturing method thereof and a display panel, and the array substrate in an embodiment of the disclosure includes: the array substrate comprises a substrate base plate and a driving circuit layer arranged on the substrate base plate, wherein the driving circuit layer comprises a grid electrode layer and a source-drain metal layer, and the array substrate further comprises: a plurality of first antennas arranged along a first direction, and a second antenna arranged along a second direction and electrically isolated from the first antennas, the second direction being perpendicular to the first direction, wherein the first antennas are disposed in the gate layer, and the second antennas are disposed in the source-drain metal layer. According to the embodiment of the disclosure, the first antenna and the second antenna are respectively arranged in the grid electrode layer and the source-drain metal layer, so that electromagnetic touch integration is realized, the thickness and the process difficulty of a display product are reduced, and the application prospect is wide.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
At present, the glass substrate design of the electronic ink screen reader on the market can realize the rapid refreshing and display of paper film particles. Referring to fig. 1, however, such products cannot realize a touch function by sensing capacitance change between fingers and products due to signal shielding limitation of an ITO (indium zinc oxide) layer in an electronic paper film, and have poor interaction capability, and the electromagnetic touch function is to utilize an electromagnetic induction principle to induce electromagnetic waves generated by an antenna coil inside a display product through an electromagnetic pen and convert the electromagnetic waves into electric signals, so that control and operation of the display product are realized, and the electromagnetic touch function is realized by limiting and adjusting the working frequency of the touch pen, the related frequency of a circuit of the display product, and the like.
However, the conventional magnetic touch function is externally hung, the electromagnetic touch resonance plate is independently or externally hung on the screen, the module thickness is high, and the conventional touch screen of products such as liquid crystal display needs to be internally integrated with a plurality of additional touch layers on the array substrate, so that the process difficulty is increased, and the peripheral wiring space is occupied.
Therefore, a new in-plane integrated magnetic touch display product is needed to meet the requirements of light weight and narrow frame of the electronic ink screen.
Disclosure of Invention
In order to solve at least one of the above problems, a first aspect of the present disclosure provides an array substrate including a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer including a gate layer and a source drain metal layer,
the array substrate further includes: a plurality of first antennas arranged along a first direction, and a second antenna arranged along a second direction perpendicular to the first direction and electrically isolated from the first antennas,
the first antenna is arranged in the grid electrode layer, and the second antenna is arranged in the source-drain metal layer.
In some alternative embodiments, the array substrate further includes a display region and a non-display region, and the array substrate further includes: a first common electrode signal line at least partially surrounding the display region, the first common electrode signal line disposed in the gate layer, and a first antenna and a second antenna disposed in the display region
The first antenna is a loop coil formed by at least two first conductive parts, the first ends of the first conductive parts of each first antenna are connected in parallel, the second ends are electrically connected with the first common electrode signal wire,
the second antenna is a loop coil formed by at least two second conductive parts, the first ends of the second conductive parts of the second antenna are connected in parallel, and the second ends of the second conductive parts are electrically connected with the first common electrode signal wire through a via hole penetrating to the grid layer.
In some alternative embodiments, the first conductive portion is a straight line segment extending in the second direction and crossing the display area, and the second conductive portion is a straight line segment extending in the first direction and crossing the display area.
In some alternative embodiments, the array substrate further includes: a plurality of first sensing wires and a plurality of second sensing wires arranged in the non-display area, wherein the first sensing wires are arranged in the grid electrode layer, the second sensing wires are arranged in the source-drain metal layer,
the first sensing wires are connected with the first ends of the first antennas in a one-to-one correspondence manner, and the second sensing wires are connected with the first ends of the second antennas in a one-to-one correspondence manner.
In some alternative embodiments, the array substrate includes a first wiring area, a display area, and a second wiring area sequentially distributed along a second direction, and the array substrate further includes:
a plurality of scanning signal lines and a plurality of data jumpers arranged in the display area and arranged along the first direction; and
a plurality of data signal lines disposed in the display area and arranged in the second direction,
the scanning signal lines and the data jumpers are arranged in the grid electrode layer, the data signal lines are arranged in the source-drain metal layer, and the data signal lines are electrically connected with the data jumpers in a one-to-one correspondence mode through holes penetrating through the grid electrode layer.
In some optional embodiments, the array substrate includes a first wiring area, a display area, and a second wiring area sequentially distributed along the first direction, and the array substrate further includes:
a plurality of data signal lines and a plurality of scan jumper lines arranged in the display area and arranged along the second direction; and
a plurality of scanning signal lines disposed in the display area and arranged along the first direction,
the data signal lines and the scanning jumper wires are arranged in the source-drain metal layers, the scanning signal lines are arranged in the grid electrode layers, and the scanning jumper wires are electrically connected with the scanning signal lines in a one-to-one correspondence mode through holes penetrating through the grid electrode layers.
In some alternative embodiments, the array substrate further includes: a plurality of pixel electrodes arranged in an array and a plurality of common electrodes arranged corresponding to the pixel electrodes,
the array substrate further includes a pixel electrode layer disposed on the driving circuit layer,
the common electrode is disposed on the source-drain metal layer, and the pixel electrode is disposed in the pixel electrode layer.
In some alternative embodiments, the array substrate includes a display region and a non-display region, and further includes: a second common electrode wiring in the gate layer and an electrode wiring in the source-drain metal layer are arranged, the second common electrode wiring is arranged in the non-display region,
the electrode wiring electrically connects each row of common electrodes and electrically connects the second common electrode line via a via hole penetrating to the gate layer.
In some alternative embodiments, the driving circuit layer further includes: thin film transistors arranged in one-to-one correspondence with the pixel electrodes,
the thin film transistor includes: and a source electrode and a drain electrode disposed in the source-drain metal layer, the pixel electrode being electrically connected to the source electrode or the drain electrode through a via hole penetrating to the source-drain metal layer.
A second aspect of the present disclosure provides a display panel, including:
the array substrate according to the above; and
and the electronic paper layer is arranged on the array substrate.
A third aspect of the present disclosure provides a method of fabricating the array substrate described above, comprising:
providing a substrate;
a driving circuit layer is formed on a substrate base plate,
the first antennas are formed in the gate layer through a one-time patterning process, and the second antennas are formed in the source-drain metal layer through a one-time patterning process.
The beneficial effects of the present disclosure are as follows:
the array substrate, the manufacturing method thereof and the display panel are formulated aiming at the existing problems at present, and the first antenna arranged along the first direction and the second antenna arranged along the second direction are respectively arranged in the grid layer and the source drain metal layer in the driving circuit layer, so that the electromagnetic touch control is integrated in the plane of the array substrate, the pixel aperture ratio is not influenced, the signal wiring of the array substrate does not occupy the peripheral wiring space, the narrow frame design is facilitated, and the array substrate has wide application prospect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram showing the basic structure of a conventional electronic ink screen;
FIG. 2 is a schematic diagram showing a touch layout of an array substrate according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of signal traces of an array substrate according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram showing signal traces of an array substrate according to another embodiment of the disclosure;
FIG. 5 illustrates a partial enlarged view of an array substrate according to an embodiment of the present disclosure;
fig. 6 illustrates a cross-sectional view of the array substrate taken along line AA' in fig. 5;
fig. 7 illustrates a cross-sectional view of the array substrate taken along line BB' in fig. 5;
FIG. 8 illustrates an overall layout trace of an array substrate according to an embodiment of the present disclosure;
FIGS. 9-13 are process flow diagrams illustrating fabrication of an array substrate according to one embodiment of the present disclosure;
fig. 14 shows a schematic view of a display substrate according to an embodiment of the disclosure.
Detailed Description
In order to more clearly illustrate the present disclosure, the present disclosure is further described below in connection with the preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons of ordinary skill in the art that the following detailed description is illustrative and not restrictive, and should not be taken as limiting the scope of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items.
As used herein, "on … …," "formed on … …," and "disposed on … …" can mean that one layer is formed directly on or disposed on another layer, or that one layer is formed indirectly on or disposed on another layer, i.e., there are other layers between the two layers. In this document, unless otherwise indicated, the term "in the same layer" is used to mean that two layers, components, members, elements, or portions may be formed by the same patterning process, and that the two layers, components, members, elements, or portions are generally formed of the same material.
In addition, in this disclosure, the term "co-layer arrangement" is used to refer to two layers, components, members, elements or portions that may be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements or portions are generally formed of the same material. For example, the two or more functional layers are arranged in the same layer, meaning that the functional layers arranged in the same layer may be formed using the same material layer and the same manufacturing process, so that the manufacturing process of the display substrate may be simplified.
To solve at least one of the above problems, an embodiment of the present disclosure discloses an array substrate including a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer including a gate layer and a source drain metal layer,
the array substrate further includes: a plurality of first antennas arranged along a first direction, and a second antenna arranged along a second direction perpendicular to the first direction and electrically isolated from the first antennas,
the first antenna is arranged in the grid electrode layer, and the second antenna is arranged in the source-drain metal layer.
In the embodiment, the first antenna arranged along the first direction and the second antenna arranged along the second direction are respectively arranged in the gate layer and the source-drain metal layer in the driving circuit layer, so that the electromagnetic touch control is integrated in the plane of the array substrate, the pixel aperture ratio is not influenced, the signal wiring of the array substrate does not occupy the peripheral wiring space, and the narrow frame design is facilitated.
In addition, in the embodiment of the disclosure, by providing the array substrate with the electromagnetic touch integrated in the driving circuit layer, when the array substrate is combined with the electronic paper film to form the electronic ink screen display panel, lighter and thinner product design can be realized, and meanwhile, more sensitive touch experience, finer and cleaner handwriting, higher response speed and unique suspension positioning function of the electromagnetic touch are provided for a user; meanwhile, unlike an LCD magnetic touch display panel, since the electronic ink screen display panel is not a backlight display mode, when the magnetic touch layer is integrated inside the array substrate, there is no influence on the pixel aperture ratio.
For a better understanding of the specific structural and functional effects of the embodiments of the present disclosure, a detailed structural description is made below with specific examples in conjunction with the accompanying drawings.
Referring to fig. 2, the array substrate includes: the semiconductor device includes a substrate 100 and a driving circuit layer disposed on the substrate 100, the driving circuit layer including a gate layer and a source drain metal layer. A top view of the array substrate is exemplarily shown, and the largest box represents the substrate 100, and the driving circuit layer is not specifically shown for brevity.
The array substrate comprises a plurality of first antennas X arranged along a first direction 1 、X 2 、…、X m And arranged along the second direction and in contact with the first antenna X 1 、X 2 、…、X m Electrically isolated second antenna Y 1 、Y 2 、…、Y n-1 And Y n The second direction is perpendicular to the first direction. Wherein, m and n are positive integers greater than or equal to 2, and the values of m and n can be equal or different.
In this example, the first direction is the X direction, and the second direction is the Y direction. The disclosure is not intended to be limited, however, the first direction may also be the Y direction and the second direction may also be the X direction, with the particular direction depending on the routing directions in the source drain metal layer and the gate layer.
First antenna X 1 、X 2 、…、X m And a second antenna Y 1 、Y 2 、…、Y n-1 And Y n Is a sensing antenna. The electromagnetic pen comprises an inductor (L) and a capacitor (C) inside and emits a high-frequency oscillation signal, the electromagnetic pen contacts the surface of the display panel to form a high-frequency LC oscillation circuit to generate a high-frequency variable electromagnetic field, and the first antenna X in the embodiment of the disclosure 1 、X 2 、…、X m And a second antenna Y 1 、Y 2 、…、Y n-1 And Y n The interaction with the electromagnetic pen is based on Faraday electromagnetic induction principle, when a high-frequency changing magnetic field generated by the electromagnetic pen passes through the two antennas, induced electromotive force is generated in a closed loop of the antennas, the magnetic field intensity of the electromagnetic pen is different at different distances, the intensity of the corresponding first antenna and second antenna in an overlapping area on the substrate is strongest, and the position of the electromagnetic pen is determined by reading the intensity of a sensing signal through the antennas, so that the electromagnetic signal sensing function is realized.
In particular, a first antenna X 1 、X 2 、…、X m A second antenna Y arranged in the gate layer 1 、Y 2 、…、Y n-1 And Y n Is arranged in the source-drain metal layer.
It should be noted that the present disclosure is not intended to limit the first antenna X 1 、X 2 、…、X m And a second antenna Y 1 、Y 2 、…、Y n-1 And Y n Is a vertical positional relationship of (a). That is, which of the two is located in the gate layer and which is located in the source-drain metal layer is not limited.
In embodiments of the present disclosure, the first antenna X is arranged with two metal layer gate layers and source drain metal layers that are also separately provided 1 、X 2 、…、X m And a second antenna Y 1 、Y 2 、…、Y n-1 And Y n The additional touch control layer is not required to be separately manufactured above the array substrate, the thickness of a display product is reduced, and the grid electrode and the signal line in the grid electrode layer and the manufacturing source can be manufacturedThe source electrode and the drain electrode in the drain metal layer and the signal line are synchronously manufactured, so that additional process and mask plate quantity are not needed, and the process cost is reduced.
The sensing principle of electromagnetic touch control is electromagnetic induction, so the first antenna X 1 、X 2 、…、X m And a second antenna Y 1 、Y 2 、…、Y n-1 And Y n An antenna that is substantially electromagnetically inductive is, therefore, practically any antenna structure that can transmit and receive electromagnetic signals and generate electromagnetic induction is sufficient. That is, it is also possible that the first antenna and the second antenna are each one metal wire.
However, in consideration of signal transmission and signal reception efficiency of the antennas, it is preferable to refer to the first antenna X as shown in fig. 2 1 、X 2 、…、X m A second antenna Y, which is a loop coil formed by at least two first conductive parts 1 、Y 2 、…、Y n-1 And Y n Loop coil formed by at least two second conductive parts.
Specifically, referring to fig. 2, the array substrate includes a display area AA and a non-display area NA, and further includes a first common electrode signal line Vcom1 at least partially surrounding the display area AA, the first common electrode signal line Vcom1 being disposed in the gate layer. Each first antenna X 1 、X 2 、…、X m The first end of the first conductive part of (a) is connected in parallel, and the second end is electrically connected with the first common electrode signal line Vcom 1; each second antenna Y 1 、Y 2 、…、Y n-1 And Y n The first end of the second conductive part of (a) is connected in parallel, and the second end is electrically connected to the first common electrode signal line Vcom 1. In this way, each first antenna forms a loop coil and each second antenna also forms a loop coil.
Optionally because of the first antenna X 1 、X 2 、…、X m And a second antenna Y 1 、Y 2 、…、Y n-1 And Y n By the gate electrode layer and the source drain metal layer, and needs to be arranged in the display area AA to perform the electromagnetic touch function of the display screen,the gate layer and the source/drain metal layer are typically wiring layers of the scan signal line and the data signal line, and for convenience of wiring, the first conductive portion is a straight line segment extending along the second direction Y and crossing the display area AA, and the second conductive portion is a straight line segment extending along the first direction X and crossing the display area AA.
In addition, it should be noted that, fig. 2 shows that each loop coil includes four conductive portions, but it is merely illustrative, and the number of conductive portions may be set according to the need in practical application. It should be understood that, the more conductive parts are disposed in each loop coil, the more sensitive the touch position detection is, but correspondingly, the lower the accuracy of the actual touch position detection is due to the larger area occupied by the intersecting positions of the first antenna and the second antenna. On the other hand, a second antenna Y is provided 1 、Y 2 、…、Y n-1 In principle, the larger the number of m and n, the higher the detection accuracy needs to be in consideration of the wiring space.
Specifically, with continued reference to fig. 2, the array substrate further includes: a plurality of first sensing wires and a plurality of second sensing wires, wherein the first sensing wires are arranged in the grid electrode layer, and the second sensing wires are arranged in the source-drain metal layer. The first sensing wires are connected with the first ends of the first antennas in a one-to-one correspondence manner, the second sensing wires are connected with the first ends of the second antennas in a one-to-one correspondence manner, and can be electrically connected to an external PCB (printed Circuit Board) through the switching of a flexible circuit board electrically connected with the array substrate, and the touch control chip on the external PCB receives detection signals and transmits the detected detection signals to the touch control chip so as to determine the specific electromagnetic touch control position through the analysis of the touch control chip.
In the embodiment of the present disclosure, because the touch layer is disposed in the same layer as the gate layer and the source drain metal layer, the first sensing trace and the second sensing trace need to be disposed in the non-display area, in order to implement the narrow frame arrangement and also in order to provide the second sensing trace with an equal amount of space to improve the sensing accuracy, preferably, the embodiment of the present disclosure further optimizes the routing manner of the scanning signal line and the data signal line.
Referring to fig. 3, the array substrate includes a first wiring region, a display region AA, and a second wiring region sequentially distributed along a second direction Y. One or more driving chip ICs may be bound in the first wiring region and used to arrange the driving chip ICs to fan-out lines of the display region AA to provide various driving signals. The second wiring area is used to arrange various sense lines shown in fig. 2, or other wiring that requires input or output signals with an external PCB circuit board. Note that since the wiring pattern does not involve the second wiring area, the FPC portion located below is omitted accordingly.
The array substrate further includes: a plurality of scanning signal lines V arranged in the first direction X and arranged in the display area AA Gate And a plurality of data jumpers Vd ata1 The method comprises the steps of carrying out a first treatment on the surface of the And a plurality of data signal lines Vdata disposed in the display area AA and arranged in the second direction Y, the data signal lines also being referred to as Source signal lines. Wherein, scan signal line VGate and data jumper line V data1 A data signal line V arranged in the gate layer data A data signal line V arranged in the source-drain metal layer data The data jumpers Vdata1 are electrically connected in a one-to-one correspondence by vias (see dark grey dots in the figure) that pass through to the gate layer.
In this way, the data signal lines V arranged in the second direction Y data The wiring to the driver chip IC is no longer required by occupying the left and right frames, thereby saving frame space, which is particularly advantageous for display panels with high pixel resolution.
In other alternative embodiments, a narrow bezel design may also be implemented by skipping gate scan signal lines. Fig. 4 shows such a wiring example, and in order to ensure uniformity of directions in the drawings of the specification, the orientation of the array substrate is adjusted in fig. 4.
Referring to fig. 4, the array substrate includes a first wiring region, a display region AA, and a second wiring region sequentially distributed along a first direction X. The array substrate further includes: a plurality of data signal lines V arranged in the second direction and arranged in the display area AA data And a plurality of scanning jumpers V Gate1 The method comprises the steps of carrying out a first treatment on the surface of the Is arranged in the display area AA and alongA plurality of scanning signal lines V arranged in the first direction X Gate . Wherein the data signal line V data And scanning jumper V Gate1 A scanning signal line V arranged in the source-drain metal layer Gate Arranged in the grid layer, scanning jumper V Gate1 Through the via hole penetrating to the gate layer and the scanned signal line V Gate And one-to-one corresponding electrical connection.
In this way, by scanning jumper V Gate1 Scanning jumper V for scanning signal lines arranged along second direction Y Gate The wiring led out to the first wiring area located above is no longer required to be arranged to the driving chip IC by occupying the left and right frames, thereby saving frame space, which is particularly advantageous for display panels with high pixel resolution.
In order to further understand the structure and routing relationship of the array substrate, a specific structure is described in detail below with reference to fig. 5 to 8. It should be noted that fig. 5 and 8 are specific structural views of the data signal jumper manner. It should be understood that when the array substrate is wired in a gate jumper manner as shown in fig. 4, the wiring directions of the gate layer and the source-drain metal layer are similar to those of fig. 5 and 8, and will not be repeated herein.
Referring to fig. 5, the pixel design on the array substrate, the relationship between each signal line, the first antenna, and the second antenna, and the pixel is shown in this structure.
As shown in fig. 5, the array substrate further includes: a plurality of pixel electrodes 108 arranged in an array, and a plurality of common electrodes 111 arranged corresponding to the pixel electrodes 108. The pixel electrodes 108 define pixel units of the electronic ink display panel, and each pair of the pixel electrodes 108 and the common electrode 111 is charged by a voltage applied thereto, and causes black and white electrophoretic particles in the electronic paper film to accumulate by the stored charges thereof to display a picture.
Wherein the common electrode 111 is disposed on the source/drain metal layer, and because it is disposed on the source/drain metal layer, so as not to be in contact with the data signal line V also disposed in the film layer data And a second antenna Y 1 、Y 2 、…、Y n-1 The common electrode 111 is in conflict with the pixel electrode 108 one by oneThe separation electrodes are correspondingly arranged, and the orthographic projection of the common electrode 111 on the substrate 100 falls within the pixel electrode 108. By the arrangement, the mask plate manufacturing process can be reduced, and the process flow is simplified.
With continued reference to fig. 5, the array substrate further includes an electrode trace disposed in the source-drain metal layer and a second common electrode trace Vcom2 disposed in the gate layer, wherein the second common electrode trace Vcom2 is disposed in the non-display area NA, the electrode trace connects the common electrodes 111 of each row together, and electrically connects the common electrode 111 with the second common electrode trace Vcom2 through a via hole penetrating to the gate layer. The common electrode 111 is charged by receiving a level signal acquired from the FPC by the second common electrode wiring Vcom 2.
In addition, the array substrate further includes a pixel electrode layer disposed on the driving circuit layer, and the pixel electrode 108 is disposed in the pixel electrode layer, as shown in fig. 6. The array substrate further includes thin film transistors T in one-to-one correspondence with the pixel electrodes 108. As shown in fig. 5 and 6, the thin film transistor T includes a gate electrode 101-1 designed in a gate layer and source and drain electrodes 104 provided in a source and drain metal layer, the gate electrode 101-1 and a scanning signal line V Gate Electrically connecting; one of the source and drain electrodes 104 and the data signal line V data Electrically connected to the pixel electrode 108, and when the thin film transistor T is responsive to the scan signal line V Gate When the control signal of (2) is turned on, the data signal line V data Is transferred to the pixel electrode 108 to charge it. As shown in fig. 6, the pixel electrode 108 is electrically connected to one of the source and drain electrodes 104 through a via CK penetrating to the source-drain metal layer. Wherein, referring to FIG. 7, the data signal line V data Data jumper V electrically connected by using via holes data1 And receives the data signal.
Referring to fig. 6, the driving circuit layer includes a thin film transistor T including a gate electrode 101-1, a gate insulating layer 102, an active layer 103, a source electrode and a drain electrode 104 sequentially disposed on a substrate 100. In addition, the driving circuit layer includes a resin layer 105, a first passivation layer 106, and a second passivation layer 107, which are sequentially stacked on the thin film transistor T. A light shielding layer 109 may be further included between the first passivation layer 106 and the second passivation layer 107.
Although a bottom gate thin film transistor is shown in the drawings, the present application is not limited to this, and a top gate thin film transistor may be used in practice. When the top gate thin film transistor is adopted, correspondingly, the gate layer is also located above the source-drain metal layer, and the description is omitted herein.
On the other hand, as shown in conjunction with fig. 5 and 8, the first antenna X 1 First conductive part of (a) and scanning signal line V Gate Data jumper V data1 Arranged in parallel with the first antenna X 1 Is arranged on a first side of a common electrode 111, a first antenna X 1 Is arranged on the second side of the common electrode 111 and is connected with another group of scanning signal lines V Gate Data jumper V data1 Are arranged in parallel. Similarly, a second antenna Y 1 And data signal line V data Arranged side by side, a second antenna Y 1 Is disposed on the third side of the common electrode 111, a second antenna Y 1 Is disposed on the fourth side of the common electrode 111.
As can be seen by referring to the overall diagram shown in fig. 8, the first antenna X 1 And a second antenna X 2 The first conductive portion and the second conductive portion are respectively arranged at two sides of a row of common electrodes 111, and the second antenna Y 1 And a second antenna Y 2 The first conductive portion and the second conductive portion of (a) are disposed on both sides of a row of common electrodes, respectively, so that the gate layer wiring and the source drain metal layer wiring can be realized without affecting the layout of the pixel cells. It will be appreciated that when a first antenna X 1 When four conductive portions are included, only the first antenna X in the present example is required 1 And X 2 The antenna is combined into one antenna, and the arrangement mode of the antenna formed by a plurality of conductive parts is similar and is not repeated here.
Corresponding to the array substrate, the embodiment of the disclosure further provides a method for manufacturing the array substrate, which comprises the following steps:
step S1, providing a substrate base plate;
step S2, forming a driving circuit layer on the substrate base plate,
the first antennas are formed in the gate layer through a one-time patterning process, and the second antennas are formed in the source-drain metal layer through a one-time patterning process.
In the embodiment, the first antenna arranged along the first direction and the second antenna arranged along the second direction are respectively arranged in the grid layer and the source-drain metal layer in the driving circuit layer, so that the electromagnetic touch control is integrated in the plane of the array substrate, the pixel aperture ratio is not influenced, the signal wiring of the array substrate does not occupy the peripheral wiring space, the narrow frame design is facilitated, and the application prospect is wide.
The method will be described in detail with reference to fig. 9 to 13 with a process flow for fabricating the cross-sectional structure of the array substrate shown in fig. 6.
In step S1, as shown with reference to fig. 9, a gate electrode 101-1 is formed on a provided substrate 100 through a one-time patterning process, the gate electrode 101-1 being disposed in a gate layer. Accordingly, the scanning signal lines V are simultaneously formed by the one-time patterning process Gate Data jumper Vdata1, and first antenna X 1 、X 2 、…、X m To form a gate layer.
Specifically, the material of the substrate base 100 is typically quartz glass. The gate 101-1 may have a multi-layered metal structure or a single-layered metal structure, and the film combination may be one selected from molybdenum/aluminum/molybdenum (Mo/AL/Mo), molybdenum/copper (Mo/Cu), molybdenum-niobium alloy/copper (MoNb/Cu), molybdenum-niobium alloy/copper/molybdenum-titanium alloy (MoNb/Cu/MoTi), or a stack thereof.
One or more buffer layers may also be deposited prior to forming the gate 101-1, but this layer need not be patterned.
In step S201, a gate insulating layer 102 is formed on the gate electrode 101-1, and an active layer 103 is formed through one patterning process. The gate insulating layer 102 may have one or more layers, and the material may be an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the layer may also require a patterning process. The material of the active layer 103 may be polysilicon (a-Si), and the doping type may be N-type doping or P-type doping.
In step S202, the source and drain electrodes 104 are then formed through a one-time patterning process. In this process, also formed simultaneously with the source and drain electrodes 104 are a common electrode 111, an electrode wiring connecting the common electrode 111, a data signal line V data And a second antenna Y 1 、Y 2 、…、Y m To form a source-drain metal layer.
Referring to fig. 11, in step S203, a resin layer 105 is formed on the source drain metal layer, and a mask plate is required to form a pattern in a patterning process.
Referring to fig. 12, in step S204, a first passivation layer 106 is formed on the resin layer 105, and a light shielding layer 109 is formed through a one-time patterning process. The material of the first passivation layer 106 is an inorganic material to block water vapor from entering the resin layer 105 and the underlying source drain metal layer. The material of the light shielding layer 109 is metal.
Referring to fig. 13, in step S205, a second passivation layer 107 is formed on the light shielding layer to form a driving circuit layer, and a mask plate is required to form a via pattern in a patterning process.
Then, the pixel electrode 108 is formed on the driving circuit layer through a one-time patterning process to form an array substrate.
Through the arrangement, the in-plane integrated magnetic touch layer can be formed by means of the 8-mask forming process of the conventional array substrate without additional patterning processes such as exposure and development, and the process flow is simple and the cost is low.
Based on the same inventive concept, the embodiment of the present disclosure further provides a display panel, as shown in fig. 14, including the above-mentioned array substrate and electronic paper film provided by the embodiment of the present disclosure.
Wherein the layer structure of the array substrate is simplified, only the data jumper V in the deposition substrate 100 and the gate layer is shown data1 And a resin layer. The electronic paper film includes: an adhesive layer 201, microcapsules 202, an ITO film 203, a polyester layer 204, and a protective film 205. Wherein the microcapsule comprises a plurality of electrophoretic particles, the plurality of electrophoretic particles comprise white screen particles and black screen particles, and the black screen particles are controlled by the voltage of the pixel electrode 108When the sub-aggregates are at the side of the microcapsule 202 close to the ITO film 203 and the black screen particles are away from the side, a white screen is displayed, whereas a black screen is displayed.
The display panel comprises the array substrate described in the above embodiment, so that the magnetic touch layer integrated in the driving circuit layer is realized, and the in-plane integrated magnetic touch function of the electronic ink screen is realized.
In the implementation, the display panel may be any product or component that may or may need to apply the electronic ink display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
The array substrate, the manufacturing method thereof and the display panel are formulated aiming at the existing problems at present, and the first antenna arranged along the first direction and the second antenna arranged along the second direction are respectively arranged in the grid layer and the source drain metal layer in the driving circuit layer, so that the electromagnetic touch control is integrated in the plane of the array substrate, the pixel aperture ratio is not influenced, the signal wiring of the array substrate does not occupy the peripheral wiring space, the narrow frame design is facilitated, and the array substrate has wide application prospect.
It should be apparent that the foregoing examples of the present disclosure are merely illustrative of the present disclosure and not limiting of the embodiments of the present disclosure, and that various other changes and modifications may be made by one of ordinary skill in the art based on the foregoing description, and it is not intended to be exhaustive of all embodiments, and all obvious changes and modifications that come within the scope of the present disclosure are intended to be embraced by the technical solution of the present disclosure.
Claims (11)
1. An array substrate comprises a substrate base plate and a driving circuit layer arranged on the substrate base plate, wherein the driving circuit layer comprises a grid electrode layer and a source-drain metal layer,
the array substrate further includes: a plurality of first antennas arranged along a first direction, and a second antenna arranged along a second direction and electrically isolated from the first antennas, the second direction being perpendicular to the first direction,
the first antenna is arranged in the grid electrode layer, and the second antenna is arranged in the source-drain metal layer.
2. The array substrate of claim 1, further comprising a display region and a non-display region, the array substrate further comprising: a first common electrode signal line at least partially surrounding the display region, the first common electrode signal line being disposed in the gate layer,
the first antenna is a loop coil formed by at least two first conductive parts, the first end of each first conductive part of the first antenna is connected in parallel, the second end is electrically connected with the first common electrode signal line,
the second antenna is a loop coil formed by at least two second conductive parts, the first ends of the second conductive parts of the second antenna are connected in parallel, and the second ends of the second antenna are electrically connected with the first common electrode signal line through a via hole penetrating to the grid layer.
3. The array substrate of claim 2, wherein the first conductive portion is a straight line segment extending in the second direction and crossing the display area, and the second conductive portion is a straight line segment extending in the first direction and crossing the display area.
4. The array substrate of claim 2, further comprising: a plurality of first sensing wires and a plurality of second sensing wires arranged in the non-display area, wherein the first sensing wires are arranged in the grid electrode layer, the second sensing wires are arranged in the source-drain metal layer,
the first sensing wires are connected with the first ends of the first antennas in a one-to-one correspondence manner, and the second sensing wires are connected with the first ends of the second antennas in a one-to-one correspondence manner.
5. The array substrate of claim 1, comprising a first wiring region, a display region, and a second wiring region sequentially distributed along the second direction, the array substrate further comprising:
a plurality of scan signal lines and a plurality of data jumper lines arranged in the display area and along the first direction; and
a plurality of data signal lines disposed in the display area and arranged along the second direction,
the scanning signal lines and the data jumper wires are arranged in the grid electrode layer, the data signal lines are arranged in the source-drain metal layer, and the data signal lines are electrically connected with the data jumper wires in one-to-one correspondence through holes penetrating through the grid electrode layer.
6. The array substrate of claim 1, comprising a first wiring region, a display region, and a second wiring region sequentially distributed along the first direction, the array substrate further comprising:
a plurality of data signal lines and a plurality of scan jumper lines arranged in the display region and arranged along the second direction; and
a plurality of scanning signal lines disposed in the display area and arranged along the first direction,
the data signal lines and the scanning jumper wires are arranged in the source-drain metal layers, the scanning signal lines are arranged in the grid electrode layers, and the scanning jumper wires are electrically connected with the scanning signal lines in one-to-one correspondence through holes penetrating through the grid electrode layers.
7. The array substrate of claim 1, further comprising: a plurality of pixel electrodes arranged in an array and a plurality of common electrodes arranged corresponding to the pixel electrodes,
the array substrate further includes a pixel electrode layer disposed on the driving circuit layer,
the common electrode is arranged on the source-drain metal layer, and the pixel electrode is arranged in the pixel electrode layer.
8. The array substrate of claim 7, comprising a display region and a non-display region, and further comprising: a second common electrode wiring disposed in the gate layer and an electrode wiring disposed in the source-drain metal layer, the second common electrode wiring being disposed in the non-display region,
the electrode wires electrically connect each row of the common electrodes and electrically connect the second common electrode wires via vias penetrating to the gate layer.
9. The array substrate of claim 7, wherein the driving circuit layer further comprises: thin film transistors arranged in one-to-one correspondence with the pixel electrodes,
the thin film transistor includes: and the pixel electrode is electrically connected with the source electrode or the drain electrode through a via hole penetrating to the source-drain metal layer.
10. A display panel, comprising:
the array substrate according to any one of claims 1 to 9; and
and the electronic paper layer is arranged on the array substrate.
11. A method of making the array substrate of any one of claims 1-9, comprising:
providing a substrate;
forming a driving circuit layer on the substrate base plate,
the first antennas are formed in the gate layer through a one-time patterning process, and the second antennas are formed in the source-drain metal layer through a one-time patterning process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202410006882.6A CN117766546A (en) | 2024-01-02 | 2024-01-02 | Array substrate, manufacturing method thereof and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410006882.6A CN117766546A (en) | 2024-01-02 | 2024-01-02 | Array substrate, manufacturing method thereof and display panel |
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| CN117766546A true CN117766546A (en) | 2024-03-26 |
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| CN202410006882.6A Pending CN117766546A (en) | 2024-01-02 | 2024-01-02 | Array substrate, manufacturing method thereof and display panel |
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| CN (1) | CN117766546A (en) |
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