CN117766484A

CN117766484A - Semiconductor package

Info

Publication number: CN117766484A
Application number: CN202311248583.5A
Authority: CN
Inventors: 唐和明; 卢超群
Original assignee: Quanxin Semiconductor Heterointegration Co ltd; Etron Technology Inc
Current assignee: Quanxin Semiconductor Heterointegration Co ltd; Etron Technology Inc
Priority date: 2022-09-26
Filing date: 2023-09-26
Publication date: 2024-03-26
Also published as: CN117766488A

Abstract

The application discloses a semiconductor package comprising: a processor die powered by the front-side or back-side power supply network; a plurality of memory dies and a control die stacked over the processor die; a plurality of high thermal conductivity HTC interconnects formed on, positioned between, and/or placed side-by-side with the die; an HTC substrate carrying all of the die; HTC structural members; and an HTC heatsink/heat spreader, wherein the die and the HTC heatsink are thermally coupled to other HTC components in the semiconductor package. The semiconductor components may be configured to override conventional single-sided interconnect and cooling topologies to enable double-sided or multi-sided cooling, power supply, and signaling.

Description

Semiconductor package

Priority claiming and cross-referencing

The present application claims the benefit of the U.S. provisional application of the prior application No. 63/409,854 of the application at 9, 26, 2022, the U.S. provisional application of the prior application No. 63/432,414 of the application at 12, 14, 2023, 9, and the U.S. provisional application of the prior application No. 63/583,008 of the application at 15, and is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package capable of enhancing heat dissipation of a 3D IC.

Background

Despite recent evolutions due to great achievements in engineering and material science, such as involving extremely complex multi-step lithographic patterning, new strain modifying materials and metal oxide gates, 2D geometry scaling of conventional transistors is rapidly approaching "red brick walls". Integration of 3D ICs (3D integrated circuits) presents a significant transition compared to traditional 2D IC and 2D package integration by vertically stacking ICs and/or transistor layers on a single interposer or substrate to provide extremely dense ICs. 3D ICs have been recognized as next generation semiconductor technology with the advantages of high performance, low power consumption, small physical size, and high integration density. 3D ICs provide a way to continuously meet the performance/cost requirements of offspring devices while maintaining a more relaxed gate length and lower process complexity.

Advanced SiP (system in package) including multiple active die, particularly with processors and memory, are often employed for high-end applications such as high-performance computing (HPC), data centers, artificial Intelligence (AI), and smart handsets to increase computing power within smaller form factors. The advanced SiP described herein includes the 2.5D IC shown in fig. 1A, the fan-out SiP shown in fig. 1B, the embedded SiP shown in fig. 1C, the silicon photons shown in fig. 1D, and the 3D IC shown in fig. 1E.

In fig. 1A, a 2.5D IC structure 90 includes a laminate substrate 901 supporting a silicon interposer 902 through a plurality of solder connections 903. The silicon interposer 902, commonly used in 2.5D IC packages and containing Through Silicon Vias (TSVs) 904, may be used as a platform to bridge the fine line and space (L/S) pitch fall between the laminate substrate 901 and the IC blocks covering 3D ICs, such as High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) stacks, i.e., memory structure 905 and processor IC 907 in fig. 1A. The silicon interposer 902 may possess passive and/or active ICs with different functions for different applications. In addition to memory devices, such as memory structure 905, and logic devices, such as processor 907, various other types of electronic components, including other types of active ICs, such as analog and mixed signal devices, MEMS (micro-electro-mechanical system) devices, and passive devices, may be mounted on the silicon interposer 902 produced by the wafer-level process. These electronic components may be arranged in the form of 2D ICs with die placed side-by-side, 2.5D ICs with multiple 3D memory structures 905 mounted side-by-side with the processor on an interposer (fig. 1A), or 3D IC packages with the processor mounted on the interposer and the memory structures 905 mounted on top of the processor. For example, the memory structure 905 in fig. 1A may be an HBM DRAM stack that includes a plurality of DRAM dies 905a vertically stacked over a base control die 905b by current copper pillar micro bumps or by future copper hybrid bond layers as the process matures. As shown in fig. 1A, a silicon interposer 902 is bonded over a laminate substrate 901 using micro bumps or solder bumps, while the laminate substrate 901 may be bonded to a printed circuit board PCB (not shown in the figures) by a plurality of Ball Grid Array (BGA) solder balls 906 underneath.

In FIG. 1B, a fan-out package structure 91 may be employed in which electrical connections on chips 913a and 913B fan out from the active surface of the chip to enable external I/O903 a to be placed outside the confines of the chip. The fan-out package structure 91 includes one or more semiconductor chips (e.g., chip 913a and chip 913 b) molded in a molding compound and allows individual chips to be connected to the fan-out wiring layer or redistribution layer (RDL) 911 and coupled with solder bumps 903a or, alternatively, with micro bumps to connect to the substrate 901, the substrate 901 may be a laminated substrate, interposer, or fan-out package structure bonded to a next level of substrate (e.g., PCB) using solder bumps or solder balls 906. In addition to the structure shown in fig. 1B, there are various other fan-out package structures including structures containing Through Mold Via (TMV, see fig. 2) and an appropriate surface coating formed on top of the TMV, either exposing the top Mold compound surface or connecting RDL 911 in fig. 1B to another RDL formed on top of the Mold compound to facilitate subsequent vertical mounting of another electronic component, such as a memory, on top of the fan-out structure. The highest capacity commercial fan-out package depicted in fig. 2 can be seen in smart handheld applications, where Application Processor (AP) die is embedded in a mold compound and DRAM packages are mounted on the fan-out structure.

In fig. 1C, an embedded SiP 92 includes one or more devices 923 embedded in a laminate substrate 901. The one or more devices 923 may be embedded silicon interconnects (which may be passive devices or active devices), active IC devices (e.g., DC-DC converters), or embedded passive devices (e.g., capacitors or inductors). Furthermore, the laminate substrate 901 with the device 923 embedded therein may be further bonded to another laminate substrate or PCB 908 by solder balls 906 or micro bumps, depending on the application. Embedded sips are typically implemented in conjunction with advanced sips that include a fan-out structure containing a die embedded in a molding compound (fig. 1B).

In fig. 1D, the silicon photonic structure 93 includes a CMOS die 916, a waveguide structure 918 having a modulator 919 and a photodetector 920 embedded therein, and an optical fiber 921 coupling optical signals into and out of the waveguide structure 918. The laser diode 917 and the waveguide structure 918 and components coupled to the waveguide structure are integrated over the silicon interposer 914 with TSVs. The silicon interposer 914 produced by the wafer level process may be configured to be mounted on a substrate (e.g., a laminate substrate) by a plurality of solder bumps or microbumps 903 for external connection.

In fig. 1E, the 3D IC-based structure 94 includes a first die 940 (in die form) and a second die 941 (also in die form). The first die 940 may be a processor die, while the second die 941 may contain a DRAM die or other type of memory device, such as SRAM. The second die 941 may be stacked on the first die 940 by a variety of suitable bonding techniques, including flip-chip and copper hybrid bonding. The 3D IC-based structure 94 allows the first die 940 (e.g., processor die) to access the second die 941 (e.g., memory die) in close proximity with the shortest data transfer time between processor and memory in all advanced sips (see fig. 1A-1E and fig. 2).

In the future, the number of 3D IC applications will steadily increase. It is expected that 3D ICs will find wide use in applications requiring "extreme" ultra-high performance, higher power efficiency devices, such as high performance computing and data centers (HPCs), AI (artificial intelligence)/ML (machine learning), 5G/6G networks, graphics, smart phones/wearable devices, automobiles, and others. These devices include CPU (central processing unit), GPU (graphics processing unit), FPGA (field programmable gate array), ASIC (application specific IC), TPU (tensor processing unit), integrated photonics, AP (handset application processor) and packet buffer/router devices.

To expedite adoption, 3D IC systems must be built on-the-fly via IC packaging system co-design involving silicon IP, IC/chiplet and IC packaging and addressing the attendant power and thermal challenges. In contrast to Performance, power, area, and Cost (PPAC) optimization for 2D packages per "square centimeter", the IC package system co-design of 3D ICs aims to achieve PPAC optimization for every "cubic millimeter", where the vertical dimensions that cover ICs, intermediaries, IC package substrates, IC packages, and system Printed Circuit Boards (PCBs) must now be considered in all trade-off decisions.

Commercial 3D ICs, such as 3D HBM DRAM memory stacks, are increasingly supported by commercial 2.5D ICs, such as the 2.5DIC structure 90 shown in fig. 1A, that contain through silicon vias (Through Silicon Via, TSVs) in both the active die and the silicon interposer. With proper heat dissipation solutions, 3D ICs may ultimately implement memory-on-memory, logic-on-logic using interconnect technologies such as TSV, RDL containing interconnect wiring and micro-vias, flip-chip bonding using copper pillar micro-bumps or solder bumps, and emerging copper hybrid bonding of Complementary Metal Oxide Semiconductor (CMOS) image sensors for inter-die communication as first demonstrated by Sony (Sony).

The 3D IC allows heterogeneous die vertical stacking from different fabrication processes and nodes, chip reuse, and microchip in SiP for high performance applications that have broken through the limitations of single die of the most advanced nodes. The 3D IC integration may be via 3D monolithic integration and/or vertical integration of different dies (as in the case of HBM DRAM stacks) or dies embedded in different packaging layers.

3D monolithic integration typically involves vertical integration of multiple active silicon layers and vertical interconnects between the layers. A monolithic 3D IC is built on vertical interconnects between multiple active silicon layers. It is still in an early development stage and has not been widely deployed. Recently, 3D IC architectures of "Central Processing Unit (CPU) overlay caching" have been presented and commercialized using copper hybrid bonding. Today, HBM DRAM stacks (each of which is created by vertically integrating several DRAM dies onto a control IC) represent the largest number of commercial 3D ICs today. The 3D IC is ideal for applications requiring more transistors to be stacked in a given device footprint, such as a system-on-a-chip SoC (e.g., the AP in fig. 2) for mobile applications and for other applications that have exceeded the single die limit at the most advanced node, such as HPCs, data centers, and AI.

Mobile devices, such as smartphones, face special thermal management challenges because only a small area can be used for heat dissipation and only a small space is available for implementing the heat dissipation solution, plus the heat generated in the mobile device is limited by a relatively low maximum allowable housing temperature, typically between 44 ℃ and 50 ℃.

Fig. 2 shows a current smart mobile application based on a Package-on-Package (PoP) structure 96. As shown in fig. 2, the DRAM package 931 is stacked on an Application Processor (AP) package 932 in the POP structure. The DRAM package 931 includes a DRAM die 9311 stacked on a laminate substrate 9312, a molding layer 9313 (e.g., a molding compound) that molds the DRAM die 9311, and solder balls 9314 formed on the laminate substrate 9312 that are vertically bonded to the AP package 932. The AP package 932 includes an AP die 9321, a molding layer 9322 that molds the AP die 9321, a plurality of TMVs 9323 formed in the molding layer 9322 and coupled to solder balls 931 of the DRAM package 931, and RDL 9324 formed on the AP 9321 and the molding layer 9322, and solder balls 9325 formed on the RDL 9324. In addition, poP structure 96 is mounted on PCB 933 by solder balls 9325 and heat spreader 934 is disposed over DRAM package 931 with Thermal Interface Material (TIM) 9381. The PoP structure 96 and PCB 933 are disposed inside the housing 935 of the smart mobile device under the display panel 936. To reduce interference, a protective screen 937 may be disposed over the heat spreader 934 with a Thermal Interface Material (TIM) 9382 and under the display panel 936 in order to protect the PoP structure 96. Furthermore, a gap filler 939 may be added between the PCB 933 and the housing 935 to fill the space in between the PCB 933 and the shield/housing.

In the smart mobile device structure shown in fig. 2, the heat generated by the AP die 9321 is dissipated primarily through the molded stacked die DRAM BGA package 931 mounted on top of the AP package 932 to the heat spreader 934 and then to the housing 935.

There is a higher thermal resistance from the hot spot of the AP die 9321 to the surface of the housing 935 (because the molding compound used in the molding layers 9313 and 9322 is effectively a thermal insulator) than the removal of heat from the surface of the housing 935 to the surrounding environment by natural convection and radiation, which is primarily dependent on the surface area of the mobile device. To control the housing temperature below its maximum allowable temperature, typically between 44 deg.c and 50 deg.c, which will result in the maximum AP power that the semiconductor package of fig. 2 can withstand being limited. For mobile devices whose space is valuable and where there is typically no space available for fans and fin heat sinks, heat dissipation from the AP package to the housing shown in fig. 2 is the primary heat dissipation means.

Driven by the continual explosive growth of application and data traffic, the AP power of mobile devices is expected to increase, thereby severely challenging the cooling limits of the PoP package structure shown in fig. 2. In addition, higher data traffic requires higher memory capacity to communicate with more powerful, higher power AP dies. To increase memory capacity while improving heat dissipation efficiency from the fan-out AP package to the housing, more DRAM die in die form (with control ICs on the bottom of the DRAM die as needed) may be stacked vertically or in package thickness on the AP package or better on the bare AP die (in 3D ICs) or high thermal conductivity interposer (in 2.5D ICs) than the stacked molded DRAM laminate package (as shown in fig. 2), it being understood that the laminate substrate used in the DRAM package and the mold compound used in both the DRAM package and the fan-out AP package are poor thermal conductors compared to the silicon substrate in the die.

3D DRAM stacks (e.g., wide I/O DRAM die or HBM DRAM die for HPC, data center and AI applications based mobile devices) provide lower power, higher bandwidth and higher density advantages than 2D DRAM packages mounted on PCBs. In a 3D DRAM stack, power per unit area may increase due to more die stacks, where adjacent dies in a vertical stack heat each other, and in the case of air cooling for mobile devices, bottom and middle level DRAMs typically have a limited heat dissipation path than die phases on their tops that are closer to a heat spreader or heat plate and heat sink. Both of these factors can cause the 3D device to overheat (as compared to 2D memory), with the bottom layer being hottest and the top layer being cooler. High temperatures in DRAM can lead to reduced performance and efficiency, especially when dynamic thermal management schemes are used to regulate DRAM bandwidth when temperatures become too high. Overheating may also cause device stalling (i.e., access being prohibited) and reliability issues. All electronic devices operate reliably within a specific temperature range. As more DRAM dies are vertically stacked on a processor, new thermal solutions are needed to mitigate the overheating effects associated with the lower DRAM dies and control ICs, which can be exacerbated, particularly when stacked directly on top of a higher power processor (e.g., an AP die or a processor in a 3D IC).

As the overheating effect is addressed using the new thermal management solutions disclosed herein, placing multiple DRAM dies (and control ICs) directly on top of the processor, whether it be an AP die or a processor for HPC, data center, and AI applications, not only helps increase memory capacity, but also helps reduce computation and memory bandwidth gaps. In the future, the rate of increase in processor speed will continue to exceed the rate of increase in DRAM memory speed. The growth index of the microprocessor is substantially greater than that of the DRAM, but each is exponentially increasing. As shown in fig. 3 (referenced Riselab from berkeley division, california university, usa), the interconnect bandwidth between processor and memory lags behind the processor performance gain. This results in a "memory wall" effect that underutilizes processor performance. Memory latency and bandwidth will continue to limit system performance while memory bandwidth will continue to lag the peak FLOP rate for high-end applications such as HPC, data centers, and AI, as shown in FIG. 3. This imbalance is also applicable to application processors and, although the industry is continually demanding higher computational performance, it has caused a significant bottleneck that is expanding each year.

Today, 2.5D ICs and 3D ICs (e.g., HBM DRAM stacks of mobile devices or similarly, wide I/O DRAM stacks) employ a single-sided packaging topology that contains single-sided cooling from the top side of the top IC and single-sided area electrical interconnects for power and signaling (e.g., from the bottom side of the bottom IC (e.g., control die in fig. 1A)) to the upper die, one die at a time. These package topologies are created, for example, by interconnect technologies including flip-chip assemblies, TSVs, and RDLs. In powering a 3D IC, a designer must consider all stacked die/packaging layers when designing a power supply network, with the die on top getting its power from the die below and the die on bottom getting its power from the 2.5D interposer (fig. 1A) or laminate substrate (fig. 1B and 2). The single-sided interconnects and single-sided cooling are not scalable because the 3D IC footprint (see, e.g., HBM stack in fig. 1E for a 3D IC or fig. 1A for a 2.5D IC) does not change as the number of dies in the stack increases. Single sided electrical interconnects and cooling pose stringent constraints on PPAC optimization for the 3D IC designer to propose the best design solution.

Disclosure of Invention

One aspect of the present disclosure provides a semiconductor package. The semiconductor package includes a first die and a first support. The first die has a front side and a back side. The first support is disposed directly below the first die and thermally coupled to the first die. The thermal conductivity of the first support is greater than the thermal conductivity of the first die.

Another aspect of the present disclosure provides a semiconductor package that allows for dual or multi-sided power and signaling as well as dual or multi-sided cooling. The semiconductor package includes a processor die, a plurality of memory dies, and a control die or a plurality of 3D memory stacks, a first High Thermal Conductivity (HTC) structure, and a plurality of other HTC structures. The processor die has a front side and a back side. The first HTC structure is disposed directly below the processor die and is thermally coupled to the processor die. The thermal conductivity of the first HTC structure is greater than the thermal conductivity of the processor die. The memory die and the control die are stacked over the processor die. The plurality of other HTC structures are disposed between the processor die and control die, disposed between adjacent vertically stacked memory dies, placed side-by-side with the dies, and/or created on the dies as integrated portions of these dies in the semiconductor structure. Each of the thermal conductivities of the plurality of other HTC structures is greater than a thermal conductivity of the processor die.

Drawings

A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the figures, wherein like reference numbers refer to similar elements throughout the figures.

Fig. 1A to 1E each illustrate an advanced SiP structure.

Fig. 2 shows a smart mobile application using a stacked package structure.

Fig. 3 shows bandwidth scaling through different generations of interconnects and memory and peak-per-second floating point operations (flow) of a processor.

Fig. 4 shows a semiconductor package according to one embodiment of the present disclosure.

Fig. 5A-5D show detailed interface structures in the semiconductor package in fig. 4.

Fig. 6A-6E show fabrication operations for constructing the semiconductor package in fig. 4.

Fig. 7 shows a semiconductor package including a 3D IC structure according to an embodiment of the present disclosure.

Fig. 8A-8F show fabrication operations for constructing the semiconductor package in fig. 7, according to embodiments of the present disclosure.

Fig. 9A-9D illustrate a process for creating an advanced interposer or IC using a full-size reconstituted diamond wafer, according to some embodiments of the disclosure.

Fig. 10A-10D illustrate a process for creating advanced ICs using full-size reconstituted diamond-based double wafers, according to some embodiments of the disclosure.

Fig. 11A-11D illustrate a process for creating an advanced IC using full-size recombinant silicon-diamond-silicon wafers, according to some embodiments of the present disclosure.

Fig. 12A and 12B illustrate exemplary advanced ICs and advanced intermediaries that may be created from a full-size diamond-based composite wafer according to embodiments of the disclosure.

Fig. 13 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 14 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 15 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 16 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 17 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 18 shows a semiconductor package including a 2.5D IC structure according to another embodiment of the present disclosure.

Fig. 19 shows a semiconductor package including a 2.5D IC structure according to another embodiment of the present disclosure.

Fig. 20 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 21 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 22 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 23 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 24A-24C provide fabrication operations for forming a processor-diamond combination with a BSPDN, according to some embodiments of the present disclosure.

Fig. 25 provides a fabrication operation for forming a thermal insulating layer and/or a heat dissipation layer in a semiconductor package according to some embodiments of the present disclosure.

Fig. 26 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 27 shows a semiconductor package including a 3D IC structure according to another embodiment of the present disclosure.

Fig. 28 shows a semiconductor package including a 2.5D IC structure according to another embodiment of the present disclosure.

Fig. 29 shows a semiconductor package including a 2.5D IC structure according to another embodiment of the present disclosure.

Fig. 30 shows a semiconductor package including a 2.5D IC structure according to another embodiment of the present disclosure.

Fig. 31 shows a semiconductor package including a 2.5D IC structure according to another embodiment of the present disclosure.

Fig. 32 shows a semiconductor package including a 2.5D IC structure according to another embodiment of the present disclosure.

Detailed Description

The following description accompanies the drawings, which are incorporated in and form a part of this specification and illustrate embodiments of the present disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments may be suitably integrated to complete another embodiment.

References to "one embodiment," "an exemplary embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment of the disclosure described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, although it may.

In order that the present disclosure may be fully understood, detailed steps and structures are provided in the following description. It will be apparent that embodiments of the present disclosure are not limited to the specific details known to those of ordinary skill in the art. In other instances, well-known structures and steps have not been described in detail so as not to unnecessarily obscure the present disclosure. Preferred embodiments of the present disclosure will be described in detail below. However, the present disclosure may be widely practiced in other embodiments besides the detailed description. The scope of the present disclosure is not limited to the detailed description, but is defined by the claims.

Methods, processes, and structures are disclosed for creating 3D and 2.5D IC interconnect structures containing Front side power supply networks (Front-side Power Delivery Network, FSPDN) or Back side power supply networks (Back-side Power Delivery Network, BSPDN), such that a combination of a jumped die or multi-sided electrical interconnect is achieved by using RDL, vias (e.g., TSV, TMV, diamond vias (Through Diamond Via, TDV, and/or Silicon-Diamond vias (TSDV)), high thermal conductivity (High Thermal Conductivity, HTC) supports, and HTC structural members (e.g., HTC interposer spacers, such as Diamond interposer spacers), these 3D ICs and 2.5DIC structures also enable dual-sided or multi-sided system-level cooling from the top side of the 3D IC, its bottom side in the 3D stack, and the chip side by using, but not limited to, RDLs, vias, HTC supports, HTC structural members (including HTC interposer spacers, such as Diamond interposer spacers), thermal insulation layers (including air gaps and thermal metamaterial structures), heat dissipation layers, heat sinks (or covers), and combinations of heat sinks: for liquid cooling applications, the heat sink may be a cooling plate and the heat sink may be a manifold). Semiconductor materials having a thermal conductivity greater than the die configuration used in the same semiconductor package are referred to as High Thermal Conductivity (HTC) materials. Although diamond is used as an example herein, other HTC materials are also contemplated. Among any known materials on earth, diamond possesses the highest thermal conductivity (about 2000W/m-K and higher TC), which is 5 times that of copper, at temperatures above about 100K, an extremely high breakdown field (about 20 MV/cm), and an extremely low coefficient of thermal expansion (about 1ppm/°c at room temperature). As in the case of the silicon interposer, diamond may be used to create a diamond interposer containing RDL (Redistribution Layer, RDL) and TDV (Through Diamond Via, TDV) using the processes disclosed herein. Diamond is therefore chosen here for illustration as it is a good quality material for heat dissipation of microelectronic devices.

In some embodiments, the HTC materials described herein may include other materials besides diamond, such as graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or combinations thereof, and the HTC substrates used to form the composite wafers may be composed of silicon, diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or combinations thereof.

The 3D ICs disclosed herein may contain ICs of the same, similar, or different sizes. ICs in 3D IC structures may contain active ICs in bare die form, ICs embedded in laminate substrates or molding compounds, various ICs in the same packaging layer, interconnect structures such as intermediaries (e.g., HTC supports) or intermediaries spacers (HTC structural members), discrete/passive or embedded passive elements, microelectromechanical (MEMS) devices, and other types of electronic components embedded. IC. The interposer and spacers may contain vias and RDLs on both the front side (BEOL) side of the IC and its bottom side. Embedding the IC, diamond interposer, and/or diamond plate with the mold compound also allows for creation of TMV within the mold compound, connecting RDLs on the top and bottom sides of the embedded IC structures in the stacked layers. Each stacked layer may include one or more ICs, and these ICs may be the same size or different sizes than other stacked layers in the 3D IC structure. Even though 3D IC and 2.5D IC structures are used in the illustration, the methods, processes and structures may be applied to other viable advanced System In Package (SiP) including fan-out embedded SiP, silicon photons and combinations thereof, including what is illustrated in fig. 1A-1E, particularly when SiP is used to incorporate various dies in the package thickness direction (z-direction).

Using a 3D IC as an example, fig. 4 shows a semiconductor package 10 according to one embodiment of the present disclosure. Semiconductor package 10 includes dies 101 and 102, each of which contains a FSPDN, an HTC support 103, an HTC structural member 1501, an HTC heat sink, and a heat sink 1503. In some embodiments, die 101 may be a processor die or a logic die, and die 102 may be a memory die, such as a DRAM die or a Static Random Access Memory (SRAM) die, which may also include control dies as desired. As shown in fig. 4, die 101 and 102 may have the same dimensions for exemplary purposes herein (which may also have different dimensions) and may be embedded in a molding compound over support 103. In particular, the memory die and the control die 102 may be stacked over the processor die 101.

The HTC support 103 is disposed directly below the die 101 and is thermally coupled to the die 101. Further, the thermal conductivity of the support 103 is greater than that of the bare die 101; thus, heat generated by the die 101 may be dissipated downward through the HTC support 103, the HTC support 103 outperforming a Low Thermal Conductivity (LTC) support, such as a laminate substrate or PCB.

The support 103 comprises an HTC interposer comprised of a material having a thermal conductivity greater than that of the die 101, the support 103 may be comprised of silicon or other suitable HTC material that may be built by micro-processing, for example. In some embodiments, the support 103 may be composed of HTC materials, including diamond, silicon, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or combinations thereof. The support 103 may be, for example, a diamond interposer containing RDLs and TDVs on its top and bottom sides, which may be implemented using a full-sized (diameter 12 ") reconstituted diamond wafer and the process described in fig. 9A-9D. Further, the support 103 may be constructed using a full-sized (e.g., diameter 12 ") recombinant silicon-diamond composite wafer (e.g., a double wafer or a three wafer) or the process shown in fig. 10A-10D or fig. 11A-11D. Which includes a diamond portion 1301 and a silicon portion 1032, and in which a silicon-diamond through hole (TSDV) 1033 may be formed. Depending on the application, TSDV 1033 may be used as a power via, a signal via, an optical via, and/or a thermal via. The support 103 may further be mounted on an organic laminate substrate 1401 or PCB by solder bumps 1201 as shown in fig. 4.

In addition, HTC support 103 may have a cross-sectional width that is greater than a cross-sectional width of die 101 such that HTC structural members 1501 may be disposed on support 103 side-by-side with dies 101 and 102 and thermally coupled to support 103 (see fig. 4). The structural member 1501 includes an intermediate layer spacer 1511 composed of an HTC material having a thermal conductivity preferably greater than silicon. For example, the spacer 1511 may be an HTC interposer, such as a diamond interposer with dies 101 and 102 and disposed at each stacked layer. These HTC spacers 1511 allow thermal energy generated by the dies 101 and 102 in each stacked layer to spread laterally in each stacked layer and support 103 to dissipate in an upward direction to the heat sink 1503 and in a downward direction to the support 103. In some embodiments, the spacers 1511 referred to herein may also be silicon intermediaries. In some embodiments, the spacers 1511 (and other elements of the structural member 1501) may be composed of HTC materials, including diamond, silicon, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or combinations thereof. HTC spacers 1511 may be a diamond interposer with TDV containing RDLs on its top and bottom sides or a silicon-diamond interposer with TSDV containing RDLs on its top and bottom sides, i.e., HTC supports 103.

In addition to the power and signal transfer manner of one die at a time of a conventional 3D IC, semiconductor package 10 also enables power and signal transfer manners across dies or multiple sides, such as from substrate to processor, then from processor to control IC, and then from control IC to bottom DRAM die, one die at a time, and so forth. For example, the skip-through die design allows power and signals to be transferred from die 101 to die 102 located at the top of die 102 by utilizing appropriate paths involving spacers 1511, vias (e.g., TSVs in the die, TDVs or TSDVs 1521 in the spacer 1511, and/or TMVs (not shown)), RDLs, and flip-chip or copper hybrid bonding while bypassing die 102 located at the bottom of die 102.

Furthermore, semiconductor package 10 enables double-sided or multi-sided cooling of the 3D IC structure such that logic die 101 (which may be a high power processor) is capable of (1) heat dissipation from the top side of the 3D IC structure (e.g., top memory die 102) to heat sink 1503 and (2) from the bottom side of the 3D IC structure (i.e., from logic die 101) down to HTC support 103 (e.g., a silicon-diamond interposer) and then up to spacers 1511 and structural members 1501 placed alongside the IC to heat sink 1503.

Heat sink 1503 is disposed over die 101, 102 and structural member 1501. The heat sink 1503 may include an HTC Thermal Interface Material (TIM) or HTC layer 1503A (e.g., made of diamond), an HTC cap (e.g., made of copper), a thermally conductive plate cavity or HTC integrated heat sink 1503B, and an HTC heat sink 1503C (e.g., fin or planar heat sink). In some embodiments, HTC structural member 1501 may further include vertical shelf 1516 thermally coupled to heat sink 1503 and support 103. The vertical shelf 1516 may be made of HTC material, such as the same material as the lid 1503B, such that heat transferred to the HTC support 103 may be dissipated upward toward the lid 1503B not only through the spacer 1511 but also through the vertical shelf 1516, thereby further improving cooling efficiency. Additionally, in some embodiments, lid 1503B may be thermally coupled to HTC layer 1503A and integrated with HTC layer 1503A by using a TIM or suitable bonding layer, as desired, and heat sink 1503C may also be thermally coupled to lid 1503B and HTC layer 1503A and integrated with lid 1503B and HTC layer 1503A by using a TIM or suitable bonding layer, as desired. However, the present disclosure is not limited thereto.

In some embodiments, heat sink 1503 may be an integrated heat sink that is a metal cover of a processor package. It may act as a protective shell around the processor and may also act as a path for heat exchange between the processor and the heat sink. In this case, the integrated heat sink may be attached to the back side of the processor by a TIM (e.g., a heat sink paste). An integrated heatsink is a combination of a typical rectangular heatsink ring joined to a substrate (e.g., support 103 or a laminate substrate) that supports and encloses a processor to protect the processor, and a planar heatsink placed on top of the rectangular heatsink ring. The HTC layer 1503A or the integrated heat sink 1503 may optionally be disposed (e.g., using direct bonding or bonding involving a bonding layer, see fig. 5A-5D) on the top die 102 and on the top spacer 1511 to achieve direct thermal and/or physical contact with the top die 102 and the top spacer 1511. In some other embodiments, the components of the heat sink 1503 may further comprise a metal cover, a heat guide plate, a cooling plate, a manifold, or a combination thereof.

In this embodiment, an HTC layer 1503A (e.g., HTC diamond plate) disposed between a cover 1503B and the top die 102 and top spacers 1511 in a 3D IC structure may cover the interior of the cover 1503B, wherein the area of the cover 1503B may be many times larger than the underlying 3D IC structure for enhanced heat dissipation.

With respect to heat sink 1503, copper heat sinks may provide better thermal performance than aluminum heat sinks. Copper heat conductive plates are planar heat pipes of a two-phase device that are in contact with a thermal chip, comprising an evaporator, a vacuum sealed heat conductive plate containing a working fluid, such as water, that transfers heat from the evaporator to the condenser, and a condenser that condenses and dissipates heat from the vapor therein to return liquid to the evaporator. The low pressure in the room allows water to vaporize at a much lower temperature than the normal boiling temperature (i.e., 100 ℃), thereby creating an isothermal radiator. The heat guide plate may be formed according to the size of the electronic device to be cooled, and the vapor chamber may dissipate heat in two dimensions, with a thickness of typically 1 to 5mm. It can be used to form the heat sink 1503 instead of solid copper to improve heat dissipation performance by 90 times. The effective thermal conductivity of the thermally conductive plate is estimated to be between 5000 and 20,000 w/m-K, which is much better than the most thermally conductive material on earth (i.e., diamond). The heat guide plate may draw heat from a heat source to a heat sink placed at a remote location (150 mm apart) with space to house the heat sink and a cooling medium (e.g., air or liquid). Bonding the thermally conductive plate to the base of the heat sink or the rear cover of the mobile device is particularly effective when there is a small and concentrated heat source to the upper large heat sink base. When the power density is high (i.e., at 20W/cm ² To 500W/cm ² Between) the heat exchanger plates are particularly effective for cooling applications. In these applications, it is often important to be able to spread heat rapidly to a large surface area.

Fig. 5A to 5D show detailed structures of interfaces 1 to 4 in the semiconductor package 10 in fig. 4, in which the spacer 1511 and the support 103 are constructed using diamond as an illustrative substrate material. The process for forming the RDL and TDV on both the diamond interposer and its top and bottom sides can be seen in fig. 9A-9D, while the process for forming the RDL and TSDV on both the silicon-diamond interposer and its top and bottom sides can be seen in fig. 10A-10D and 11A-11D. An interface 1 between the support 103 and the spacer 1511 is shown in fig. 5A, created by a copper hybrid bond between a bonding layer 1514 on the diamond portion 1512 of the spacer 1511 and a bonding layer 1035 on the diamond portion 1031 of the silicon-diamond support 103. Surface layers 1513 and 1034 are optional layers that form chemical bonds with diamond and may be deposited by Physical Vapor Deposition (PVD), such as sputtering on spacers 1511 and support 103, including titanium (Ti), silicon (Si), or tungsten (W) layers. In some embodiments, the respective surface bonding layers 1035 and 1514 on the support 103 and the spacer 1511 may be part of a redistribution layer (RDL) on the support 103 and the spacer 1511, and the support 103 and the spacer 1511 may be bonded by bonding pads 1036 on the RDL of the support 103 with bonding pads 1515 on the RDL of the spacer 1511, which may be performed using a Non-Conductive Paste or film (NCP) and in a manner that the microbumps use copper hybrid bonding or flip-chip bonding. Further, the spacer 1511 may include a TDV 1521 and the support 103 may include a TSDV 1033, as shown in fig. 4, such that signals, power, and heat may be transmitted across a die, a double-sided, or a multi-sided manner. Bonding a die, such as die 101, to support 103 involves a process and structure similar to that used to form interface 1 (fig. 5A). This process and structure may also be applied to die-to-die (e.g., die 102-to-die 101 and die 102-to-another die 102) bonding to form the 3D structure in fig. 4. In some embodiments, bonding the spacer 1511 to the IC may also be accomplished using the structures and related processes described in forming interface 1 in fig. 5A, and replacing die 102 with a spacer such as in fig. 4.

The copper hybrid bond may be based on, for example, silicon dioxide (SiO ₂ ) To SiO ₂ Bonding or Polyimide (PI) to PI bonding. The direct oxide-to-oxide bonding may be performed in the following process sequence: (1) Planarizing the joining surface to an arithmetic or root mean square roughness of < 1 (or 0.5) nm, depending on the application; (2) Using, for example, N ₂ (Nitrogen)/O ₂ The gas of (oxygen)/Ar (argon) is activated by plasma to form dangling bonds; (3) Defect removal and surface wetting by deionized water cleaning; (4) By reacting two to three monolayers of water molecules with polar hydroxyl (OH) groups (which terminate in natural and thermal SiO ₂ ) Hydrogen bonding to bond wafers containing oxide bonding layers (e.g., spacers 1511 and supports 103) at room temperature and atmospheric pressure; (5) Is connected at the top and the bottomH on the combined surface ₂ O molecule and silanol group (Si-OH- (H) ₂ O) x-HO-Si; silanol=si—oh) to form van der Waals bonds; and (6) annealing to remove water molecules at the interface and form permanent covalent bonds at temperatures typically less than 400 ℃ (preferably less than 250 ℃). It is also important to control the recess of the bond pad (typically a copper bond pad) during the planarization step (1) to ensure high copper hybrid bond yields. Regarding oxide-to-oxide bonding, manufacturers can vary oxide type and deposition techniques, process conditions (e.g., plasma gas, plasma power, surface roughness with respect to Chemical-mechanical polishing (Chemical-Machanical Polishing, CMP), surface cleanliness, single layer to multiple layers of water molecules in the deionized cleaning), bonding conditions (e.g., temperature, speed, and pressure), and annealing conditions (e.g., annealing temperature, annealing time, and number of annealing steps) to maximize bonding or shear strength between two components being bonded (e.g., spacer 1511 and support 103). Void generation due to water droplet formation (Joule-thomson) at the wafer edge during direct bonding must be avoided by controlling critical parameters including plasma conditions, surface roughness, cleanliness, wafer warpage/flatness, bonding conditions, etc.

In addition to oxide-to-oxide bonding, polyimide-to-polyimide (polyimide-to-polyimide) bonding, for example, based on fully cured polyimide of pyromellitic dianhydride (Pyromellitic Dianhydride, PMDA) and 4,4 '-diaminodiphenyl ether (4, 4' -ODA) to form the bonding layer may also be considered to achieve copper hybrid bonding in applications where external pressure may be applied as desired. In this case, the conditions (e.g., volume of introduced water, joining time, and oxygen (O) ₂ ) Plasma activation time) to adapt the shear strength to maximize the shear strength between the support 103 and the spacer 1511. To achieve void-free PI to PI bonding, it is important to activate the PI surface by oxygen plasma activation to produce low density hydrophilic groups on the PI surface, which effectively enhances the adsorption of water molecules introduced by the deionized water wetting process. The adsorbed water molecules in turn bring about a relatively high density O that promotes pre-bondingH group (hydroxy). After PI surface activation and wetting, PI-to-PI hybrid bonding can be experienced for a few minutes at a relatively low temperature of 250 ℃ only when a permanent bond is required. No good bonding can be achieved by plasma processes alone, wetting or hydration processes. Key parameters that can be manipulated to achieve good bonding include plasma activation time, volume of water introduced, bonding temperature, and bonding time.

The interface 2 between the two diamond spacers 1511 is shown in fig. 5B, and the spacers 1511 may be joined by a joining layer 104 formed on the two spacers 1511 (only the top spacers are shown in fig. 5B, since the bottom spacers have a similar configuration). Optionally, surface layer 1513 (Ti, si or W) may be deposited prior to the formation of the tie layer.

As in the case of fig. 5A, the layer disposed on the spacer 1511 may contain a bonding or RDL layer 1514 and a surface bonding layer 104 on top of it. Although not shown, the top spacer 1511 may also contain a TDV that acts as a thermal via to enhance heat dissipation upwards.

The interface 3 between the top die 102 and the HTC layer 1503A (see also fig. 4) is shown in fig. 5C, which is illustrated by way of example as diamond, but this HTC layer may also be an HTC TIM or made of other HTC materials indicated above. Bonding between the diamond and the backside of the die (e.g., silicon) may be achieved by direct bonding, without involving the surface bonding layer shown in fig. 5C. This would require planarization of the bonding surfaces of the top bare die diamond layer 1503A, top spacer 1511 and silicon to a surface roughness of, for example, less than 1nm, by CMP and Deep Reactive-Ion Etching (DRIE), with or without the use of a sacrificial layer such as silicon dioxide, as desired, and also requires preconditioning of all surfaces as desired. Pre-bonding conditioning of diamond and silicon surfaces may involve: (1) Wet surface pretreatment involving ultrasonic Deionized (DI) water cleaning, H ₂ SO ₄ /H ₂ O ₂ Treatment, NH ₃ /H ₂ O ₂ Processing and N ₂ Blow-drying; (2) Plasma/inductively coupled plasma reactive ion etching (ICP-RIE): o (O) ₂ 、H ₂ /O ₂ The method comprises the steps of carrying out a first treatment on the surface of the (3) Deep RIE (DRIE): o (O) ₂ /CF ₄ 、SF ₆ /O ₂ The method comprises the steps of carrying out a first treatment on the surface of the And/or (4) before bonding, activating the bonding surface in the bonding machine by a Fast Atom Beam (Fast Atom Beam) gun FAB (using, for example, an argon neutral Atom Beam at about 1 keV) or by an ion gun (using, for example, argon ions at about 60 eV) to vacuum remove the oxide film and expose dangling bonds at the surface for bonding. Note that: (1) FAB is very suitable for (sputtering) Si/Si, si/SiO ₂ Metal, compound semiconductor and monocrystalline oxide, while ion guns are known to be suitable for SiO ₂ /SiO ₂ Glass, si ₃ N ₄ (silicon nitride)/Si ₃ N ₄ 、Si/Si、Si/SiO ₂ Metals, compound semiconductors, and single crystal oxides, some of which may be deposited as a bonding layer as needed to promote bonding yield; and (2) preferably 10 during bonding ^-6 The vacuum of Pa (pascal) prevents re-adsorption to the activated bonding surface.

When there is a challenge in the direct bond between diamond and silicon and between diamond and diamond after the pre-bonding surface conditioning, a glue or bonding layer may be used. As shown in fig. 5C, a surface layer 151 (e.g., a Ti, si, or W layer) and a bonding layer 152 (e.g., au or solder) may be deposited on the HTC layer 1503A. When metal is used to form the bonding layer to achieve low temperature bonding at temperatures preferably below 250 ℃, the backside (e.g., silicon) of the top die 102 may be deposited with a good diffusion barrier layer 121 (comprising Ti, tiN, ti/TiN or Ti/Ni) and bonding layer 122 (e.g., au or solder). The top die 102 and the HTC layer 1503A may be bonded by respective bonding layers 152 and 122. In some other embodiments, the bonding layers 152 and 122 may be ultra-thin non-metallic glue layers, such as CVD polysilicon (poly-Si) layers, which may be deposited on diamond or on both diamond and silicon as an intermediate bonding layer to achieve a low temperature direct bonding high yield between diamond and silicon. Polysilicon (its thermal conductivity TC exceeds SiO in terms of minimizing the impact on the thermal resistivity of the final 3D IC or package structure ₂ 100 times the thermal conductivity TC of (c) is superior to SiO when used to create a thin bonding layer ₂ . The bonding layer is typically ultra-thin (about 100nm or less than 100nm thick) to minimize its thermal effects. Higher TC and Lower Coefficient of Thermal Expansion (LCTE) jointsMaterials are preferred because of the low CTE of both diamond and silicon<3 ppm/. Degree.C.). Bond layer candidates include the above-described Ti/Au, polysilicon, silicon dioxide, and polyimide (the latter two for direct bonding involving, for example, oxide-to-oxide bonding) as well as others and combinations thereof: (1) nonmetallic: si (e.g. polysilicon), siO ₂ 、Si ₃ N ₄ 、Al ₂ O ₃ (alumina), diamond, boron nitride, graphene, polyimide; (2) metal: ti, W, pt, cr, au, cu, ir Nickel (Ni), iron (Fe), ag-In, au-In, ag, sn, solder, transient liquid bonding metals; and (3) metal on oxide: srTiO ₃ Ir on, YSZ/Si, ir on MgO, sapphire or TaO ₃ Ir.

After deposition, the bond layer may be pretreated, DRIE (e.g., using SF), as desired by the planarization process and pre-bonding surface described above ₆ O and O ₂ Is a mixture of (a)), plasma/ICP-RIE (using O) ₂ 、Ar、N ₂ 、Ar/O ₂ ) And a FAB (using, for example, ar neutral atoms) or an ion gun (using, for example, ar ions) in the bonding station. The application of bonding pressure and bonding surface heterogeneity by the bonding layer die may be considered as needed to improve C2W (chip-to-wafer; or wafer-to-wafer W2W) bonding yield. Bonding may also be performed by C2W or W2W bonding under vacuum and at low temperature (preferably room temperature) with application of bonding force, followed by annealing at a temperature preferably less than 250 ℃. In the case of transparent diamond (e.g., single crystal diamond SCD), a 1 picosecond 355nm pulsed laser may also be used to improve bond quality and yield. The C2W bonding may be achieved with a high precision hot press (TCB) bonding apparatus, and a commercially available W2W bonding apparatus may be used for the W2W bonding. The ability to deliver ultra high integration density oxide-to-oxide-based W2W (or C2W) bonding relies on the use of bonding layers (e.g., siO ₂ ) Self-aligned wafer-to-wafer bonding is achieved at relatively low temperatures (typically less than 400 ℃ and preferably less than 250 ℃). Also contemplated herein are Si-containing ₃ N ₄ Is a candidate for the above-described bonding layer. When bonding involves active ICs, a thermal exposure of no more than 400 ℃ allows the use of conventional metallization and low-k dielectrics, such asCu and carbon containing low-k BEOL. Two additional advantages of low temperature bonding are avoiding excessive wafer deformation due to thermal expansion matching effects and minimizing thermal impact on the underlying transistor high-k metal gate stack and function.

The interface 4 between the HTC layer 1503A and the cap 1503B is shown in fig. 5D and is illustrated using diamond as an example. As shown in fig. 5D, the aforementioned surface layer 151 and bonding layer 152 may be formed on HTC diamond layer 1503A, and the aforementioned surface layer 153 and bonding layer 154 may also be formed on metal cap 1503B when an HTC material, such as diamond, is used to form at least a portion of cap 1503. When referring to metal cap 1503A, a TIM may be used to bond HTC diamond layer 1503A and metal cap 1503B.

More details concerning the four interfaces 1 to 4 will be provided below. The bonding layer present as the top layer of RDL at interfaces 1 and 2 (fig. 5A and 5B), which is part of RDL and on the surface of RDL, may be silicon dioxide or PI-based and may be formed on a diamond surface that is typically pre-coated with Ti, si or W that reacts with diamond and forms stable carbides. Ohmic metal carbide contacts may be formed on diamond using thin films, multi-layer metal coatings based on carbide formers as an adhesion basis, followed by deposition of an optional intermediate bonding layer, such as nickel (Ni) or nickel vanadium (Ni-V), and a stable inert metal, such as a noble silver (Ag) or gold (Au) layer, as the final bonding layer (for interfaces 3 and 4). These coatings on diamond are stable up to about 400 ℃ and can be used to attach, for example, diamond layer 1503A to the back side of the IC (e.g., top memory die 102) at interface 3 (fig. 5C) and cover 1503B at interface 4 (fig. 5D) that are pre-coated with a barrier layer.

In order to prevent metal diffusion in the IC silicon (Si) substrate at interface 3 (fig. 5C), a diffusion barrier layer 121 is required on the Si backside. The barrier layer 121 may be titanium (Ti), chromium (Cr), or tungsten (W). Stacks of Ti, ti/nickel vanadium (Ni-V) and Ag may be sputter deposited on the Si backside after an in situ sputter etch using argon (Ar) to remove native oxide from the Si backside to prepare the Si for bonding, wherein: (1) the Ti layer may act as a barrier to Ni diffusion towards Si; (2) The Ni-V layer (solderable intermediate layer) forms a good bond with the soft solder; and (3) the bonding Ag layer protects the underlying layer from oxidation and achieves solderability.

The Ti/Ni-V/Ag metal stack may be adapted to achieve low stress and low wafer warpage that are particularly important for thin ICs commonly found in 3D IC structures by adjusting the sputtering conditions. Ag-to-Ag and Au-to-Au bonding using TCB can occur at temperatures below 250 ℃. Ag and Au have high thermal conductivities of 430W/mK and 320W/mK, respectively (about 400W/mK for copper and 148W/mK for silicon) and have high melting points of 961 ℃ and 1064 ℃ respectively. Au is more expensive than Ag. Ag and Au can be sputter deposited or plated. The interface 3 may be formed by, for example, bonding Ti/Ni-V/Ag on Si to Ti/Ag on diamond, bonding Ti/Ni-V/Au on Si to Ti/Au on diamond, or bonding Ti/Au on Si to Ti/Au on diamond, while Ti/Au on diamond may also be Ti/platinum (Pt)/Au on diamond. The lid 1503B and the heat sink 1503C may be made of copper, silicon, diamond, or other higher TC materials as described above.

Bonding the high TC layer 1503A to the cap 1503B at interface 4 (fig. 5D) may be accomplished by, for example, bonding Ti/Au or Ti/Ag on both the diamond and cap or in a manner similar to that formed at interface 3, except that a barrier layer is not required here. In this embodiment, lid 1503B is supported by vertical shelf 1516 on support 103, and the engagement of vertical shelf 1516 with support 103 may be accomplished based on a Thermal Interface Material (TIM) or other HTC engagement material placed on top of thermal vias in support 103, including solder and appropriate surface coatings at the engagement interface. In some embodiments, heat sink 1503 may be an integrated heat sink and may be joined to support 103 by a similar method.

For bonds involving large areas and non-uniformities or warpage that may occur when interface 4 is formed, au and Ag may be co-deposited and thereafter used for bonding with or without an etching process of Ag. The use of sintered Ag high heat semi-sintered materials or high heat die attach materials, such as materials used in making optical transceivers for optical communications, is also contemplated. In addition, it is also contemplated that vacuum vapor phase bonding may be used to perform transient liquid phase bonding based on copper-tin (Cu-Sn), ni-Sn, au-Sn, ag-Sn, silver-indium (Ag-In), or Au-In at bonding temperatures below 300 ℃ as needed to minimize void formation at the bonding interface.

Fig. 6A-6E show fabrication operations for constructing the semiconductor package 10 in fig. 4. In fig. 6A, a release layer 171 is applied over a 12 "carrier 170 and die 101 and spacers 1511, containing RDL and vias as needed, are bonded to release layer 171. Depending on the thicknesses of die 101 and spacer 1511, the bonding of the two may require the use of another temporary carrier with another release layer (not shown here). In the present embodiment, the spacer 1511 is disposed on the carrier 170 side by side with the die 101. Die 101 and spacer 1511 are then overmolded by mold compound 106, and mold compound 106 is planarized to expose TSV 1012 in die 101 (or RDL on die 101) and TDV 1521 in spacer 1511 (or RDL on spacer 1511). Next, an RDL 104 is formed thereon as shown in fig. 6B.

Fig. 6C and 6D stack the die 102 and the spacers 1511 of the second and third layers by repeating the process described in fig. 6B. Details may be referred to the description of fig. 6B and are not repeated here for brevity.

After the 3D die structure in fig. 6D is mounted on a wafer mount tape supported by a wafer mount frame, carrier 170 (e.g., 12 "glass) is released using a suitable laser source and the 3D IC stack structure is diced to make the dicing independent, and the independently diced 3D IC structures can be bonded to support 103, support 103 can be in wafer form and supported by a temporary carrier using a release layer, and the carrier can be released after bonding and wafer mounting, singulated after carrier release, and bonded to laminated substrate or PCB 1401. Alternatively, individual 3D IC structures may be bonded to the support 103' that has been pre-bonded to the laminate substrate or PCB 1401. Finally, a heat sink 1503 comprising an HTC layer 1503A, a metal cap 1503B, and a heat sink 1503C may be disposed over the 3D IC stack structure, wherein the cap 1503B may be thermally coupled to the support 103 through a vertical shelf 1516. In this way, the semiconductor package 11 shown in fig. 7 can be formed.

Fig. 7 shows a semiconductor package 11 including a 3D IC structure according to another embodiment of the present disclosure. The difference between the semiconductor package 11 and the semiconductor package 10 (fig. 4) is that: the semiconductor package 11 involves first stacking two memory ICs for illustration (i.e., die 102 covering a control IC; more than 2 dies 102 may also be stacked) on a logic IC (i.e., die 101), bonding a stack of die 101 and 102 containing diamond spacers to a support 103' (e.g., silicon diamond or diamond interposer) that may be pre-bonded to a laminate substrate 1401 or may be subsequently bonded to the laminate substrate 1401, and attaching a cover 1503B ' to the laminate substrate 1401, but not to the support 103', by a vertical shelf 1516.

Fig. 8A-8F show fabrication operations for constructing the semiconductor package 11 in fig. 7. In fig. 8A, taking as an example a silicon-diamond interposer (but which is also a diamond interposer) that includes RDL and TSDV on both its top and bottom sides, a support 103' that includes a silicon portion 1032, a diamond portion 1031, and a TSDV1033 may be prepared first. TSDV1033 passes through silicon portion 1032 and diamond portion 1031 and connects to RDLs 1036 and 1037 formed on two opposite surfaces of support 103'. Carrier 170 (e.g., a 12 "glass carrier for use in fanning) is bonded to support 103' by use of a release layer 171 that is releasable by a laser (or other means, such as thermomechanical shearing and cleaning as needed) to provide mechanical support to support 103' because support 103' is typically thin, such as 100 μm or less in thickness.

In fig. 8B, die 101 and spacer 1511 (with a surface bonding layer) forming part of structural member 1501 are bonded to support 103 'by RDL 1037 through RDL 1514 (with a surface bonding layer) of spacer 1511 and support 103' using non-conductive glue NCP and in a hybrid bond or microbump based flip chip bond. The die 101 and the spacer 1511 are overmolded with the molding compound 106, and the molding compound 106 may be planarized by CMP and DRIE to expose the TSVs 1012 in the die 101 (or RDL or BEOL layers of the die 101) and the TDVs 1521 in the spacer 1511, with or without a sacrificial layer (e.g., silicon dioxide) as desired, followed by the formation of new RDLs 104 on the molding compound 106. Fig. 8C and 8D stack the second and third layers of die 102 and spacers 1511 by repeating the process described in fig. 8B to obtain the structure shown in fig. 8D, with the backside of the top die 102 and top spacers exposed (without the molding compound). As previously mentioned, the top spacer 1511 placed side-by-side with the top die 102 may also be provided with thermal vias (not shown). For more details, reference is made to the description of FIG. 8B, which is not repeated here for brevity.

In fig. 8E, another carrier (e.g., a 12 "glass carrier) that provides mechanical support is attached to the backside of the top die 102 (the side opposite the side with FEOL and BEOL layers) and the top spacer 1511 by using a release layer 173. Carrier 170 is then released using an appropriate means, such as laser irradiation, and solder bumps 1201 or micro-bumps with appropriate under-bump metallurgy (UBM) are formed on RDL 1036 on support 103' opposite RDL 1037.

After mounting the structure in fig. 8E on a wafer mount tape supported by a wafer mount frame, carrier 172 may be released by using an appropriate laser source; the semiconductor package 11 is then diced or singulated using processes including laser cutting, mechanical cutting, plasma/DRIE etching, wet etching, or combinations thereof, and the singulated structure shown in fig. 8E (without carrier 172 and release layer 173) is bonded to a laminated substrate or PCB 1401, as shown in fig. 8F. Finally, a heat sink 1503 'including an HTC layer 1503A, a metal cap 1503B', a heat sink 1503C, and a TIM (as desired) may be disposed over the exposed top die 102 and the exposed top spacer 1511 in the structural member 1501 (shown in fig. 8F), while the structural member 1501 is disposed over the laminate 1401, thereby forming a thermal coupling between the die 102, the spacer 1511, the laminate 1401, the support 103', the structural member 1501, and the heat sink 1503'. In this way, the semiconductor package 11 shown in fig. 7 can be formed.

Referring back to fig. 7 (and fig. 4), the semiconductor package 11 (and the semiconductor package 10) implements: (1) The cross-die or multi-sided signal and power transmission (i.e., power and signals may now be supplied directly from both the bottom die 101 and/or the interposer supporting the bottom die 101 on the bottom side (i.e., support 103') to the die 101 above and all other dies 102 in the die stack, one die at a time, as compared to a conventional single-sided interconnect that can only be supplied from the bottom die 101 to the die directly above and then from the top die to the further die above it); and (2) double-sided or multi-sided cooling of 3D IC structures (containing logic die 101, which may be a high performance high power processor), where heat may flow up to the heat sink, sideways to the HTC spacers, and down to the HTC supports.

Using the structure in fig. 7 as an example, in particular, heat may be: (1) Dissipating upward from die 102 on the top side of the 3D IC structure to lid 1503B' to heat sink 1503C; and (2) dissipate from the bottom side 101 of the 3D IC structure (i.e., logic die 101) down to HTC support 103 '(e.g., a silicon-diamond interposer) and then up to HTC spacers 1511 and structural members 1501 placed side-by-side with ICs 101 and 102 to the diamond plate (i.e., HTC layer 1503A) to lid 1503B' to heat sink 1503C.

Fig. 9A-9D provide a process for creating an advanced diamond interposer (e.g., spacers 1511 and supports 103/103') or diamond-based IC from a full-size (e.g., 12 "diameter) reconstituted diamond wafer. To create a diamond interposer from a full-size reconstituted diamond wafer, one may start with a full-size (e.g., diameter 12 ") diamond substrate 40 (e.g., about 100 μm thick and approximately the thickness of a 2.5D silicon interposer) shown in fig. 9A and subject it to the use of oxygen as an etching gas (in combination with, for example, CF ₄ Is a further heavier gas) of a mask such as aluminum/silicon dioxide, aluminum/silicon/aluminum or stainless steel (DRIE or so-called Bosch process) to create a Through Diamond Via (TDV) hole (not shown) of high aspect ratio (high aspect ratio) at a high etch rate. In some embodiments, thousands of TDV holes with a diameter of 20 μm and a width to depth ratio of 5 may be created in each wafer after a DRIE operation. Other mask options that may be considered include aluminum, titanium, gold, chromium, silicon dioxide, aluminum oxide, photoresist, and/or spin-on glass. The etch mask material needs to be etched more slowly than diamond in DRIE with high selectivity. Ultra-short pulse (e.g., femtosecond pulse) laser micromachining can also be used with appropriate etching and cleaning operations or in conjunction with DRIE processes for improved etching performance. The combination of DRIE and epitaxial deposition creates ultra high aspect ratio (up to 500) holes in silicon. It may also be shaped later to create an ultra-high aspect ratio TDV. After opening of the TDV hole, plasma enhanced chemical vapor deposition of e.g. oxide can optionally be performed by sputtering (Plasma Enhanced Chemical Vapor Dep The process includes, for example, the steps of, for example, the physical vapor deposition (physical vapor deposition, PVD) of the oxide, PECVD) and barrier/seed titanium/copper (Ti/Cu) or tantalum nitride/Cu (TaN/Cu), followed by copper (Cu) plating to fill the TDV hole. Subsequently, chemical Mechanical Polishing (CMP) and DRIE (with or without a sacrificial layer, such as silicon dioxide, as needed) can be used to remove the overburden Cu and complete the TDV 41.RDL 43 (e.g., micron-sized fine line RDL) and a surface coating (or bond pad) may then be formed on front side 40F of diamond substrate 40, as shown in fig. 9B. Because the interposer illustrated in fig. 9A-9D is typically thin, before another RDL 45 is formed on the opposite side of the diamond substrate 40, in fig. 9C a carrier 47 (e.g., also a glass substrate commonly used in fan processing) may be bonded to the RDL 43 of the interposer by using a release layer 49, wherein the release layer 49 can withstand the high temperatures induced during polyimide-based RDL formation, followed by a thinning operation involving CMP and DRIE using a sacrificial layer (e.g., silicon dioxide) as needed so that TDV 41 at the back side 40B of the diamond substrate 40 can be exposed. As shown in fig. 9D, after RDL 45 formation, the resulting structure may be mounted on a wafer mounting tape supported by a wafer mounting frame to prepare the structure for dicing, and carrier 47 may be removed, for example, by exposing release layer 49 (or other means including thermo-mechanical shearing) to laser light, followed by a dicing operation to singulate diamond substrate 40 in order to obtain a diamond interposer of the desired size for forming the package structures described herein.

It will be appreciated by those of ordinary skill in the art that the procedure described in fig. 9A-9D is also applicable to the fabrication of diamond-based or other HTC material-based integrated circuits or other structures other than intermediaries.

Fig. 10A-10D and 11A-11D provide advanced ICs that can be created using diamond-based composite wafers (e.g., double and triple wafers) in which diamond can be placed in close proximity to chip hotspots for rapid diffusion and dissipation of heat. In fig. 10A, a full-size reconstituted silicon-diamond dual wafer 50 is first provided, followed by a fluorinated gas (e.g., CF ₄ 、SF ₆ Or xenon difluoride) as an etching gas to the silicon portion of the dual wafer 600 (i.e., the so-called bosch etch process)Device layer) to create Through Silicon Via (TSV) holes (not shown), and this process may be implemented in connection with IC FEOL and BEOL processes of a composite wafer. Subsequently, the diamond hole directly below the TSV hole may be opened using the process described in fig. 9A and 9D to create a diamond through hole (TDV) hole in the diamond portion of the double wafer 50 below the TSV hole, thereby forming a silicon-diamond through hole (TSDV) hole (not shown). Subsequently, the diamond interposer process described in fig. 9A-9D may be followed from PECVD and PVD (e.g., sputtering) for passivation and barrier/seed layer deposition, copper plating (Cu) to fill the TSDV holes, CMP to remove the overburden Cu, and completion of the steps to build the TSDV 51. As shown in fig. 10B, RDL 53 may then be formed on front side 50F (e.g., the surface of the silicon portion) of dual wafer 50 connected to TSDV 601. Because the dual wafer IC in fig. 10A-10D may be very thin, before another RDL 55 is formed on the opposite side of the dual wafer 50, a carrier 57 (e.g., a glass substrate commonly used in fan processing) may be bonded to the RDL 53 of the dual chip IC by a release layer 59, as shown in fig. 10C, wherein the release layer 59 may withstand the high temperatures induced during formation by polyimide-based RDLs, followed by a thinning operation involving CMP and DRIE as needed, so that the TSDV 51 on the back side 50B of the dual wafer 50 can be exposed. In fig. 10D, after RDL 55 with appropriate surface coatings and bond pads (e.g., micro bumps) is formed and the resulting structure is mounted to a wafer mounted tape/frame, carrier 57 may be removed by exposing laser radiation release layer 59 or other means including thermo-mechanical shearing, wet cleaning, or a combination thereof, and the resulting structure may be cut or singulated by a cutting operation including laser cutting, mechanical cutting, plasma etching, wet etching, or a combination thereof to singulate double wafer 50 in order to obtain the desired size silicon-diamond ICs or intermediaries for use in the package structures described herein.

Similar operations in fig. 10A-10D may be applied to the three wafer scheme illustrated in fig. 11A-11D, which is better suited for the formation of thin processor or memory dies, for example, containing a thin silicon-based device layer, a thin diamond layer placed in close proximity to the device layer to dissipate heat from the chip hot spot, and a thicker silicon carrier layer for facilitating thin film processing. In the case of the view of figure 11A,a full-sized silicon-diamond wafer 60 (e.g., 12 ") is first provided comprising a first silicon portion 62, a diamond portion 64, and a second silicon portion 66, followed by a fluorinated gas (e.g., CF) ₄ 、SF ₆ Or xenon difluoride) as an etching gas to create Through Silicon Via (TSV) holes (not shown) in one of the silicon portions of the wafer 60, a so-called bosch etch process, and this process may be implemented in conjunction with FEOL and BEOL processes of ICs of a composite wafer. Subsequently, the diamond under the TSV hole may be partially or fully opened using the process described in fig. 9A-9D to create a diamond through hole (TDV) hole in the diamond portion of the three wafer 60, whereupon the TSV hole may be via an alignment mark as needed, and thereby form a silicon-diamond through hole (TSDV) hole (not shown). The diamond interposer process described in fig. 9A-9D may be followed from PECVD and PVD (e.g., sputtering) for passivation and barrier/seed layer deposition, copper plating (Cu) to fill TSDV holes, CMP to remove overburden Cu, and completion of the steps to build TSDV 61. In fig. 11B, RDL 63 may then be formed on front side 60F of wafer 60. Because the three-wafer IC in fig. 11A-11D may be very thin, a carrier 67 (e.g., a glass substrate commonly used in fan processing) may be bonded to the RDL 63 of the three-wafer IC by a release layer 69 prior to forming another RDL 65 on the opposite side of the three-wafer 60, wherein the release layer 69 may withstand the high temperatures induced during formation of a typically polyimide-based RDL, as shown in fig. 11C, the silicon carrier portion 66 of the three-wafer 60 may be removed to expose the TSDV during planarization processes using CMP and DRIE, and a sacrificial layer (e.g., silicon dioxide) may be used or not used during such periods as desired. After RDL 65 is formed over exposed diamond portion 64 and TSDV 61, carrier 67 may be removed after wafer mounting by laser irradiation release layer 69 or other suitable means (as shown in fig. 11D), followed by dicing or singulation operations to frees the ICs to obtain silicon-diamond ICs or intermediaries of the desired dimensions for use in the package structures described herein.

Fig. 12A and 12B outline advanced ICs, advanced intermediaries, and advanced spacers that may be created from a diamond composite wafer (i.e., a double wafer and a three wafer) comprising a diamond substrate D1 and a silicon substrate S1. In fig. 12A, an advanced IC or advanced interposer is formed with RDL R1 and micro bump B1 on one side and RDL R2 and metal pad P2 on the other side, while in fig. 12B, an advanced IC or advanced interposer is formed with RDL R1 and metal pad P1 on one side and RDL R2 and metal pad P2 on the other side. Further, here, via T1 (i.e., TSDV) may include an electrical via, an optical via, a thermal via, or a combination thereof, while RDLs R1 and R2 may be useful not only for electrical interconnection purposes but also for optical interconnection purposes involving waveguide functionality.

Fig. 13 shows a semiconductor package 12 including a 3D IC structure according to another embodiment of the present disclosure. The difference between the semiconductor package 12 and the semiconductor package 10 in fig. 4 is that: the die 101 'and 102' of the semiconductor package 12 are built using the process shown in fig. 10A-10D and 11A-11D using ICs built based on silicon-diamond composite wafers. Taking the die 101' as an example, the backside 101B ' (silicon layer) of the die 101' may be thermally coupled to a support 104', which is a diamond layer and an interposer comprised of a material having a thermal conductivity greater than silicon, and having a cross-sectional width substantially equal to the cross-sectional width of the first die 101 '. The support 104' and die 101' are combined to form a composite wafer-based composite layer having at least one Through Silicon Diamond Via (TSDV) 105' for signal/power transmission and/or enhanced heat dissipation through the die 101' and support 104 '. In some embodiments, the die 101 'and support 104' may be, for example, a composite layer cut from a silicon-diamond composite wafer. The composite layer in the semiconductor package may be cut from a silicon-diamond composite wafer, which may be made of, for example, a silicon-diamond double wafer or a silicon-diamond-silicon wafer. The dies 101 'and 102' can be implemented by the processes shown in fig. 10A-10D and fig. 11A-11D.

In addition, semiconductor package 12 may omit spacer 1511 used in semiconductor package 10, and thus, heat transferred to support 103 'may be dissipated upward to cover 1503B through structural member 1501' (i.e., a vertical shelf) supporting cover 1503B. In this embodiment, the cover 1503B may be secured to the structural member 1501' with a joint 1517 created by bonding, cold welding, or the like. In this case, the 3D IC structure in semiconductor package 12 may improve cooling efficiency by a combination of support 104', support 103', cover 1503B, HTC layer 1503A, and heat sink 1503C placed in close proximity to the chip hot spot. In some embodiments, cover 1503B may be cooled by a capillary vapor phase cooling mechanism using, for example, a thermally conductive plate. The 3D structure shown in fig. 13 without a heat sink can be easily extended to liquid submerged cooling by immersing the structure, together with the cover and structural member 1501 'on support 103', in a dielectric coolant or water with appropriate surface passivation.

Fig. 14 shows a semiconductor package 13 including a 3D IC structure according to another embodiment of the present disclosure. The difference between the semiconductor package 12 and the semiconductor package 13 is that: to better suit mobile applications, the heat sink 2503 of the semiconductor package 13 may not include a fin heat sink based on space constraints. In particular, fig. 14 shows the 3D IC structure being cooled by means of diamond composite wafer based ICs 101' and 102', a silicon-diamond or diamond-based support 103' and HTC heat sink 2503, wherein heat sink 2503 may be embodied as a heat guide plate, which may be part of the back cover of the smart handheld device.

Fig. 15 shows a semiconductor package 14 including a 3D IC structure according to another embodiment of the present disclosure. The difference between semiconductor package 12 and semiconductor package 14 is that: the semiconductor package 14 further includes a second HTC support 1601 between the silicon die 101 "and 102", e.g., between the processor die and the control die and/or between the two top silicon die 102 ". The support 1601 may include an interposer (e.g., a diamond interposer) comprised of a material having a thermal conductivity greater than silicon. Also, to enable signal and power transfer between different layers of dies, vias 1602 may be formed in the support 1601, and RDLs may be formed on both the top and bottom sides of the support 1601, and the support 1601 may be bonded with the silicon dies 101 "and 102" using copper hybrid bonding or flip-chip bonding based on micro bumps. For example, in some embodiments, the support 1601 may comprise a diamond interposer, and the through holes 1602 may be formed in the diamond interposer support 1601, or the support 1601 may comprise a silicon-diamond interposer with TSDV.

The semiconductor packages 10, 11, 12, 13 and 14 shown in fig. 4, 7, 13, 14 and 15 relate to conventional IC processes that create both FEOL and BEOL layers on the same side (front side) of the IC. That is, in the semiconductor packages 10, 11, 12, 13, and 14, the front side 101F of the die 101 (using the semiconductor package 10 in fig. 4 as an example) is disposed in close proximity to the support 103, and the back side 101B of the die 101 is disposed farther from the support 103 than the front side 101F.

For IC processes at the 2nm node and beyond, a Back-side power supply network (Back-side Power Delivery Network, BSPDN) is required. This applies to advanced processors that cover applications for mobile devices, HPCs, data centers, and AI. Fig. 16 shows a semiconductor package 15 that is similar to the Front side power supply network (FSPDN) -based semiconductor package 10 shown in fig. 4, except that the semiconductor package 15 employs BSPDNs to form the processor die 201. In this case, BEOL layers will appear on both sides of the ultra-thin IC 201, i.e., FEOL, local interconnect and intermediate interconnect on the front side, while global interconnect is on the bottom side, where the back side may be disposed in close proximity to the support (in sharp contrast to the front side in the case of FSPDN). Further, the die 201 may be cooled by HTC supports 204 (e.g., HTC structures, such as diamond spacers) disposed directly below the backside of the die 201. The support 204 may include an interposer comprised of a material having a thermal conductivity greater than silicon, which may be diamond-based or other HTC materials. Also, the support 204 has a cross-sectional width that is substantially equal to the cross-sectional width of the processor die 201, and the die 201 and support 204 may be bonded to the die 201 by way of copper hybrid bonding and use the BSPDN process shown in fig. 24A-24C to collectively form a processor-HTC material combination or a processor-diamond combination.

As shown in fig. 16, the die 201 may have its back side 201B disposed in close proximity to the support 204 and its front side 201F disposed farther from the support 204 than the back side 201B. In this embodiment, power may be transferred from the laminate substrate or PCB 1401 to the FEOL layer device formed on the die 201 through the solder ball 1201, TSDV 1033 'in the support 103', TDV 2041 in the support 204, and TSV 2012 (including nano-TSVs) in the die 201.

Fig. 17 shows a semiconductor package 16 including a 3D IC structure according to another embodiment of the present disclosure. Although the semiconductor package 16 also employs a processor die 201' with a BSPDN, as is the case with the semiconductor package 15 in fig. 16, one difference between the semiconductor package 16 and the semiconductor package 15 is that: the die 201 'and 202' of the semiconductor package 16 may omit the spacer 1511 used in the semiconductor package 15 in fig. 16. Also, the die 202 'stacked on the die 201' may be constructed of silicon-diamond composite wafers (e.g., double and triple wafers) with TSDV formed therein in order to achieve better cooling efficiency.

Fig. 18 shows a semiconductor package 17 including a 2.5D IC structure according to another embodiment of the present disclosure. In fig. 18, where die 301 (i.e., a processor die) is formed on HTC support 304 (i.e., a processor-diamond combination with BSPDN) and mounted on HTC support 303 side-by-side with at least one 3D DRAM stack 302 (each may include control die 3021 and DRAM die 3022), HTC support 303 may be an HTC substrate containing an interconnection bridge or an HTC support such as a diamond interposer or a silicon-diamond interposer. The support 304 may include an interposer comprised of a material having a thermal conductivity greater than silicon, which may be diamond based, silicon-diamond composite wafers, or other HTC materials as described above. In addition, thermal vias 3042 may also be formed within the silicon die 301 and the diamond support 304 to enhance heat dissipation. Note that: only power and thermal vias/interconnects are shown in fig. 18 for simplicity, while signal interconnects are not shown. The same applies to fig. 19 and 20.

As shown in fig. 18, the processor-diamond combination (i.e., die 301 on support 304) may have its back side 301B disposed in close proximity to support 304 and its front side 301F disposed farther from support 304 than back side 301B. In this embodiment, the support 304 has a cross-sectional width substantially equal to the cross-sectional width of the processor die 301.

In fig. 18, the semiconductor package 17 may further include a structural member 3501 and a heat sink 3503, the heat sink 3503 may be thermally coupled to the structural member 3501 and to the substrate 3401 containing thermal vias and thermal planes or to the HTC support 303 (not shown). The heat sink 3503 may include a metal heat sink, a heat conduction plate (or cold plate) 3503A, and a heat sink (or manifold) 3503B. The heat sink 3503A is thermally coupled to the die 301 and DRAM stack 302 by using the HTC TIM 3601 and HTC material 3603 (e.g., diamond plate) and to the heat sink 3503B that may be thermally coupled by another HTC TIM 3602. In this package configuration, heat generated by the die 301 and DRAM stack 302 may be more efficiently dissipated up to the heat spreader 3503B and down to the HTC supports 304 and 303. In the semiconductor package 18, the HTC material 3603 (e.g., diamond plate) may be bonded to the front side (i.e., FEOL/local interconnect/intermediate interconnect/RDL side) of the die 301 after the above-described structures and processes (see, e.g., fig. 5B). HTC material 3603 and the front side of die 301 mounted on support 304 may also be combined and mounted on top of support 303, as shown in fig. 18. However, the present disclosure is not limited thereto. In some other embodiments, HTC material 3603 may be omitted.

Fig. 19 shows a semiconductor package 18 including a 2.5D IC structure according to another embodiment of the present disclosure. Semiconductor package 18 is the counterpart of semiconductor package 17 shown in fig. 18, except that it has a conventional IC of FSPDN. In this case, the die 301' may be directly bonded to the support 303' using its front side 301F '. Furthermore, in semiconductor package 18, HTC TIM 3601 may also be replaced by a combination of HTC material (e.g., diamond plate) and TIM, as is the case with semiconductor package 17 shown in fig. 18.

Referring to fig. 18 and 20, the semiconductor package 17 in fig. 18 includes a 2.5D IC structure containing a processor die (i.e., a processor-diamond combination) with a BSPDN and a 3D DRAM stack 302 disposed side-by-side on a support 303, while the semiconductor package 19 in fig. 20 contains a 3D DRAM stack 402 mounted on top of the processor-diamond combination. In fig. 20, a semiconductor package 19 includes a 3D IC structure according to another embodiment of the present disclosure. The semiconductor package 19 includes a die 401 (e.g., a processor die), at least one DRAM stack 402 including a control die 4021 and a DRAM die 4022, and an HTC support 403 (e.g., a diamond interposer, a silicon-diamond interposer, an HTC laminate substrate, a silicon interposer, or an HTC structure). The DRAM die 4022 is stacked on the control die 4021, and the control die 4021 controllably manages the interconnection between the processor die 401 and the memory die 4022. The DRAM stack 402 is mounted on the processor die 401 with spacer interconnects or spacers 440 disposed therebetween, and the processor die 401 mounted on the support 404 may be disposed on a support 403 bonded to a laminate substrate or PCB 4401. Although not shown in fig. 20, the processor die 401 may carry more than one DRAM stack 402, e.g., four or six DRAM stacks 402 may be stacked on the processor die 401, in which case larger spacer interconnects 440 may also be used as desired.

Moreover, the semiconductor package 19 further includes an air gap 450, low Thermal Conductivity (LTC) spacer interconnects 440, optional RDL or BEOL layers (e.g., local and intermediate interconnects) 460, HTC structural members 4501, and HTC heat sinks 4503. The air gap 450 is defined by the LTC spacer interconnect 440, the processor die 401, and the control die 4021, with the spacer interconnect 440 disposed between the processor die 401 and the DRAM stack 402 under the control die. In this embodiment, the LTC spacer interconnect 440 and the air gap 450 may be used to insulate (the air gap 450 may also be created within the BEOL layer to achieve insulation and speed as needed) in order to block heat from the processor (e.g., die 401) that is typically much higher in power than the memory device. In some other embodiments, the spacer interconnect 440 may also be made of HTC materials, depending on the application.

Heat sink 4503 is thermally coupled to structural member 4501. The heat sink 4503 may include heat sinks, such as a cooling plate 4503A, and a heat sink (or manifold) 4503B. The cooling plate 4503A is thermally coupled to the DRAM die 4022 by an HTC TIM 4601, and the heat sink 4503B may be thermally coupled to the cooling plate 4503A by another HTC TIM 4602.

In addition, structural member 4501 includes vertical shelves 4515 and HTC bridges 4516 for supporting heat sink 4503, which may be used to provide a heat dissipation path from support 403 with thermal vias/planes to cooling plate 4503A and then to heat sink 4503B of heat sink 4503, so that heat generated by processor die 401 may be dissipated first down to support 403 and then up to heat sink 4503 through HTC bridges 4516.

RDL 460 contains conductive traces over front side 401F of processor die 401, and a thermal insulating layer or heat spreading layer may be formed in RDL 460, in a back-end-of-line (BEOL) structure proximate front side 401F of processor die 401, and/or in a front-end-of-line (FEOL) structure proximate front side 401F of processor die 401.

Additionally, an embedded heat spreader 4701 may be formed in the DRAM 402, and similarly, the embedded heat spreader may also be placed in the support 403 and/or other dies and structures, such as the processor die 401, for better heat dissipation.

Fig. 21 shows a semiconductor package 20 including a 3D IC structure according to another embodiment of the present disclosure. The semiconductor package 20 has a structure similar to that of the semiconductor package 19; however, in the semiconductor package 20, the processor-diamond combination containing the processor die 401 is powered by the previously mentioned BSPDN, and the DRAM stack 402' is mounted with the control IC 4021' disposed on top of the DRAM stack and its bottom DRAM die 4022' mounted directly on the processor die 401, and wherein the control IC is powered from the top side. That is, the processor die 401 and the bottom DRAM die 4022 'of the DRAM stack 402' are interconnected in flip-chip bonding based on micro-bump or copper hybrid bonding. In fig. 21, a heat sink 4503 is disposed over structural member 4501 and circuit layer 4403 bonded to control die 4021' with HTC material 4601 in between, wherein circuit layer 4403 is connected to a laminate substrate or PCB 4401 through flexible circuit interconnects (conductive lines) 4402. In this case, the laminated substrate or PCB 4401 may support the support 403, the processor-diamond combination containing the processor die 401, the memory die 4022', and the control die 4021'.

For DRAM stack 402', power is delivered from the backside (top side in fig. 21) of control die 4021' through circuit layer 4403 and power (and signal) connectors (e.g., flex circuit interconnect 4402), where circuit layer 4403 may be, for example, a low Coefficient of Thermal Expansion (CTE) HTC diamond or clad metal (e.g., copper-invar-copper) interposer, and its CTE may be matched to the CTE of silicon to enhance heat dissipation and reliability. In particular, the flex circuit interconnect 4402 electrically connects the laminate substrate and the PCB 4401 and the circuit layer 4403 proximate to the heat sink 4503, wherein the flex circuit interconnect 4402 is configured to provide a path for transmitting power and signals to the control die 4021'.

In some embodiments, the circuit layer 4403 may be a clad metal having unique properties, such as copper-invar-copper and copper-Mo-copper. Invar is an Fe-Ni alloy with 36% nickel content that exhibits the lowest Coefficient of Thermal Expansion (CTE) of known metals and alloys at 1.2ppm/°c, for example, between 20 ℃ and 100 ℃ and which CTE remains fairly low from the lowest temperature up to approximately 230 ℃. By adjusting the thickness of copper, the metal core (invar or Mo), and copper, the CTE of the clad metal can be made to approach that of silicon (about 3ppm/°c) or between that of silicon and PCB (about 12ppm/°c). The resulting tile having an electrodeposited copper layer with a thickness between 0.5 mil and 5 mil, and on at least one side of the thickness between 1 μm and 50 μm has a CTE of 2.8 to 6ppm/°c at a temperature between 0°f and 200°f. In addition, we can adjust the thickness of the cladding metal layer to achieve an HTC, such as 2 to 3W/cm/. K (4W/cm/. K relative to copper), that is much higher than the TC of silicon (1.5W/cm/. K).

For high speed applications, polyimide dielectric based conductive lines with multiple (i.e., 2) metal (copper Cu) layers can be a good interconnect solution. Since the flexible member is mechanically formable and bendable, the flexible member may also be used to connect metal pads on one side in 3D and may also connect metal pads on multiple sides therein. The flex may provide high density interconnects (with pitches as small as 20 μm and even as small as 10 μm), DC power transmission, integrated I/O (input and output), power distribution, decoupling, and electromagnetic compatibility. All of the above good properties, together with the fact that the flex can be tested as known to be good prior to bonding, make the flex (particularly adhesive-free flex) an ideal candidate for 3D interconnection. Taking Chip-on-Film (COF) bonding for liquid crystal display applications as an example, thermocompression bonding (Thermo-Compression Bonding, TCB) is used to bond an adhesive-free flexible member with Cu leads (which may be pre-tin-plated Sn) to gold bumps, sn bumps or tin/copper (Sn/Cu) bumps on glass or substrates, for example, for applications like mobile devices. A solvent-free epoxy underfill may be applied after bonding to avoid air bubbles that may be associated with improper baking of the solvent-based underfill. Alternatively, a non-conductive adhesive (NCA) or non-conductive paste (NCP) may be applied prior to bonding to the glass in a manner similar to the fine pitch flip chip micro bump assembly, followed by TCB. Pre-baking may be performed on the circuitry prior to flexible bonding to ensure that delamination will not occur. Metal pads residing on bonding flexures on different sides may be interconnected using flexures, such as wires/pads with palladium (Pd) -containing passivation layers, for flexure-to-flexure bonding at low temperatures, such as 140 ℃.

Fig. 22 shows a semiconductor package 21 including a 3D IC structure according to another embodiment of the present disclosure. The semiconductor package 21 has a structure similar to the semiconductor package 14 relating to FSPDN (see fig. 15); wherein the semiconductor package 21 contains a support 5601 disposed between the processor die 501 and the die 502 in a vertical direction and between two adjacent dies 502. In some embodiments, the one or more dies 502 referenced herein include a control die 502 and a memory die 502 in a DRAM stack, and wherein the control die 502 is disposed at a bottom of the one or more memory dies 502. The support 5601 may also be referred to as an HTC structure that includes an interposer (e.g., a diamond interposer or a silicon-diamond interposer) comprised of a material having a thermal conductivity greater than silicon, thereby facilitating heat dissipation. The support 5601 may have a cross-sectional width that is greater than or substantially equal to a cross-sectional width of the processor die 501 or an adjacent memory die 502.

In addition, the semiconductor package 21 further includes a via 5602 formed in the support 5601, an RDL 5603 formed on a first side of the support 5601, and an RDL 5604 formed on a second side of the support 5601 opposite the first side, wherein the RDLs 5603 and 5604 may be electrically connected through the via 5602, thereby allowing for signal and power transfer and enhancing heat dissipation related to the processor die 501 and the control and memory die 502.

In the semiconductor package 21, the processor die 501 may be a die having an FSPDN formed using a diamond-silicon composite wafer, and where the die contains silicon or active IC portions and a diamond support portion 504, and the silicon portion on the support 504 may be mounted on an HTC support 503. Alternatively, the diamond portion 504 may be placed on top of the silicon portion of the processor-diamond combination in the semiconductor package 21.

The semiconductor package 21 further includes a structural member 5501 and a heat sink 5503. The heat sink 5503 is thermally coupled to the structural member 5501 by an HTC Thermal Interface Material (TIM) 5611, and the heat sink 5503 may also be thermally coupled to the memory die 502 by another HTC TIM 5612. Also, the structural member 5501 may include a diamond spacer thermally coupled to the support 503 through a TIM 5613. The support 503 may comprise an interposer comprised of a material having a thermal conductivity greater than that of the silicon interposer material. For example, the support 503 may include a diamond interposer with a TDV 5031 formed therein for signal/power transmission and enhanced heat dissipation. In some embodiments, the support 503 may be comprised of diamond, silicon, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or combinations thereof.

The support 503 is mounted on a laminate substrate or PCB 5401. Accordingly, in addition to heat dissipation in the upward direction, the support 503 and structural member 5501 (e.g., diamond spacers) may also provide a heat dissipation path from the bottom of the die 501 to the support 504 and then to the support 503, structural member 5501, and heat sink 5503, and may also enhance the heat dissipation effect of this path due to the presence of the support 5601. In some embodiments, the heat sink 5503 may include a diamond heat sink, a heat guide plate, a TIM, or a combination thereof, depending on system requirements.

Fig. 23 shows a semiconductor package 22 including a 3D IC structure according to another embodiment of the present disclosure. The semiconductor package 22 has a structure similar to that of the semiconductor package 21. However, unlike the processor die 501 and support 504 in the semiconductor package 21, which are implemented using a composite wafer, the processor die 501' and support 504' under the processor die 501' together form a processor-diamond combination using the processes described in figures 24A-24C below.

Fig. 24A-24C show a process flow to create a BSPDN structure enhanced with an HTC support, such as a diamond interposer or an interposer based on other HTC materials without a second silicon substrate, so that the second silicon substrate side of the HTC-processor combination can be mounted and interconnected with the HBM DRAM stack with or without RDL. In fig. 24A, a first semiconductor substrate 71 is bonded to a second semiconductor substrate 72 through a pair of bonding layers 73 (e.g., dielectric bonding layers). Optionally, each of the first semiconductor substrate 71 and the second semiconductor substrate 72 includes a respective buffer stop layer 71B or 72B between the active region and the bulk region. In the first semiconductor substrate 71, the buried power rails 711 may be formed prior to creating the front-end-of-line (FEOL) structure 712 of the processor IC, and the semiconductor will later be stacked with the local interconnects 713, the intermediate interconnects 714, and optionally RDLs (not shown in fig. 24A) or bonding layers. The local interconnect 713 and the intermediate interconnect 714 may be part of a back-end-of-line (BEOL) structure of the processor IC having distinguishable line widths and spacings. Since the first semiconductor substrate 701 for fabricating the processor IC will then be thinned to less than 5 μm by a suitable wafer grinding/thinning operation, chemical Mechanical Polishing (CMP) operation, dry and/or wet etching operation, or a combination thereof, while leaving the active silicon region and power rails intact, the second semiconductor substrate 72 may generally be attached to the intermediate interconnect 714 by a bonding layer 73 for structural integrity, as shown in fig. 24A.

In fig. 24B, the backside passivation layer 74 may be deposited by, for example, thermal oxidation or PECVD, and forms a silicon oxide layer. Next, nano TSV 751 is formed at the backside of the processor IC to establish electrical connection with buried power rail 711. Thermal vias 722 may be formed at various locations on the backside of the processor IC proximate to the heat source (e.g., proximate to FEOL structures 712, nano-TSVs 751, and/or buried source rails 711). Then, global interconnect 76 (and optionally RDL 77A) may be formed over nano TSV 751 and thermal via 722, with thermal via 722 connected to global interconnect (and RDL 77A) on the backside of the processor IC, which global interconnect 76 may be designed to provide power and signals to the processor IC through the backside of the processor IC with BSPDN. Global interconnect 76 is a generic term that includes power traces and signal traces that are connected to the FEOL 712 structure of the processor IC.

In fig. 24C, a first support 83, such as a diamond interposer or any other suitable HTC-based component, may be bonded to the processor IC with RDL 77A previously formed thereon based on copper hybrid bonding such as inter-oxide bonding, the first support 83 having RDL 77B on a first side facing the back side of the processor IC and RDL 77C on a second side opposite the first side. Here, the bonding layer connecting the support 83 to the processor IC may be a hybrid bonding layer. In some embodiments, the support 83 or diamond intermediary layer may possess multiple TDVs for different purposes. For example, thermal vias 83A in support 83 connecting RDL 77B and RDL 77C may be thermally coupled to thermal vias 722 previously formed in the processor IC. For another example, power and signal vias 83B (collectively power/signal vias) in support 83 that connect RDL 77B and RDL 77C are electrically connected to power and signal traces of global interconnect 76 and then to FEOL 712 structures of the processor IC. Contact terminals 78, such as micro bumps, may be formed on RDL 77C of support 83. In a next step, the second semiconductor substrate 72, including the bulk semiconductor, the buffer stop layer 72B, and the bonding layer 73, is removed by a suitable planarization and etching operation, and RDL 77D may then be formed on the intermediate interconnect 714 that is exposed after the removal of the second semiconductor substrate 72, as desired.

In some embodiments, for example, the processor die 501 'and support 504' in fig. 23 may form a BSPDN, such as by the process shown in fig. 24A-24C, and thus, the processor die 501 'and support 504' may have the same structure as the semiconductor substrate 71 and support 83. Moreover, in some embodiments, the die 201 and support 204 of the additional example shown in fig. 16 may also be formed by the processes shown in fig. 24A-24C.

Fig. 25 shows a fabrication operation for forming a thermal insulating layer or structure and/or a heat dissipating layer or structure in a suitable interconnect layer of the semiconductor packages described herein. The insulating layer or structure 951 may be formed adjacent to a predetermined active area, for example, between the memory cache 950A and the thermal core 950B of the processor IC, in the form of one or more trenches or holes andeither before or during FEOL processing of the IC. In some embodiments, the thermal isolation layer 901 may comprise a thermal metamaterial structure, such as silicon dioxide/graphene/Si/graphene/silicon dioxide generated during FEOL processing, or an ultra-thin (e.g., 2 nm) nanomaterial, such as MoSe deposited in the isolation trench by a vacuum process ₂ 、MoS ₂ WSe ₂ Graphene on heterostructures to achieve better thermal management. Thermal metamaterial structures (e.g. MoSe ₂ 、MoS ₂ WSe ₂ Graphene on heterostructures) can possess high thermal insulation properties, with greater than SiO at comparable thicknesses ₂ And has an effective thermal conductivity lower than air at room temperature. Additionally, the thermal barrier and/or heat dissipation layer 953 may be deposited in the BEOL structure in the form of conductive traces or three-dimensional metamaterial structures. The heat sink material may include graphene, carbon nanotubes, diamond, boron nitride, and/or boron arsenide. The insulating layer and/or heat sink layer 953 may then be patterned by a suitable photolithographic operation and molded out of a suitable dielectric material and wired to the thermal vias by a suitable photolithographic operation (e.g., via hole/trench patterning in the dielectric layer and contact metallization). 24C and 25, the insulating and/or heat dissipation layers illustrated in FIG. 25 may be formed in RDL 77D, the BEOL structures of the processor IC (e.g., local interconnect 713 and intermediate interconnect 714 proximate to the front side of the processor IC), the FEOL structures 712 of the processor IC, and/or the global interconnect 76 proximate to the back side of the processor IC.

Fig. 26 shows a semiconductor package 23 including a 3D IC structure according to another embodiment of the present disclosure. The semiconductor package 23 has a structure similar to the semiconductor package 22; however, the semiconductor package 23 further includes a circuit layer 5403 and a flexible circuit interconnect 5402. The circuit layer 5403 is electrically coupled to the control die 502 and the flex circuit interconnect 5402 is electrically connected to a laminate substrate or PCB 5401. The circuit layer 5403 is proximate to the heat sink 5503, with the flex circuit interconnect 5402 configured to provide power and signal distribution paths primarily to the control IC and memory die 502.

Fig. 27 shows a semiconductor package 24 including a 3D IC structure according to another embodiment of the present disclosure. The semiconductor package 24 has a structure similar to the semiconductor package 21; however, the processor die 601 is powered by a front side power supply network (FSPDN). That is, the processor die 601 may have its front side 601F (FEOL/BEOL side) disposed in close proximity to the support 503 and its back side 601B disposed farther from the support 503 than the front side 601F.

Fig. 28 shows a semiconductor package 25 including a 2.5D IC structure according to another embodiment of the present disclosure. The semiconductor package 25 has a structure similar to the semiconductor package 24. That is, both semiconductor package 25 and semiconductor package 24 are powered by the FSPDN; however, unlike the 3D IC structure employed by semiconductor package 24, the processor die 701 and the DRAM stack including die 702 in semiconductor package 25 are disposed side-by-side on support 703 in a 2.5D IC structure.

Fig. 29 shows a semiconductor package 26 including a 2.5D IC structure according to another embodiment of the present disclosure. The semiconductor package 26 has a structure similar to the semiconductor package 25; however, the processor die 701' may be constructed from a silicon-diamond composite wafer such that the backside 701B ' (opposite the FEOL/BEOL side) of the silicon layer of the processor die 701' may be thermally coupled to the diamond support 704, thereby facilitating heat dissipation.

Fig. 30 shows a semiconductor package 27 including a 2.5D IC structure according to another embodiment of the present disclosure. The semiconductor package 27 has a structure similar to the semiconductor package 25; however, semiconductor package 27 employs a processor die 801 with a BSPDN. In this case, the processor die 801 may have its backside 801B disposed in close proximity to the support 803 and its front side 801F disposed farther from the support 803 than the backside 801B.

As shown in fig. 30, processor die 801 may be built based on silicon, however, the disclosure is not so limited. Fig. 31 shows a semiconductor package 28 including a 2.5D IC structure according to another embodiment of the present disclosure. The semiconductor package 28 has a structure similar to the semiconductor package 27; however, the processor die 801 'with BSPDN may be bonded to the diamond support 804' by, for example, copper hybrid bonding. That is, the semiconductor package 28 employs a structure of a processor-diamond combination that may be formed by the process flows previously shown in fig. 24A-24C.

Fig. 32 shows a semiconductor package 29 including a 2.5D IC structure according to another embodiment of the present disclosure. The semiconductor package 29 has a structure similar to the semiconductor package 28. For example, processor die 801 'and diamond support 804' in semiconductor package 28 and processor die 961 and support 964 in semiconductor package 29 form two processor-diamond combinations with BSPDN. However, in semiconductor package 29, two DRAMs 962 are partially stacked on processor die 961. In particular, DRAM 962 is disposed over processor die 901 and diamond spacer 967 having TDV 9671 formed therein. In addition, diamond spacers 967 and processor-diamond composite structures (including processor die 961 and support 964) are disposed on another HTC support 963, with conductive traces formed therein, and thus, signal and power transmission and heat dissipation down can be achieved through support 963. The support 963 may include an interposer comprised of a material having a thermal conductivity greater than that of the silicon interposer material. For example, the support 963 may include a diamond interposer with a TDV formed therein in order to improve cooling efficiency. In some embodiments, the support 963 may be composed of diamond, silicon, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or combinations thereof.

The 3D IC and 2.5D IC structures described herein all allow for double-sided or multi-sided cooling from the top and bottom sides of the 3D IC and 2.5D IC structures, while some 3D IC structures enable cross-die, double-sided or multi-sided signal and power transfer, which can now be directly supplied to the die above and all other dies in the die stack from both the bottom die and/or interposer supporting the bottom die on the bottom side, and can be from the top side of the 3D IC (e.g., to the control IC) to the die below the 3D IC, as compared to conventional single-sided interconnects (only supplied to the die directly above and then to the further die above it from the top die, one die at a time).

In addition, in the same packaging level of the 3D stack, the dies shown in the figures of the present disclosure may be single dies or a combination of ICs or chiplets interconnected by, for example, wafer level fan-out 2.5D ICs and 3D IC processes. Each level may also incorporate passive and other active components. In all cases, HTC TIMs may help alleviate thermal problems.

Also, in all figures, when micro bumps are used, a non-conductive paste/film is needed (but not shown) to fill the gap between the two components of the flip chip bond. Furthermore, to achieve finer pitch, the flip-chip bumps, in particular, between two ICs, may be replaced by copper hybrid bonding. The disclosed 3D IC and 2.5D IC structures may also be molded (which may not be shown in the figures) to enhance the structural integrity of these structures.

Another aspect of the present disclosure provides a semiconductor package. The semiconductor package includes a processor die, a first High Thermal Conductivity (HTC) structure, a plurality of memory dies, and a control die, and a second HTC structure. The processor die has a front side and a back side. The first HTC structure is disposed directly below the processor die and is thermally coupled to the processor die. The thermal conductivity of the first HTC structure is greater than the thermal conductivity of the processor die. The memory die and the control die are stacked over the processor die. The second HTC structure is disposed between the processor die and a control die or between adjacent memory dies. The thermal conductivity of the second HTC structure is greater than the thermal conductivity of the processor die.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above may be implemented in different methods and replaced by other processes, or a combination thereof.

Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. One of ordinary skill in the art will readily appreciate from the disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A semiconductor package, comprising:

a first die having a front side and a back side; and

A first support disposed directly below and thermally coupled to the first die, wherein a thermal conductivity of the first support is greater than a thermal conductivity of the first die.

2. The semiconductor package of claim 1, wherein the first support comprises an interposer comprised of a material having a thermal conductivity greater than silicon, and wherein the interposer has a cross-sectional width greater than or substantially equal to the first die.

3. The semiconductor package of claim 1, wherein the first support and the first die are combined to form a composite layer having at least one via through the first die and the first support.

4. The semiconductor package of claim 1, wherein the first support is comprised of diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, or silicon carbide.

5. The semiconductor package of claim 1, wherein the back side of the first die is positioned in close proximity to the first support and a front side of the first die is farther from the first support than the back side, and further comprising:

global interconnects disposed on the back side of the first die; and

A first redistribution layer RDL disposed on the global interconnect; and

A second RDL on a first side of the first support facing the first die;

Wherein the first die and the first support are joined by the first RDL and the second RDL.

6. The semiconductor package of claim 5, further comprising:

a third RDL on a second side of the first support opposite the first side;

a first thermal via in the first support connecting the second RDL and the third RDL; and

A first power via and a first signal via in the first support connecting the second RDL and the third RDL.

7. The semiconductor package of claim 6, further comprising:

a buried power rail proximate to a front end of line FEOL structure of the first die;

a power trace and a signal trace in the global interconnect electrically connected to the buried power rail and the FEOL structure, respectively; and

A second thermal via proximate to the power trace and the signal trace in the global interconnect and the FEOL structure of the first die, wherein the second thermal via is thermally coupled to the first thermal via in the first support.

8. The semiconductor package of claim 6, further comprising:

A fourth RDL containing conductive traces over the front side of the first die,

wherein a heat spreading layer or insulating layer is formed in the fourth RDL, in a back-end-of-line BEOL structure proximate to the front side of the first die, in the global interconnect of the first die, or in a front-end-of-line FEOL structure proximate to the front side of the first die.

9. The semiconductor package of claim 1, further comprising:

a plurality of second dies stacked on or disposed side by side with the first die;

a structural member disposed side-by-side with the first die and the plurality of second dies; and

A heat sink disposed over the first die, the plurality of second dies, and the structural member,

wherein the structural member is thermally coupled with the first support and the heat sink, and the structural member possesses a thermal conductivity greater than the thermal conductivity of the first die.

10. The semiconductor package of claim 9, wherein the structural member comprises: (1) A plurality of intervening layers composed of a material having a thermal conductivity greater than that of silicon and having vias; (2) A spacer interconnect composed of a material having a thermal conductivity lower than silicon, with or without a via; (3) a vertical shelf of the heat sink; or a combination thereof.

11. The semiconductor package of claim 9, wherein the heat sink comprises a metal cap, an integrated heat sink, a planar heat sink, a fin heat sink, a thermally conductive plate, a cooling plate, a manifold, an interposer, or a combination thereof, wherein the heat sink is thermally coupled to the structural member with or without a thermal interface material TIM, the TIM having a thermal conductivity greater than silicon.

12. The semiconductor package of claim 9, further comprising:

a second support between the first die and one of the plurality of second dies or between adjacent second dies, wherein the second support comprises an interposer comprised of a material having a thermal conductivity greater than silicon; and

A through hole in the second support.

13. The semiconductor package of claim 12, further comprising:

a heat dissipation layer or thermal insulation layer in the respective interconnect structures of the first support, the second support, the plurality of second dies, or a combination thereof.

14. The semiconductor package of claim 12, wherein the second support further comprises:

a fifth RDL on a first side of the second support; and

A sixth RDL on a second side of the second support opposite the first side,

wherein the via electrically or optically connects the fifth RDL and the sixth RDL.

15. The semiconductor package of claim 1, wherein the back side of the first die is positioned in close proximity to the first support and the front side of the first die is farther from the first support than the back side, and further comprising:

a second support between the first die and one of the plurality of second dies or between adjacent second dies;

a structural member disposed side-by-side with the first die and the plurality of second dies, wherein the structural member has a thermal conductivity greater than the thermal conductivity of the first die;

a heat sink over the plurality of second dies and the first die, wherein the heat sink is thermally coupled to the structural member;

a carrier supporting the first die, the first support, the plurality of second dies, and the second support; and

A flexible circuit interconnect electrically connecting the carrier or the first support to a circuit layer proximate to the heat sink, wherein the flexible circuit interconnect is configured to provide power and signals to one of the second die or the front side of the first die.

16. A semiconductor package, comprising:

a processor die having a front side and a back side;

a first high thermal conductivity HTC structure disposed directly below and thermally coupled to the processor die, wherein a thermal conductivity of the first HTC structure is greater than a thermal conductivity of the processor die;

a plurality of memory dies and a control die stacked over the processor die; and

A second HTC structure between the processor die and a control die or between adjacent memory dies, wherein a thermal conductivity of the second HTC structure is greater than the thermal conductivity of the processor die.

17. The semiconductor package of claim 16, wherein the first HTC structure and the processor die are combined to form a composite wafer having at least one via through the processor die and the first HTC structure.

18. The semiconductor package of claim 16, further comprising:

a buried power rail proximate to a front end of line FEOL structure of the processor die; and

Power traces and signal traces, in interconnects proximate to the backside of the processor die,

wherein the power trace and the signal trace are electrically connected to the buried power rail and the FEOL structure, respectively, and are configured to provide power and signals to the processor die from the backside of the processor die.

19. The semiconductor package of claim 18, further comprising:

a spacer interconnect between the processor die and the plurality of memory dies and control die;

an air gap defined by the spacer interconnect, the processor die, and the control die, wherein the control die controls the interconnection between the processor die and the memory die;

a redistribution layer RDL containing conductive traces over the front side of the processor die; and

A heat spreading layer or insulating layer is formed in the RDL, in a back-end-of-line BEOL structure proximate to the front side of the processor die, or in a front-end-of-line FEOL structure proximate to the front side of the processor die.

20. The semiconductor package of claim 18, further comprising:

a heat sink over the plurality of memory dies;

a laminate substrate supporting the processor die, the first HTC structure, the memory die, the control die, and the second HTC structure; and

A flexible circuit interconnect electrically connecting the laminate substrate or the first HTC structure to a circuit layer proximate to the heat spreader, wherein the flexible circuit interconnect is configured to provide power and signals to at least one of the front side of the processor die or the control die.