CN117766380A - Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure - Google Patents

Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure Download PDF

Info

Publication number
CN117766380A
CN117766380A CN202211121824.5A CN202211121824A CN117766380A CN 117766380 A CN117766380 A CN 117766380A CN 202211121824 A CN202211121824 A CN 202211121824A CN 117766380 A CN117766380 A CN 117766380A
Authority
CN
China
Prior art keywords
conductive layer
layer
target
tungsten
preset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211121824.5A
Other languages
Chinese (zh)
Inventor
张冲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202211121824.5A priority Critical patent/CN117766380A/en
Priority to PCT/CN2022/128181 priority patent/WO2024055389A1/en
Publication of CN117766380A publication Critical patent/CN117766380A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present disclosure relates to a semiconductor structure/gate structure fabrication method, a semiconductor structure and a gate structure, including: providing a substrate; forming a first conductive layer with a first preset thickness on a substrate by adopting a first preset deposition process; forming an initial second conductive layer with a second preset thickness on the first conductive layer by adopting a second preset deposition process; wherein, a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer; removing the initial second conductive layer and the film oxide layer by using a dry etching process under a preset bias environment, and forming a target second conductive layer with a third preset thickness on the first conductive layer under the condition that the cavity is not transferred; the third preset thickness is greater than or equal to the second preset thickness; and forming a main conductive layer on the target second conductive layer. The embodiment of the disclosure can at least avoid introducing a thin film oxide layer in the process of preparing the conductive layer, thereby reducing the resistance of the conductive layer and improving the performance and reliability of preparing the semiconductor product.

Description

Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure/gate structure manufacturing method, a semiconductor structure and a gate structure.
Background
A dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, generally comprising a plurality of repeated memory cell structures, wherein a storage capacitor in a single memory cell structure is connected to a source of a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and the transistor is controlled to be turned on or off by a voltage signal on the word line, so that data information stored in the capacitor is read through the bit line, or the data information is written into the capacitor through the bit line for storage.
For a single memory cell structure, the operating power consumption of the transistor directly affects the overall power consumption. Therefore, how to further reduce the operation power consumption of the transistors in the single memory cell structure becomes an important research for further reducing the power consumption of the semiconductor memory.
Disclosure of Invention
According to various embodiments of the present disclosure, a semiconductor structure/gate structure manufacturing method, a semiconductor structure, and a gate structure are provided, in which at least the introduction of a thin film oxide layer during the process of manufacturing a conductive layer can be avoided, thereby reducing the resistance of the conductive layer and improving the performance and reliability of manufacturing a semiconductor product.
According to some embodiments, a first aspect of the present disclosure provides a semiconductor structure fabrication method, comprising:
providing a substrate;
forming a first conductive layer with a first preset thickness on a substrate by adopting a first preset deposition process;
forming an initial second conductive layer with a second preset thickness on the first conductive layer by adopting a second preset deposition process; wherein, a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer;
removing the initial second conductive layer and the film oxide layer by using a dry etching process under a preset bias environment, and forming a target second conductive layer with a third preset thickness on the first conductive layer under the condition that the cavity is not transferred; the third preset thickness is greater than or equal to the second preset thickness;
and forming a main conductive layer on the target second conductive layer.
According to some embodiments, the predetermined bias voltage comprises an ac bias voltage and/or a radio frequency bias voltage.
According to some embodiments, the processing of the initial second conductive layer and the thin film oxide layer using a dry etching process in a pre-set bias environment includes:
and controlling the magnetron sputtering bias system to continuously etch for a preset time under the preset bias power so as to remove the initial second conductive layer and the film oxide layer.
According to some embodiments, a semiconductor structure fabrication method includes at least one of the following features: the third preset thickness is 3 nm-5 nm; the preset bias power is 50W-200W; the preset time is 2 s-5 s.
According to some embodiments, after transferring the cavity in a vacuum environment, a primary conductive layer is formed on the target secondary conductive layer.
According to some embodiments, a semiconductor structure fabrication method includes at least one of the following features: the first preset deposition process is a chemical vapor deposition process; the second predetermined deposition process is a physical vapor deposition process.
According to some embodiments, a semiconductor structure fabrication method includes at least one of the following features: the first preset thickness is 2 nm-5 nm; the second preset thickness is 2 nm-3 nm; the thickness of the main conductive layer is 25 nm-30 nm.
According to some embodiments, a semiconductor structure fabrication method includes at least one of the following features: the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer comprises titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or a combination thereof; the initial second conductive layer and the target second conductive layer are seed layers, and the materials of the initial second conductive layer and the target second conductive layer comprise titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof; the material of the main conductive layer comprises titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride or a combination thereof; the ions in the dry etching process include argon ions, krypton ions, xenon ions, or a combination thereof.
According to some embodiments, a second aspect of the present disclosure provides a method for manufacturing a gate structure, including:
providing a substrate, wherein the substrate comprises an active region;
forming a gate dielectric layer on the active region;
forming a first conductive layer with a first preset thickness on the gate dielectric layer by adopting a first preset deposition process;
forming an initial second conductive layer with a second preset thickness on the first conductive layer by adopting a second preset deposition process; wherein, a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer;
removing the initial second conductive layer and the film oxide layer by using a dry etching process under a preset bias environment, and forming a target second conductive layer with a third preset thickness on the first conductive layer under the condition that the cavity is not transferred; the third preset thickness is greater than or equal to the second preset thickness;
and forming a main conductive layer on the target second conductive layer, wherein the first conductive layer, the target second conductive layer and the main conductive layer form a gate conductive layer.
According to some embodiments, the predetermined bias voltage comprises an ac bias voltage and/or a radio frequency bias voltage.
According to some embodiments, removing the initial second conductive layer and the thin film oxide layer using a dry etching process in a preset bias environment includes:
And controlling the magnetron sputtering bias system to continuously etch for a preset time under the preset bias power so as to remove the initial second conductive layer and the film oxide layer.
According to some embodiments, the gate structure fabrication method includes at least one of the following features: the third preset thickness is 3 nm-5 nm; the preset bias power is 50W-200W; the preset time is 2 s-5 s.
According to some embodiments, after transferring the cavity in a vacuum environment, a primary conductive layer is formed on the target secondary conductive layer.
According to some embodiments, forming a gate dielectric layer over an active region includes: forming a gate trench in the active region; and forming a gate dielectric layer at the bottom and the side wall of the gate trench.
According to some embodiments, the gate structure fabrication method includes at least one of the following features: the gate dielectric layer comprises the following materials: aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof; the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer comprises titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or a combination thereof; the initial second conductive layer and the target second conductive layer are seed layers, and the materials of the initial second conductive layer and the target second conductive layer comprise titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof; the material of the main conductive layer comprises titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride or a combination thereof; the ions in the dry etching process include argon ions, krypton ions, xenon ions, or a combination thereof.
According to some embodiments, the first conductive layer is titanium silicide nitride, the initial second conductive layer is tungsten silicide, and the target second conductive layer is tungsten silicide.
According to some embodiments, a third aspect of the present disclosure provides a semiconductor structure, including a substrate, a first conductive layer, a target second conductive layer, and a main conductive layer, the first conductive layer formed on a surface of the substrate; the target second conductive layer is positioned on the surface of the first conductive layer far away from the substrate; the main conductive layer is positioned on the surface of the target second conductive layer far away from the substrate; wherein, no thin film oxide layer is arranged between the first conductive layer and the target second conductive layer.
According to some embodiments, the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or a combination thereof; the target second conductive layer is a seed layer, and the material of the target second conductive layer comprises titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof; the material of the main conductive layer comprises titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride or a combination thereof.
According to some embodiments, a fourth aspect of the present disclosure provides a gate structure, including a substrate, a gate dielectric layer, a first conductive layer, a target second conductive layer, and a main conductive layer, where the substrate includes an active region, the gate dielectric layer is formed on a surface of the active region, the first conductive layer is located on a surface of the gate dielectric layer away from the substrate, and the target second conductive layer is located on a surface of the first conductive layer away from the substrate; the main conductive layer is positioned on the surface of the target second conductive layer far away from the substrate; wherein, no thin film oxide layer is arranged between the first conductive layer and the target second conductive layer.
According to some embodiments, the gate dielectric layer is at least partially within the active region.
According to some embodiments, the gate structure includes at least one of the following features: the gate dielectric layer comprises the following materials: aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof; the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer comprises titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or a combination thereof; the target second conductive layer is a seed layer, and the material of the target second conductive layer comprises titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof; the material of the main conductive layer comprises titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride or a combination thereof.
The semiconductor structure manufacturing method, the semiconductor structure or the gate structure in the above embodiment at least includes the following advantages:
after forming a first conductive layer as a blocking layer or an adhesion layer on a substrate, forming an initial second conductive layer as a seed layer on the first conductive layer, wherein a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer, it is creatively proposed to remove the initial second conductive layer and the thin film oxide layer by a dry etching process under a preset bias environment, then forming a target second conductive layer thicker than the removed initial second conductive layer on the first conductive layer without transferring a cavity, and then forming a main conductive layer on the target second conductive layer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a top view of a semiconductor structure provided in one embodiment;
FIG. 2 is a schematic view showing a sectional structure taken along the direction cc 'and the direction ee' in FIG. 1;
FIG. 3 is a TEM schematic of a gate structure according to one embodiment;
FIG. 4 is a flow chart illustrating a method of fabricating a semiconductor structure according to an embodiment;
FIGS. 5-7 are schematic cross-sectional views of semiconductor structures obtained by different steps in a semiconductor structure fabrication process according to one embodiment;
FIG. 8 is a flow chart illustrating a method of fabricating a gate structure according to an embodiment;
FIGS. 9-12 are schematic cross-sectional views of semiconductor structures obtained by different steps in the method for fabricating a gate structure according to one embodiment;
FIG. 13 is a flow chart illustrating a method for fabricating a buried gate structure according to an embodiment;
FIGS. 14-18 are schematic cross-sectional views of semiconductor structures obtained by different processes in the fabrication of a buried gate structure according to one embodiment;
FIG. 19a is an EDX spectrum of a partial cross-sectional structure of a gate structure obtained by a transmission electron microscopy apparatus without employing the gate structure fabrication method of an embodiment of the present disclosure;
fig. 19b is an EDX spectrum of a partial cross-sectional structure of a gate structure obtained by a transmission electron microscopy apparatus after using the method for manufacturing a gate structure according to an embodiment of the present disclosure.
Reference numerals illustrate:
100. a substrate; 10. a substrate; 11. an array region; 12. a peripheral region; 20. a word line; 30. a bit line; 51. a gate dielectric layer; 52. a first conductive layer; 531. an initial second conductive layer; 532. a target second conductive layer; 54. a main conductive layer; 55. a protective layer; 56. a side wall structure; 60. a thin film oxide layer; 101. an active region; 501. a gate trench.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
Referring to fig. 1-2, the dram includes an array region 11 composed of a plurality of memory cells and a peripheral region 12 located at the periphery of the array region 11, and transistors of the peripheral region 12 are integrated with the array region 11 by etching through holes and forming a metal silicide layer. Specifically, each memory cell includes a capacitor and a transistor, the gate of the transistor is connected to the word line 20, the drain of the transistor is connected to the bit line 30, and the source of the transistor is connected to the capacitor. The transistor is controlled to be turned on or off by a voltage signal on the word line 20, and data information stored in the capacitor is read by the bit line 30, or the data information is written into the capacitor by the bit line 30 for storage.
In the related art, transistors in the peripheral region are formed in synchronization with memory cells in the array region, so as to reduce process steps and improve production efficiency. However, as semiconductor device structures continue to shrink, resulting in a decrease in the size of gate structures, and further reduction in the size of gate structures while ensuring that the memory performance of the devices does not decrease is one of the development goals that developers continue to pursue. However, during development, the applicant found that the presence of a thin film oxide layer 60 in the gate conductive layer by transmission electron microscopy (Transmission Electron Microscope image, TEM) of the gate structure can refer to fig. 3, resulting in an increase in the resistance of the gate structure and thus an increase in the overall power consumption of the device.
For the above reasons, the present disclosure aims to provide a semiconductor structure/gate structure manufacturing method, a semiconductor structure and a gate structure, which avoid introducing a thin film oxide layer in the process of manufacturing a conductive layer, thereby reducing the resistance of the conductive layer and improving the performance and reliability of manufacturing a semiconductor product.
Referring to fig. 4, an embodiment of the disclosure provides a method for manufacturing a semiconductor structure, including the following steps:
Step S210: providing a substrate;
step S220: forming a first conductive layer with a first preset thickness on a substrate by adopting a first preset deposition process;
step S230: forming an initial second conductive layer with a second preset thickness on the first conductive layer by adopting a second preset deposition process; wherein, a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer;
step S240: processing the initial second conductive layer and the film oxide layer by using a dry etching process under a preset bias environment, and forming a target second conductive layer with a third preset thickness on the first conductive layer under the condition that the cavity is not transferred; the third preset thickness is greater than or equal to the second preset thickness;
step S250: and forming a main conductive layer on the target second conductive layer.
As an example, please continue to refer to fig. 4, after forming a first conductive layer as a barrier layer or an adhesion layer on a substrate, forming an initial second conductive layer as a seed layer on the first conductive layer, and finding that a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer, it is creatively proposed to remove the initial second conductive layer and the thin film oxide layer by a dry etching process under a preset bias environment, then forming a target second conductive layer thicker than the removed initial second conductive layer on the first conductive layer without transferring a cavity, and then forming a main conductive layer on the target second conductive layer, thereby avoiding introducing the thin film oxide layer in the process of forming the conductive layer on the substrate, and reducing the resistance of the conductive layer and improving the performance and reliability of the prepared semiconductor product. Compared with the method for cleaning the thin film oxide layer of the substrate transfer cavity before forming the target second conductive layer, the method at least avoids equipment downtime caused during the transfer of the cavity, and therefore the utilization rate of equipment and the production efficiency of a production line are relatively improved.
As an example, referring to fig. 5, the substrate 100 provided in step S210 may include a substrate and/or an epitaxial structure, and one or more of a word line structure, a bit line structure, a capacitor structure, a transistor structure, and the like may be formed in the substrate or the epitaxial structure. In step S220, a first predetermined deposition process, such as a chemical vapor deposition process, may be used to form the first conductive layer 52 with a first predetermined thickness on the substrate 100. In step S230, a second predetermined deposition process, such as a physical vapor deposition process, is used to form an initial second conductive layer 531 with a second predetermined thickness on the first conductive layer 52; since the chemical vapor deposition process and the physical vapor deposition process are performed in different chambers, and the vacuum degree of the different chambers is different, oxygen atoms are collected on the first conductive layer 52 after the chamber is converted, and thus, after the initial second conductive layer 531 is formed, the thin film oxide layer 60 is formed between the initial second conductive layer 531 and the first conductive layer 52.
As an example, with continued reference to fig. 5, the first predetermined thickness may be 2nm to 5nm, e.g., the first predetermined thickness may be 2nm, 3nm, 4nm, 5nm, etc. As an example, the first conductive layer 52 may be a barrier layer or an adhesion layer to avoid damage to the upper surface of the substrate 100 during the subsequent deposition of the initial second conductive layer 531, and may increase the adhesion of the subsequent formation target second conductive layer 532 to reduce resistance and improve conductivity. The material of the first conductive layer 52 may include titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or combinations thereof, so as to meet the actual requirements of various application scenarios and reduce the cost and complexity of the preparation.
As an example, referring to fig. 6, in step S240, the initial second conductive layer 531 and the thin film oxide layer 60 are removed by a dry etching process under a predetermined bias environment, and a target second conductive layer 532 with a third predetermined thickness is formed on the first conductive layer 52 without transferring the cavity; the third preset thickness is greater than or equal to the second preset thickness, so that oxygen atoms are prevented from being accumulated again on the upper surface of the first conductive layer 52 during the cavity conversion process. As an example, the preset bias voltage may include one or both of an ac bias voltage and a radio frequency bias voltage, and a specific implementation form of the preset bias voltage may be determined according to actual requirements of a specific application scenario, so as to reduce manufacturing cost and complexity.
As an example, referring to fig. 6, in step S240, the magnetron sputtering bias system may be controlled to continue dry etching for a preset time under a preset bias power to remove the initial second conductive layer 531 and the thin film oxide layer 60, and form a target second conductive layer 532 with a third preset thickness on the first conductive layer 52 without transferring the cavity; the third preset thickness is greater than or equal to the second preset thickness.
As an example, with continued reference to fig. 6, the second predetermined thickness may be 2nm to 3nm, for example, the second predetermined thickness may be 2nm, 2.5nm, 3nm, or the like.
As an example, with continued reference to fig. 6, the ions in the dry etching process may include argon ions, krypton ions, xenon ions, or a combination thereof. The ions in the dry etching process, such as argon ions, bombard the surface of the initial second conductive layer 531 under the bias, so that the initial second conductive layer 531 and the thin film oxide layer 60 are etched away under the bombardment of the argon ions.
As an example, with continued reference to fig. 6, the preset bias power may be 50W to 200W, for example, the preset bias power may be 50W, 100W, 150W, 200W, or the like.
As an example, with continued reference to fig. 6, the preset time may be 2s to 5s, for example, the preset time may be 2s, 3s, 4s, 5s, or the like. By controlling the dry etching time under the condition of the preset bias power determination, the damage to the surface of the first conductive layer 52 is avoided while the initial second conductive layer 531 and the thin film oxide layer 60 are completely removed.
As an example, with continued reference to fig. 6, the initial second conductive layer 531 and the target second conductive layer 532 may be seed layers, and the materials of the initial second conductive layer 531 and the target second conductive layer 532 may include titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper, or the like, or combinations thereof, so as to reduce the resistance and conductive energy consumption of the overall conductive layer after the main conductive layer is formed subsequently.
As an example, referring to fig. 7, in step S250, the main conductive layer 54 may be formed on the target second conductive layer 532 by using a deposition process, so that the thin film oxide layer 60 is avoided from being introduced in the process of forming the conductive layer on the substrate 100, thereby reducing the resistance of the conductive layer and improving the performance and reliability of the semiconductor product.
As an example, referring to fig. 7, after the initial second conductive layer 531 and the thin film oxide layer 60 are etched away under the bombardment of the argon ions, the bias voltage in the magnetron sputtering bias system may be turned off and the dry etching may be stopped, and a target second conductive layer 532 with a third preset thickness may be deposited on the first conductive layer 52 in the same cavity; the third predetermined thickness is greater than or equal to the second predetermined thickness, and then the main conductive layer 54 may be formed on the target second conductive layer 532 after transferring the cavity in a vacuum environment. As an example, the structure obtained in step S240 may be transferred under a high vacuum environment between different cavities of the same apparatus, after which the main conductive layer 54 is deposited on the target second conductive layer 532, avoiding the introduction of a thin film oxide layer between the target second conductive layer 532 and the main conductive layer 54.
As an example, with continued reference to fig. 7, the third predetermined thickness may be 3nm to 5nm, for example, the third predetermined thickness may be 3nm, 3.5nm, 4.0nm, 4.5nm, 5nm, or the like.
As an example, referring to fig. 7, the material of the main conductive layer 54 may include titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride, or a combination thereof, so as to meet the actual requirements of a plurality of different application scenarios, and reduce the cost and complexity of the preparation.
Referring to fig. 8, an embodiment of the disclosure provides a method for manufacturing a gate structure, including the following steps:
step S211: providing a substrate, wherein the substrate comprises an active region;
step S212: forming a gate dielectric layer on the active region;
step S221: forming a first conductive layer with a first preset thickness on the gate dielectric layer by adopting a first preset deposition process;
step S230: forming an initial second conductive layer with a second preset thickness on the first conductive layer by adopting a second preset deposition process; wherein, a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer;
step S240: removing the initial second conductive layer and the film oxide layer by using a dry etching process under a preset bias environment, and forming a target second conductive layer with a third preset thickness on the first conductive layer under the condition that the cavity is not transferred; the third preset thickness is greater than or equal to the second preset thickness;
step S250: and forming a main conductive layer on the target second conductive layer, wherein the first conductive layer, the target second conductive layer and the main conductive layer form a gate conductive layer.
As an example, please continue to refer to fig. 8, after forming a first conductive layer as a barrier layer or an adhesion layer on a gate dielectric layer, forming an initial second conductive layer as a seed layer on the first conductive layer, wherein a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer, so creatively proposes to remove the initial second conductive layer and the thin film oxide layer by using a dry etching process under a preset bias environment, then form a thicker target second conductive layer on the first conductive layer than the removed initial second conductive layer without transferring a cavity, and then form a main conductive layer on the target second conductive layer, wherein the first conductive layer, the target second conductive layer and the main conductive layer form the gate conductive layer, thereby avoiding introducing the thin film oxide layer in the process of forming the gate conductive layer, reducing the resistance of the gate conductive layer, and improving the performance and reliability of the prepared semiconductor product.
As an example, referring to fig. 9, a first type doped well region (not shown) may be formed in the substrate 10, and the substrate 10 may be formed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 10 may have a single-layer structure or a multilayer structure. For example, the substrate 10 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 10 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate 10 should not limit the scope of the present disclosure. An ion implantation process may be used to implant P-type ions into the substrate 10 to form a first type doped well region (not shown), which may include, but is not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF 2) ions, indium (In) ions, and the like.
As an example, referring to fig. 9, a shallow trench isolation structure (Shallow Trench Isolation, STI for short) may be formed in the substrate 10, and the shallow trench isolation structure may isolate a plurality of active regions 101 in the substrate 10 that are arranged at intervals. In embodiments in which substrate 10 comprises a P-type substrate, active region 101 may be formed by implanting N-type ions; correspondingly, in embodiments in which the silicon substrate comprises an N-type substrate, the active region 101 may be formed by implanting P-type ions. Accordingly, the active region may be a P-type active region or an N-type active region. The P-type active region may form an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) device and the N-type active region may form a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, PMOS) device. The N-type impurity ions may include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, antimony (Sb) ions, and the like.
As an example, with continued reference to fig. 9, one or more of a word line structure, a bit line structure, a capacitor structure, a transistor structure, and the like may be formed within the substrate 10. In step S212, any one or more of an In-situ water vapor generation process (In-Situ Steam Generation, ISSG), an atomic layer deposition process, a plasma vapor deposition process, a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO), etc. may be used to form the gate dielectric layer 51 on the active region 101; gate dielectric layer 51 may be formed using a high-k dielectric constant (e.g., a dielectric constant greater than or equal to 3.9) material. For example, the material of gate dielectric layer 51 may include, but is not limited to, aluminum oxide (Al 2 O 3 ) Hafnium oxide (HfO) 2 ) Hafnium oxynitride (HfON), zirconium oxide (ZrO) 2 ) Tantalum oxide (Ta) 2 O 5 ) Titanium oxide (TiO) 2 ) Strontium titanium oxide (SrTiO) 3 ) Or a combination thereof.
As an example, referring to fig. 9, in step S221, a first conductive layer 52 with a first predetermined thickness may be formed on the gate dielectric layer 51 by a first predetermined deposition process, for example, a chemical vapor deposition process. In step S230, a second predetermined deposition process, such as a physical vapor deposition process, is used to form an initial second conductive layer 531 with a second predetermined thickness on the first conductive layer 52; since the chemical vapor deposition process and the physical vapor deposition process are performed in different chambers, and the vacuum degree of the different chambers is different, oxygen atoms are collected on the first conductive layer 52 after the chamber is converted, and thus, after the initial second conductive layer 531 is formed, the thin film oxide layer 60 is formed between the initial second conductive layer 531 and the first conductive layer 52.
As an example, with continued reference to fig. 9, the first predetermined thickness may be 2nm to 5nm, for example, the first predetermined thickness may be 2nm, 3nm, 4nm, 5nm, or the like. As an example, the first conductive layer 52 may be a barrier layer or an adhesion layer to avoid damage to the upper surface of the gate dielectric layer 51 during the subsequent deposition of the initial second conductive layer 531, and may increase adhesion of the target second conductive layer 532 to reduce resistance and improve conductivity. The material of the first conductive layer 52 may include titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or the like, or combinations thereof, so as to meet the actual requirements of various application scenarios and reduce the cost and complexity of the preparation.
As an example, referring to fig. 10 to 11, in step S240, the initial second conductive layer 531 and the thin film oxide layer 60 are removed by a dry etching process under a predetermined bias environment, and a target second conductive layer 532 with a third predetermined thickness is formed on the first conductive layer 52 without transferring the cavity; the third preset thickness is greater than or equal to the second preset thickness, so that oxygen atoms are prevented from being accumulated again on the upper surface of the first conductive layer 52 during the cavity conversion process. As an example, the preset bias voltage may include one or both of an ac bias voltage and a radio frequency bias voltage, and a specific implementation form of the preset bias voltage may be determined according to actual requirements of a specific application scenario, so as to reduce manufacturing cost and complexity.
As an example, referring to fig. 10-11, in step S240, the magnetron sputtering bias system may be controlled to continue dry etching for a preset time at a preset bias power to remove the initial second conductive layer 531 and the thin film oxide layer 60, and form the target second conductive layer 532 with a third preset thickness on the first conductive layer 52 without transferring the cavity; the third preset thickness is greater than or equal to the second preset thickness.
As an example, with continued reference to fig. 10, the second predetermined thickness may be 2nm to 3nm, for example, the second predetermined thickness may be 2nm, 2.5nm, 3nm, or the like.
As an example, with continued reference to fig. 10, the ions in the dry etching process may include argon ions, krypton ions, xenon ions, or a combination thereof. The ions in the dry etching process, such as argon ions, bombard the surface of the initial second conductive layer 531 under the bias, so that the initial second conductive layer 531 and the thin film oxide layer 60 are etched away under the bombardment of the argon ions.
As an example, with continued reference to fig. 10, the preset bias power may be 50W to 200W, for example, the preset bias power may be 50W, 100W, 150W, 200W, or the like. Too high a bias power can easily cause etching ions to damage the inner walls of the chamber and cause etching appendages to contaminate the upper surface of the first conductive layer 52; too low a bias power can easily result in too long an etch time or an unclean etch. In this embodiment, by setting the preset bias power to 50W-200W, the initial second conductive layer 531 and the thin film oxide layer 60 can be removed completely in a shorter time, and unnecessary etching damage to the cavity is avoided.
As an example, with continued reference to fig. 11, the preset time may be 2s to 5s, for example, the preset time may be 2s, 3s, 4s, 5s, or the like. By controlling the dry etching time under the condition of determining the preset bias power, the damage to the surface of the first conductive layer 52 is avoided while the initial second conductive layer 531 and the thin film oxide layer 60 are removed.
As an example, with continued reference to fig. 11, the initial second conductive layer 531 and the target second conductive layer 532 may be seed layers, and the materials of the initial second conductive layer 531 and the target second conductive layer 532 may include titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper, or combinations thereof, so as to reduce the resistance and conductive energy consumption of the overall conductive layer after the main conductive layer is formed later.
As an example, referring to fig. 11, in step S250, the main conductive layer 54 may be formed on the target second conductive layer 532 by using a deposition process, so that the thin film oxide layer 60 is avoided from being introduced during the process of forming the conductive layer on the substrate 100, thereby reducing the resistance of the conductive layer and improving the performance and reliability of the semiconductor product.
As an example, referring to fig. 11, after the initial second conductive layer 531 and the thin film oxide layer 60 are etched away under the bombardment of the argon ions, the bias voltage in the magnetron sputtering bias system may be turned off and the dry etching may be stopped, and a target second conductive layer 532 with a third preset thickness may be deposited on the first conductive layer 52 in the same cavity; the third predetermined thickness is greater than or equal to the second predetermined thickness, and then the main conductive layer 54 may be formed on the target second conductive layer 532 after transferring the cavity in a vacuum environment. As an example, the structure obtained in step S240 may be transferred under a high vacuum environment between different cavities of the same apparatus, after which the main conductive layer 54 is deposited on the target second conductive layer 532, avoiding the introduction of a thin film oxide layer between the target second conductive layer 532 and the main conductive layer 54.
As an example, with continued reference to fig. 11, the third predetermined thickness may be 3nm to 5nm, for example, the third predetermined thickness may be 3nm, 3.5nm, 4.0nm, 4.5nm, 5nm, or the like.
As an example, with continued reference to fig. 11, the material of the main conductive layer 54 may include titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride, or a combination thereof, so as to meet the actual requirements of a plurality of different application scenarios, and reduce the manufacturing cost and complexity.
As an example, referring to fig. 12, after forming the main conductive layer 54, a deposition process may be used to form a protective layer 55, the protective layer 55 covering the gate dielectric layer 51, the first conductive layer 52, the target second conductive layer 532, and the main conductive layer 54; sidewall structures 56 are then formed on the sidewalls of the protective layer 55. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process, and Spin-on Dielectric (SOD) process.
Referring to fig. 13-18, an embodiment of the disclosure provides a method for manufacturing a buried gate structure, the method comprising the steps of:
Step S211: providing a substrate 10 including an active region 101 therein;
step S213: forming a gate trench 501 in the active region 101, and forming a gate dielectric layer 51 at the bottom and sidewalls of the gate trench 501;
step S221: forming a first conductive layer 52 with a first preset thickness on the gate dielectric layer 51 by adopting a first preset deposition process;
step S230: forming an initial second conductive layer 531 of a second predetermined thickness on the first conductive layer 52 using a second predetermined deposition process; wherein, a thin film oxide layer 60 is formed between the initial second conductive layer 531 and the first conductive layer 52;
step S240: removing the initial second conductive layer 531 and the thin film oxide layer 60 by using a dry etching process under a preset bias environment, and forming a target second conductive layer 532 of a third preset thickness on the first conductive layer 52 without transferring the cavity; the third preset thickness is greater than or equal to the second preset thickness;
step S250: a main conductive layer 54 is formed on the target second conductive layer 532, and the first conductive layer 52, the target second conductive layer 532, and the main conductive layer 54 constitute a gate conductive layer.
As an example, referring to fig. 13, after forming the first conductive layer 52 as a barrier layer or an adhesion layer on the gate dielectric layer 51, and then forming the initial second conductive layer 531 as a seed layer on the first conductive layer 52, it is creatively proposed to remove the initial second conductive layer 531 and the thin film oxide layer 60 by a dry etching process under a preset bias environment, then form a thicker target second conductive layer 532 on the first conductive layer 52 than the removed initial second conductive layer 531 without transferring a cavity, and then form the main conductive layer 54 on the target second conductive layer 532, wherein the first conductive layer 52, the target second conductive layer 532 and the main conductive layer 54 form the gate conductive layer, so that the introduction of the thin film oxide layer in the process of forming the gate conductive layer is avoided, thereby reducing the resistance of the gate conductive layer and improving the performance and reliability of the semiconductor product. In addition, in the process of removing the initial second conductive layer 531 and the thin film oxide layer 60 by using the dry etching process under the preset bias environment, a downward electric field is formed near the substrate 10, dry etching ions are attracted to bombard the gate dielectric layer 51 downward, and the gate dielectric layer 51 at the bottom of the gate trench 501 is bombarded on the side wall of the gate trench 501, so that the uniformity of the thickness of the gate dielectric layer 51 can be improved, the uniformity of the thickness of the first conductive layer 52 and the target second conductive layer 532 which are formed subsequently is improved, and the performance and reliability of the semiconductor product are further improved.
As an example, referring to fig. 14 to 15, in step S213, an etching process may be used to form a gate trench 501 In the active region 101, and any one or more of an In-situ vapor deposition process (In-Situ Steam Generation, ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO) may be used to form a gate dielectric layer 51 at the bottom and the sidewalls of the gate trench 501. The etching process may include, but is not limited to, a dry etching process and/or a wet etching process. The dry etching process may include, but is not limited to, one or more of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), high-concentration plasma etching (HDP), and the like.
As an example, with continued reference to fig. 15, gate dielectric layer 51 may be formed using a high-k dielectric constant (e.g., a dielectric constant greater than or equal to 3.9) material. For example, the material of gate dielectric layer 51 may include, but is not limited to, aluminum oxide (Al 2 O 3 ) Hafnium oxide (HfO) 2 ) Hafnium oxynitride (HfON), zirconium oxide (ZrO) 2 ) Tantalum oxide (Ta) 2 O 5 ) Titanium oxide (TiO) 2 ) Strontium titanium oxide (SrTiO) 3 ) Etc., or a combination thereof.
As an example, referring to fig. 16, in step S221, a first conductive layer 52 with a first predetermined thickness may be formed on the gate dielectric layer 51 by a first predetermined deposition process, for example, a chemical vapor deposition process. In step S230, a second predetermined deposition process, such as a physical vapor deposition process, is used to form an initial second conductive layer 531 with a second predetermined thickness on the first conductive layer 52; since the chemical vapor deposition process and the physical vapor deposition process are performed in different chambers, and the vacuum degree of the different chambers is different, oxygen atoms are collected on the first conductive layer 52 after the chamber is converted, and thus, after the initial second conductive layer 531 is formed, the thin film oxide layer 60 is formed between the initial second conductive layer 531 and the first conductive layer 52.
As an example, with continued reference to fig. 16, the first predetermined thickness may be 2nm to 5nm, for example, the first predetermined thickness may be 2nm, 3nm, 4nm, 5nm, or the like. As an example, the first conductive layer 52 may be a barrier layer or an adhesion layer to avoid damage to the upper surface of the gate dielectric layer 51 during the subsequent deposition of the initial second conductive layer 531, and may increase adhesion of the target second conductive layer 532 to reduce resistance and improve conductivity. The material of the first conductive layer 52 may include titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or the like, or combinations thereof, so as to meet the actual requirements of various application scenarios and reduce the cost and complexity of the preparation.
As an example, referring to fig. 16 to 17, in step S240, the initial second conductive layer 531 and the thin film oxide layer 60 are removed by a dry etching process under a predetermined bias environment, and a target second conductive layer 532 with a third predetermined thickness is formed on the first conductive layer 52 without transferring the cavity; the third preset thickness is greater than or equal to the second preset thickness, so that oxygen atoms are prevented from being accumulated again on the upper surface of the first conductive layer 52 during the cavity conversion process. As an example, the preset bias voltage may include one or both of an ac bias voltage and a radio frequency bias voltage, and a specific implementation form of the preset bias voltage may be determined according to actual requirements of a specific application scenario, so as to reduce manufacturing cost and complexity.
As an example, referring to fig. 16-17, in step S240, the magnetron sputtering bias system may be controlled to continue dry etching for a preset time at a preset bias power to remove the initial second conductive layer 531 and the thin film oxide layer 60, and form the target second conductive layer 532 with a third preset thickness on the first conductive layer 52 without transferring the cavity; the third preset thickness is greater than or equal to the second preset thickness.
As an example, with continued reference to fig. 16, the second predetermined thickness may be 2nm to 3nm, for example, the second predetermined thickness may be 2nm, 2.5nm, 3nm, or the like.
As an example, with continued reference to fig. 17, ions in the dry etching process may include at least one of argon ions, krypton ions, xenon ions, and the like. The ions in the dry etching process, such as argon ions, bombard the surface of the initial second conductive layer 531 under the bias, so that the initial second conductive layer 531 and the thin film oxide layer 60 are etched away under the bombardment of the argon ions.
As an example, with continued reference to fig. 17, the preset bias power may be 50W to 200W, for example, the preset bias power may be 50W, 100W, 150W, 200W, or the like. Too high a bias power can easily cause etching ions to damage the inner walls of the chamber and cause etching appendages to contaminate the upper surface of the first conductive layer 52; too low a bias power can easily result in too long an etch time or an unclean etch. In this embodiment, by setting the preset bias power to 50W-200W, the initial second conductive layer 531 and the thin film oxide layer 60 can be removed completely in a shorter time, and unnecessary etching damage to the cavity is avoided.
As an example, with continued reference to fig. 17, the preset time may be 2s to 5s, for example, the preset time may be 2s, 3s, 4s, 5s, or the like. By controlling the dry etching time under the condition of the preset bias power determination, the damage to the surface of the first conductive layer 52 is avoided while the initial second conductive layer 531 and the thin film oxide layer 60 are completely removed.
As an example, with continued reference to fig. 17, the second conductive layer 53 may be a seed layer, and the material of the initial second conductive layer 531 or the target second conductive layer 532 may include titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper, or the like, or a combination thereof, so as to reduce the resistance and conductive energy consumption of the overall conductive layer after the main conductive layer is subsequently formed.
As an example, referring to fig. 18, in step S250, a deposition process may be used to form the main conductive layer 54 on the target second conductive layer 532, where the main conductive layer 54, the target second conductive layer 532, the first conductive layer 52 and the gate dielectric layer 51 fill the gate trench 501. The present embodiment avoids the introduction of the thin film oxide layer 60 during the formation of the gate conductive layer on the gate dielectric layer 51, thereby reducing the resistance of the gate conductive layer and improving the performance and reliability of the semiconductor product.
As an example, referring to fig. 18, after the second conductive layer 53 and the thin film oxide layer 60 are etched away under the bombardment of the argon ions, the bias voltage in the magnetron sputtering bias system may be turned off and the dry etching may be stopped, and a target second conductive layer 532 with a third preset thickness may be deposited on the first conductive layer 52 in the same cavity; the third predetermined thickness is greater than or equal to the second predetermined thickness, and then the main conductive layer 54 may be formed on the target second conductive layer 532 after transferring the cavity in a vacuum environment. As an example, the structure obtained in step S240 may be transferred under a high vacuum environment between different cavities of the same apparatus, after which the main conductive layer 54 is deposited on the target second conductive layer 532, avoiding the introduction of a thin film oxide layer between the target second conductive layer 532 and the main conductive layer 54.
As an example, with continued reference to fig. 18, the third predetermined thickness may be 3nm to 5nm, for example, the third predetermined thickness may be 3nm, 3.5nm, 4.0nm, 4.5nm, 5nm, or the like.
As an example, with continued reference to fig. 18, the material of the main conductive layer 54 may include titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride, or a combination thereof, so as to meet the actual requirements of a plurality of different application scenarios, and reduce the manufacturing cost and complexity.
Although the respective steps in the flowcharts of fig. 4, 8, and 13 are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed as indicated by arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, while at least some of the steps of fig. 4, 8, and 13 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the execution of these sub-steps or stages in turn is not necessarily performed in turn, but may be performed alternately or alternately with at least some of the other steps or sub-steps of other steps.
As an example, referring to fig. 7, the present disclosure provides a semiconductor structure including a substrate 100, a first conductive layer 52, a target second conductive layer 532, and a main conductive layer 54, wherein the first conductive layer 52 is formed on a surface of the substrate 100; the target second conductive layer 532 is located on the surface of the first conductive layer 52 away from the substrate 100; the main conductive layer 54 is located on a surface of the target second conductive layer 532 remote from the substrate 100; wherein, there is no thin film oxide layer between the first conductive layer 52 and the target second conductive layer 532.
As an example, referring to fig. 5 to 7, after forming the first conductive layer 52 as a barrier layer or an adhesion layer on the substrate 100, forming the initial second conductive layer 531 as a seed layer on the first conductive layer 52, and since it is found that a thin film oxide layer is formed between the initial second conductive layer 531 and the first conductive layer 52, it is creatively proposed to remove the initial second conductive layer 531 and the thin film oxide layer by a dry etching process under a preset bias environment, then form a target second conductive layer 532 thicker than the removed initial second conductive layer on the first conductive layer without transferring a cavity, and then form the main conductive layer 54 on the target second conductive layer 532, thereby avoiding introducing the thin film oxide layer during the formation of the conductive layer on the substrate 100, and thus reducing the resistance of the conductive layer and improving the performance and reliability of the prepared semiconductor product.
As an example, with continued reference to fig. 7, the first conductive layer 52 is a barrier layer or an adhesion layer, and the material of the first conductive layer 52 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or a combination thereof; the target second conductive layer 532 is a seed layer, and the material of the target second conductive layer 532 includes titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper, or a combination thereof; the material of the main conductive layer 54 includes titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride, or a combination thereof.
As an example, referring to fig. 12, the disclosure provides a gate structure, which includes a substrate 10, a gate dielectric layer 51, a first conductive layer 52, a target second conductive layer 532, and a main conductive layer 54, wherein the substrate 10 includes an active region 101, the gate dielectric layer 51 is formed on a surface of the active region 101, the first conductive layer 52 is located on a surface of the gate dielectric layer 51 away from the substrate 10, and the target second conductive layer 532 is located on a surface of the first conductive layer 52 away from the substrate 10; the main conductive layer 54 is located on the surface of the target second conductive layer 532 remote from the substrate 10; wherein, there is no thin film oxide layer between the first conductive layer 52 and the target second conductive layer 532.
As an example, referring to fig. 9-12, after forming the first conductive layer 52 as a barrier layer or an adhesion layer on the gate dielectric layer 51, forming the initial second conductive layer 531 as a seed layer on the first conductive layer 52, and finding that a thin film oxide layer is formed between the initial second conductive layer 531 and the first conductive layer 52, it is creatively proposed to remove the initial second conductive layer 531 and the thin film oxide layer by a dry etching process under a preset bias environment, then forming a target second conductive layer 532 thicker than the removed initial second conductive layer on the first conductive layer 52 without transferring a cavity, and then forming a main conductive layer 54 on the target second conductive layer 532, where the first conductive layer 52, the target second conductive layer 532 and the main conductive layer 54 form the gate conductive layer, so that the introduction of the thin film oxide layer in the process of forming the gate conductive layer is avoided, thereby reducing the resistance of the gate conductive layer and improving the performance and reliability of the prepared semiconductor product.
In some embodiments, the gate dielectric layer is at least partially within the active region to reduce the volume of the gate structure.
As an example, referring to fig. 14-18, the disclosure provides a buried gate structure, which includes a substrate 10, a gate dielectric layer 51, a first conductive layer 52, a target second conductive layer 532, and a main conductive layer 54, wherein the substrate 10 includes an active region 101, a gate trench 501 is formed in the active region 101, the gate dielectric layer 51 is formed at a bottom and a sidewall of the gate trench 501, the first conductive layer 52 is located on a surface of the gate dielectric layer 51 away from the substrate 10, and the target second conductive layer 532 is located on a surface of the first conductive layer 52 away from the substrate 10; the main conductive layer 54 is located on the surface of the target second conductive layer 532 remote from the substrate 10; wherein, there is no thin film oxide layer between the first conductive layer 52 and the target second conductive layer 532.
As an example, referring to fig. 14 to 18, after forming the first conductive layer 52 as a barrier layer or an adhesion layer on the gate dielectric layer 51, forming the initial second conductive layer 531 as a seed layer on the first conductive layer 52, and finding that a thin film oxide layer is formed between the initial second conductive layer 531 and the first conductive layer 52, it is creatively proposed to remove the initial second conductive layer 531 and the thin film oxide layer by a dry etching process under a preset bias environment, then forming a target second conductive layer 532 thicker than the removed initial second conductive layer 531 on the first conductive layer 52 without transferring a cavity, and then forming a main conductive layer 54 on the target second conductive layer 532, where the first conductive layer 52, the target second conductive layer 532 and the main conductive layer 54 form the gate conductive layer, so that the introduction of the thin film oxide layer in the process of forming the gate conductive layer is avoided, thereby reducing the resistance of the gate conductive layer and improving the performance and reliability of the prepared semiconductor product. In addition, in the process of removing the initial second conductive layer 531 and the thin film oxide layer by using the dry etching process under the preset bias environment, a downward electric field is formed near the substrate 10, dry etching ions are attracted to bombard the gate dielectric layer 51 downward, and the gate dielectric layer 51 at the bottom of the gate trench is bombarded on the side wall of the gate trench, so that the uniformity of the thickness of the gate dielectric layer 51 can be improved, the uniformity of the thickness of the target second conductive layer 532 formed later is improved, and the performance and reliability of the semiconductor product are further improved.
As an example, with continued reference to fig. 14-18, the gate structure includes at least one of the following features: the material of the gate dielectric layer 51 includes: aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof; the first conductive layer 52 is a barrier layer or an adhesion layer, and the material of the first conductive layer 52 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride, or a combination thereof; the target second conductive layer 532 is a seed layer, and the material of the target second conductive layer 532 includes titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper, or a combination thereof; the material of the main conductive layer 54 includes titanium, tungsten, cobalt, nickel, tantalum titanate, tungsten silicide, tungsten nitride, or a combination thereof.
As an example, referring to fig. 19 a-19 b, fig. 19a is an energy dispersive X-Ray (Energy Dispersive X-Ray, EDX) spectrum of a local cross-section structure obtained by a transmission electron microscope device without using the gate structure manufacturing method in an embodiment of the present disclosure, fig. 19b is an EDX spectrum of a local cross-section structure obtained by a transmission electron microscope device with the gate structure manufacturing method in an embodiment of the present disclosure, wherein the material of the first conductive layer 52 is titanium silicide nitride, the material of the initial second conductive layer 531 and the target second conductive layer 532 may be tungsten silicide, the material of the main conductive layer 54 is tungsten, the material of the protective layer 55 is silicon nitride, and an oxide is present in the rectangular frame D between the first conductive layer 52 and the initial second conductive layer 531 in fig. 19a, which increases the resistance of the gate structure, resulting in an increase in the threshold voltage of the gate structure and a decrease in the stability and reliability of operation; in fig. 19b, no oxide exists between the target second conductive layer 532 and the main conductive layer 54, and the surface flatness of the first conductive layer 52, the target second conductive layer 532, and the main conductive layer 54 in fig. 19b is significantly better than in fig. 19a, so that not only is the introduction of a thin film oxide layer avoided during the formation of a gate conductive layer, but also the flatness of the interface between adjacent layers is improved, the resistance of the gate conductive layer is reduced, and the performance and reliability of the semiconductor product are improved.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.

Claims (21)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first conductive layer with a first preset thickness on the substrate by adopting a first preset deposition process;
forming an initial second conductive layer with a second preset thickness on the first conductive layer by adopting a second preset deposition process; wherein a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer;
Processing the initial second conductive layer and the film oxide layer by using a dry etching process under a preset bias environment, and forming a target second conductive layer with a third preset thickness on the first conductive layer under the condition that a cavity is not transferred; the third preset thickness is greater than or equal to the second preset thickness;
and forming a main conductive layer on the target second conductive layer.
2. The method of claim 1, wherein the predetermined bias voltage comprises an ac bias voltage and/or a rf bias voltage.
3. The method of claim 2, wherein the processing the initial second conductive layer and the thin film oxide layer in a pre-set bias environment using a dry etching process comprises:
and controlling the magnetron sputtering bias system to continuously etch for a preset time under preset bias power so as to remove the initial second conductive layer and the thin film oxide layer.
4. A method of fabricating a semiconductor structure according to claim 3, comprising at least one of the following features:
the third preset thickness is 3 nm-5 nm;
the preset bias power is 50-200W;
the preset time is 2 s-5 s.
5. The method of any of claims 1-4, wherein the main conductive layer is formed on the target second conductive layer after transferring the cavity in a vacuum environment.
6. The method of manufacturing a semiconductor structure according to any one of claims 1 to 4, comprising at least one of the following features:
the first preset deposition process is a chemical vapor deposition process;
the second preset deposition process is a physical vapor deposition process.
7. The method of manufacturing a semiconductor structure according to any one of claims 1 to 4, comprising at least one of the following features:
the first preset thickness is 2 nm-5 nm;
the second preset thickness is 2 nm-3 nm;
the thickness of the main conductive layer is 25 nm-30 nm.
8. The method of manufacturing a semiconductor structure according to any one of claims 1 to 4, comprising at least one of the following features:
the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer comprises titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or a combination thereof;
the initial second conductive layer and the target second conductive layer are seed layers, and the materials of the initial second conductive layer and the target second conductive layer comprise titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof;
The material of the main conductive layer comprises titanium, tungsten, cobalt, nickel, tantalum, titanium tantalum, tungsten silicide, tungsten nitride or a combination thereof;
the ions in the dry etching process include argon ions, krypton ions, xenon ions, or a combination thereof.
9. The method of claim 8, wherein the first conductive layer is titanium silicide nitride, the initial second conductive layer is tungsten silicide, and the target second conductive layer is tungsten silicide.
10. A method for fabricating a gate structure, comprising:
providing a substrate, wherein the substrate comprises an active region;
forming a gate dielectric layer on the active region;
forming a first conductive layer with a first preset thickness on the gate dielectric layer by adopting a first preset deposition process;
forming an initial second conductive layer with a second preset thickness on the first conductive layer by adopting a second preset deposition process; wherein a thin film oxide layer is formed between the initial second conductive layer and the first conductive layer;
the initial second conductive layer and the target second conductive layer are processed by a dry etching process under a preset bias environment, and a target second conductive layer with a third preset thickness is formed on the first conductive layer under the condition that a cavity is not transferred; the third preset thickness is greater than or equal to the second preset thickness;
And forming a main conductive layer on the initial second conductive layer and the target second conductive layer, wherein the first conductive layer, the target second conductive layer and the main conductive layer form a gate conductive layer.
11. The method of claim 10, wherein the predetermined bias voltage comprises an ac bias voltage and/or a rf bias voltage.
12. The method of claim 11, wherein the processing the initial second conductive layer and the target second conductive layer in the pre-set bias environment by a dry etching process comprises:
and controlling the magnetron sputtering bias system to continuously etch for a preset time under preset bias power so as to remove the initial second conductive layer and the thin film oxide layer.
13. The method of fabricating a gate structure of claim 12, comprising at least one of the following features:
the third preset thickness is 3 nm-5 nm;
the preset bias power is 50-200W;
the preset time is 2 s-5 s.
14. The method of any one of claims 10-13, wherein the main conductive layer is formed on the target second conductive layer after transferring the cavity in a vacuum environment.
15. The method of any one of claims 10-13, wherein forming a gate dielectric layer over the active region comprises:
forming a gate trench in the active region;
and forming a gate dielectric layer at the bottom and the side wall of the gate trench.
16. The method of fabricating a gate structure according to any one of claims 10 to 13, comprising at least one of the following features:
the gate dielectric layer comprises the following materials: aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof;
the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer comprises titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or a combination thereof;
the initial second conductive layer and the target second conductive layer are seed layers, and the materials of the initial second conductive layer and the target second conductive layer comprise titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof;
the material of the main conductive layer comprises titanium, tungsten, cobalt, nickel, tantalum, titanium tantalum, tungsten silicide, tungsten nitride or a combination thereof;
The ions in the dry etching process include argon ions, krypton ions, xenon ions, or a combination thereof.
17. A semiconductor structure, comprising:
a substrate;
the first conductive layer is formed on the surface of the substrate;
a target second conductive layer located on a surface of the first conductive layer remote from the substrate;
a main conductive layer located on a surface of the target second conductive layer away from the substrate;
wherein, no thin film oxide layer is arranged between the first conductive layer and the target second conductive layer.
18. The semiconductor structure of claim 17, comprising at least one of the following features:
the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer comprises titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or a combination thereof;
the target second conductive layer is a seed layer, and the material of the target second conductive layer comprises titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof;
the material of the main conductive layer includes titanium, tungsten, cobalt, nickel, tantalum, titanium tantalum, tungsten silicide, tungsten nitride, or a combination thereof.
19. A gate structure, comprising:
A substrate including an active region therein;
the gate dielectric layer is formed on the surface of the active region;
the first conductive layer is positioned on the surface of the gate dielectric layer, which is far away from the substrate;
a target second conductive layer located on a surface of the first conductive layer remote from the substrate;
a main conductive layer located on a surface of the target second conductive layer remote from the substrate;
wherein, no thin film oxide layer is arranged between the first conductive layer and the target second conductive layer.
20. The gate structure of claim 19, wherein the gate dielectric layer is at least partially within the active region.
21. The gate structure of claim 19 or 20, comprising at least one of the following features:
the gate dielectric layer comprises the following materials: aluminum oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof;
the first conductive layer is a barrier layer or an adhesion layer, and the material of the first conductive layer comprises titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium silicide nitride or a combination thereof;
the target second conductive layer is a seed layer, and the material of the target second conductive layer comprises titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof;
The material of the main conductive layer includes titanium, tungsten, cobalt, nickel, tantalum, titanium tantalum, tungsten silicide, tungsten nitride, or a combination thereof.
CN202211121824.5A 2022-09-15 2022-09-15 Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure Pending CN117766380A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202211121824.5A CN117766380A (en) 2022-09-15 2022-09-15 Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure
PCT/CN2022/128181 WO2024055389A1 (en) 2022-09-15 2022-10-28 Semiconductor structure/gate structure preparation method, semiconductor structure, and gate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211121824.5A CN117766380A (en) 2022-09-15 2022-09-15 Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure

Publications (1)

Publication Number Publication Date
CN117766380A true CN117766380A (en) 2024-03-26

Family

ID=90274123

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211121824.5A Pending CN117766380A (en) 2022-09-15 2022-09-15 Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure

Country Status (2)

Country Link
CN (1) CN117766380A (en)
WO (1) WO2024055389A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784105B1 (en) * 2003-04-09 2004-08-31 Infineon Technologies North America Corp. Simultaneous native oxide removal and metal neutral deposition method
US7030431B2 (en) * 2004-03-19 2006-04-18 Nanya Technology Corp. Metal gate with composite film stack
KR100775965B1 (en) * 2006-08-17 2007-11-15 삼성전자주식회사 Mos transistor of semiconductor device and method of manufacturing the same
KR100753558B1 (en) * 2006-08-21 2007-08-30 삼성전자주식회사 Cmos transistor of semiconductor device and method of manufacturing the same
JP5798865B2 (en) * 2011-09-29 2015-10-21 セイコーインスツル株式会社 Semiconductor device and manufacturing method thereof
KR102246880B1 (en) * 2015-02-10 2021-04-30 삼성전자 주식회사 Integrated circuit device and method of manufacturing the same

Also Published As

Publication number Publication date
WO2024055389A1 (en) 2024-03-21

Similar Documents

Publication Publication Date Title
TWI411107B (en) High performance mosfet
US7316960B2 (en) Strain enhanced ultra shallow junction formation
US6514828B2 (en) Method of fabricating a highly reliable gate oxide
US8790991B2 (en) Method and structure for shallow trench isolation to mitigate active shorts
US7737482B2 (en) Self-aligned strap for embedded trench memory on hybrid orientation substrate
CN106605303B (en) Metal Oxide Metal Field Effect Transistor (MOMFET)
US10985064B2 (en) Buried power and ground in stacked vertical transport field effect transistors
TW201009958A (en) Thin body silicon-on-insulator transistor with borderless self-aligned contacts
CN111564441B (en) Semiconductor structure and preparation method
US6180465B1 (en) Method of making high performance MOSFET with channel scaling mask feature
US9418864B2 (en) Method of forming a non volatile memory device using wet etching
WO2022122595A1 (en) Ncfets with complimentary capacitance matching using stacked n-type and p-type nanosheets
JP2007511907A (en) Low-power multichannel CMOSFET with fully depleted quantum well
CN117766380A (en) Semiconductor structure/gate structure preparation method, semiconductor structure and gate structure
KR20190092976A (en) Method for fabricating semiconductor device
US7807542B2 (en) Semiconductor device having storage node electrode with protection film thereon and method of fabricating the same
TW202207468A (en) Semiconductor device and method
CN107369648B (en) Method for manufacturing double-gate oxide layer
US7999300B2 (en) Memory cell structure and method for fabrication thereof
CN112420702A (en) Semiconductor device with a plurality of semiconductor chips
US20220238437A1 (en) Semiconductor structure and preparation method thereof
WO2023040470A1 (en) Vertical fet replacement gate formation with variable fin pitch
US11527616B2 (en) Vertical transport CMOS transistors with asymmetric threshold voltage
CN114784008B (en) Semiconductor structure and preparation method thereof
US20240194757A1 (en) Multilayer inner spacer for gate-all-around device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination