CN117765993A - Pseudo multi-port memory, method for accessing memory array and memory array - Google Patents

Abstract

The invention provides a pseudo multi-port memory, a method for accessing a memory array and the memory array. The memory array provided by the invention can comprise: a plurality of hierarchical bit lines, each of the hierarchical bit lines comprising: a first bit line wired on the first metal layer; a second bit line wired on a second layer metal different from the first layer metal; a plurality of memory cells, the plurality of memory cells comprising: a first group of memory cells coupled to the first bit line of the hierarchical bit line; a second set of memory cells coupled to the second bit lines of the hierarchical bit lines; the first set of memory cells and the second set of memory cells are located in the same column.

Description

Pseudo multi-port memory, method for accessing memory array and memory array

Technical Field

The present invention relates to memory design, and more particularly, to a pseudo multi-port memory and related memory access method. Each memory cell of the pseudo multi-port memory has a dual port memory cell structure and multiple enable pulses on the same word line (word line).

Background

Filter operations are often used in various image processing modules. With respect to filters in the image processing module, a cache (cache) storage element may be used to temporarily retain pixel data of the source image. Traditional approaches are to implement cache memory storage elements using single-port Static Random Access Memory (SRAM) bit cells (e.g., six transistor (6T) single-port SRAM bit cells) or dual-port (two-port) SRAM bit cells (e.g., 8T dual-port SRAM bit cells). In some applications, the image processing module needs to have a larger pixel output bandwidth. One conventional approach is to increase the pixel output bandwidth (i.e., read throughput) of the image processing module at the expense of hardware cost and chip area. Thus, there is a need for an innovative memory design that can improve read throughput with a suitable cost burden.

Disclosure of Invention

The invention provides a pseudo multi-port memory, a method for accessing a memory array and the memory array.

In one embodiment, the present invention provides a pseudo multi-port memory that may include: a memory array comprising a plurality of Read Word Lines (RWLs), a plurality of Write Word Lines (WWLs), and a plurality of memory cells, wherein each of the memory cells has a dual port memory cell structure and is coupled to one of the plurality of RWLs and the plurality of WWLs; a row decoder circuit for generating and outputting a RWL signal to a selected RWL, and for generating and outputting a WWL signal to a selected WWL, wherein a selected one of the plurality of memory cells is coupled to the selected RWL and the selected WWL; a time control circuit for generating and outputting a time control signal to the row decoder circuit, wherein the row decoder circuit is controlled by the time control signal such that the RWL signal has one enable pulse and such that the WWL signal has a plurality of enable pulses within one memory clock cycle of the pseudo multi-port memory; a sense amplifier circuit for performing a read operation on the selected memory cell when the enable pulse of the RWL signal enables the selected RWL, and for performing at least one read operation on the selected memory cell when at least one first enable pulse of the plurality of enable pulses included in the WWL signal enables the selected WWL; a write driver circuit for performing a write operation on the selected memory cell when a second enable pulse included in the plurality of enable pulses of the WWL signal enables the selected WWL.

In another embodiment, the present invention provides a method of accessing a memory array comprising a plurality of Read Word Lines (RWLs), a plurality of Write Word Lines (WWLs), and a plurality of memory cells, wherein each of the memory cells has a dual port memory cell structure and is coupled to one of the plurality of RWLs and the plurality of WWLs, the method comprising: performing a time control operation to generate and output a time control signal; performing a row decoding operation in accordance with the time control signal to generate and output a RWL signal for a selected RWL and a WWL signal for a selected WWL, wherein a selected one of the plurality of memory cells is coupled to the selected RWL and the selected WWL, and the RWL signal has one enable pulse and the WWL signal has a plurality of enable pulses during one memory clock cycle of the pseudo-multiport memory; performing a read operation on the selected memory cell when the enable pulse of the RWL signal enables the selected RWL; performing at least one read operation on the selected memory cell when at least one first enable pulse included in the plurality of enable pulses of the WWL signal enables the selected WWL; a write operation is performed on the selected memory cell when a second enable pulse included in the plurality of enable pulses of the WWL signal enables the selected WWL.

In another embodiment, the invention provides a memory array, which may include: a plurality of hierarchical bit lines, each of the hierarchical bit lines comprising: a first bit line wired on the first metal layer; a second bit line wired on a second layer metal different from the first layer metal; a plurality of memory cells, the plurality of memory cells comprising: a first group of memory cells coupled to the first bit line of the hierarchical bit line; a second set of memory cells coupled to the second bit lines of the hierarchical bit lines; the first set of memory cells and the second set of memory cells are located in the same column.

Drawings

FIG. 1 is a schematic diagram of a pseudo multi-port memory according to one embodiment of the invention.

Fig. 2 shows an example of the memory array 102 shown in fig. 1.

Fig. 3 is a graphical representation of waveforms of a plurality of signals used in accordance with the pseudo multi-port memory 100 shown in fig. 1 in accordance with one embodiment of the present invention.

Detailed Description

In the following description and claims, certain component terms are used. Those skilled in the art will appreciate that electronic device manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "connected" is intended to mean either a direct or an indirect electrical connection. Thus, if one device is connected to another device, that connection may be either a direct electrical connection or an indirect electrical connection via other devices and connections.

FIG. 1 is a schematic diagram of a pseudo multi-port memory according to one embodiment of the invention. The pseudo multi-port memory 100 includes a memory array 102 and peripheral circuitry 104. Peripheral circuitry 104 is used to control access (read (R)/write (W)) to memory array 102 and may include row decode circuitry (labeled "row decoder") 106, time control circuitry (labeled "time controller") 108, column decode circuitry (labeled "column decoder") 110, sense amplifier circuitry and write driver circuitry (labeled "sense_a, B/write driver") 112, and global read/write circuitry (labeled "global read/write") 114.

The memory array 102 includes a plurality of memory cells 116 arranged in a two-dimensional (2D) array having a plurality of rows and a plurality of columns. Fig. 2 shows an example of the memory array 102 shown in fig. 1. In this embodiment, each memory cell 116 may comprise a dual port SRAM cell structure for storing one bit (a bit), such as an 8T bit cell structure. Thus, the memory array 102 includes a plurality of read word lines RWL_0-RWL_N-1, a plurality of write word lines WWL_0-WWL_N-1, and a plurality of bit lines BL_0-BL_M-1, BL ' _0-BL ' _M-1, wherein the read word line RWL_j and the write word line WWL_j (j= {0,1, …, N-1 }) correspond to the same row of memory cells, and the two bit lines BL_k and BL ' _k (k= {0,1, …, M-1 }) correspond to the same column of memory cells. The 8T dual port SRAM bitcell structure may include a read bitline RBL and a pair of write bitlines WBL and WBLBIn this embodiment, for brevity, the read bit line RBL and the write bit lines WBL, WBLB +.>May be collectively referred to as the bit lines of the memory cells.

In this embodiment, a hierarchical (hierarchical) bit line structure may be employed to increase the density of memory cells and the access speed of the memory. For example, bit lines BL_0-BL_M-1 are routed on a first metal layer (e.g., M0), while bit lines BL '_0-BL' _M-1 are flight-bits (FBL) that are routed on a second metal layer (e.g., M2) that is different from the first metal layer (e.g., M0). For each memory cell column MC_0-MC_M-1, memory cells 116 located in the same memory cell column MC_k (k= {0,1, …, M-1 }) are categorized into a first group of memory cells 202 and a second group of memory cells 204, wherein the first group of memory cells 202 is coupled to bit line BL_k (k= {0,1, …, M-1 }) and the second group of memory cells 204 is coupled to bit line BL' _k (k= {0,1, …, M-1 }). Since all memory cells in the same memory cell column do not need to be coupled to the same unit line (single bit line) having a long length, each of the bit lines bl_k and BL' _k (k= {0,1, …, M-1 }) may have a shorter length, thereby improving the access speed of the memory. Furthermore, since all memory cells in the same memory cell column do not need to be coupled to the same unit line wired on one metal layer, using bit lines bl_k and BL' _k (k= {0,1, …, M-1 }) wired on different metal layers allows for higher memory cell densities. Since the impedance of bit line BL_k (k= {0,1, …, M-1 }) may be different from the impedance of bit line BL' _k (k= {0,1, …, M-1 }), an unbalanced FBL (or: non-FBL) load may be employed to compensate for speed and power. For example, the number of cells of the first set of memory cells 202 may be different than the number of cells of the second set of memory cells 204. However, this is for illustrative purposes only and should not be limiting of the invention.

The present invention is directed to implementing pseudo multi-port memories using memory cells having a dual port memory cell structure (e.g., an 8T dual port SRAM bit cell structure). For example, the present invention proposes to use a dual pump mechanism (double pump scheme) to implement pseudo-three port memory by using memory cells with a dual port memory cell structure (e.g., an 8T dual port SRAM bit cell structure). The row decode circuitry 106 shown in FIG. 1 is configured to decode a read address R-adr (particularly a first portion of address bits contained in the read address R-adr) and a write address W-adr (particularly a first portion of address bits contained in the write address W-adr) to generate and output read word line signals to a selected read word line RWL and to generate and output write word line signals to a selected write word line WWL, wherein selected ones of the memory cells 116 included in the memory array 102 are coupled to the selected read word line RWL and the selected write word line WWL. The column decode circuitry 110 is used to decode a read address R-adr (particularly a second portion of address bits contained in the read address R-adr) and a write address W-adr (particularly a second portion of address bits contained in the write address W-adr) to generate and output bit line signals to selected bit lines BL, with selected ones of the memory cells 116 included in the memory array 102 being coupled to the selected bit lines BL. For example, assuming that the read address R-adr and the write address W-adr both point to the same memory cell located at the intersection of the first memory cell row and the first memory column, the read word line signal generated by the row decoding circuit 106 is supplied to the read word line rwl_0 shown in fig. 2 (i.e., rwl=rwl_0), the write word line signal generated by the row decoding circuit 106 is supplied to the write word line wwl_0 shown in fig. 2 (i.e., wwl=wwl_0), and the bit line signal generated by the column decoding circuit 110 is supplied to the bit line bl_0 shown in fig. 2 (i.e., bl=bl_0).

The time control circuit 108 is configured to generate and output a time control signal (which may include one or more clock signals) TC to the row decode circuit 106. The row decode circuit 106 is controlled by the time control signal TC such that the read word line signal has one enable pulse in one memory clock cycle of the pseudo multi-port memory 100, and the write word line signal has a plurality of enable pulses in the memory clock cycle. Thus, within one memory clock cycle of the pseudo multi-port memory 100, the sense amplifier circuit (which is part of the circuit block 112 shown in fig. 1) is configured to perform a read operation on a selected memory cell when the selected read word line RWL is enabled by an enable pulse included in the read word line signal, and to perform at least one read operation on the selected memory cell when the selected write word line WWL is enabled by at least one first enable pulse in the enable pulse of the write word line signal. Further, within the same memory clock cycle of pseudo multi-port memory 100, the write driver circuit (which is part of circuit block 112 shown in FIG. 1) is configured to perform a write operation to the selected memory cell when the selected write word line WWL is enabled by a second one of the enable pulses of the write word line signal. For example, for a write word line signal provided to a selected write word line WWL, a first enable pulse for a read operation may be followed by a second enable pulse for a write operation.

Referring to fig. 2 and 3, fig. 3 is a diagram illustrating waveforms of a plurality of signals used in correspondence with the pseudo multi-port memory 100 shown in fig. 1 according to an embodiment of the present invention. Time controlThe control circuit 108 generates the time control signal TC from the chip select signals (e.g., RCS and WCS), the write enable signal (e.g., WWE), and the clock signals (e.g., RCK and WCK). During a read of memory clock cycle 1T (i.e., op=read), the read bit line RBL of the selected memory cell (which may have an 8T dual port SRAM bit cell structure) is precharged and then turned off (turn off), the read word line RWL of the selected memory cell is driven high by an enable pulse R-radr of the read word line signal generated by the time control circuit 108 and the sense amplifier of the sense amplifier circuit is activated (a_sae=1) to capture the value a_d0 (a_d0=mem (R-radr)) on the read bit line RBL and the captured value is output through the global read bit line GRBL; write bit line WBL, WBLB for selected memory cellsPrecharging is performed and then turned off, the write word line signal of the selected memory cell is driven high by the enable pulse R-wadr of the write word line signal generated by the time control circuit 108, and the sense amplifier (b_sae=1) of the sense amplifier circuit is activated to capture the write bit lines WBL, WBLBThe value B_D0 (B_D0=MEM (R-wadr)) and is via the data lines DL and DLB +.>Outputting the captured value, wherein the write bit lines WBL, WBLB + ->Can be reused as a read bit line.

During a write cycle (i.e., op=write) of the same memory clock cycle 1T, the write driver circuit drives write bit lines WBL, WBLB of the selected memory cellsAnd write word line WWL of the selected memory cell is driven high by an enable pulse W-wadr generated by time control circuit 108. As shown in FIG. 3, the selected storeThe memory cell performs two read operations and one write operation (i.e., 1W 2R) within one memory clock cycle 1T, thus forming a pseudo three-port memory cell (based on a dual-port memory cell structure) due to the use of the dual pump mechanism. It is noted that the write word line signal generated by the time control circuit 108 is not limited to include only two enable signals (one enable pulse for one read operation and the other enable pulse for one write operation). In practice, the write word line signal generated by the time control circuit 108 may be configured to have N (N>2) And (2) enable pulses including (N-1) enable pulses for (N-1) read operations and one enable pulse for a write operation.

In contrast to typical memory designs that achieve 4-fold read throughput using four 1W1R dual-port memories arranged in parallel, the proposed memory design only requires the use of two pseudo three-port memories (i.e., two 1W2R memories) to achieve 4-fold read throughput. Thus, an enhancement of read throughput can be achieved using the proposed pseudo-three port memory without suffering from the cost burden of typical memory designs.

The pseudo multi-port memory 100 may employ a hierarchical bit line structure (using FBL and non-FBL for pseudo multi-port memory cells on the same column) to increase the density of memory cells and the access speed of the memory. However, this is for illustrative purposes only and is not meant to limit the invention. As described above, the present invention focuses on a pseudo multi-port memory using memory cells having a dual-port memory cell structure. It should be noted that any pseudo multi-port memory design that enables each memory cell to function as a pseudo multi-port memory cell (e.g., a pseudo three-port memory cell) using the proposed pumping mechanism (e.g., a dual pumping mechanism) falls within the scope of the present invention.

In addition, any memory design that uses the proposed hierarchical bit line structure (using FBL and non-FBL for memory cells on the same column) to increase the density of memory cells and the access speed of the memory is within the scope of the present invention. In the above embodiment, the proposed hierarchical bit line structure is applied to each memory cell 116, each memory cell 116 being a pseudo three-port memory cell implemented based on a dual-port memory cell structure, wherein the write word line signal received by the memory cell has a plurality of enable pulses during one memory clock cycle. In a first alternative design, the proposed hierarchical bit line structure may be applied to each memory cell 116, which is typically a dual port memory. In a second alternative design, the proposed hierarchical bit line structure may be applied to each memory cell 116, which is typically a single-port memory. In a third alternative design, the proposed hierarchical bit line structure may be applied to each memory cell 116, each being a pseudo-dual port memory cell implemented based on a single port memory cell structure, where the word line signal received by the memory cell has multiple enable pulses (e.g., one enable pulse for a read operation and another enable pulse for a write operation) during one memory clock cycle. In a fourth alternative design, the proposed hierarchical bit line structure may be applied to memory cells 116 used by a register file.

Those skilled in the art will readily appreciate that many modifications and variations are possible in the apparatus and methods of the present invention while retaining the teachings of the invention. Accordingly, the description herein should be construed as limited only by the appended claims.

Claims (18)

1. A pseudo multi-port memory, comprising:

a memory array comprising a plurality of read word lines RWLs, a plurality of write word lines WWLs, and a plurality of memory cells, wherein each of the memory cells has a dual port memory cell structure and is coupled to one of the plurality of RWLs and WWLs;

a row decoder circuit for generating and outputting a RWL signal to a selected RWL, and for generating and outputting a WWL signal to a selected WWL, wherein a selected one of the plurality of memory cells is coupled to the selected RWL and the selected WWL;

a time control circuit for generating and outputting a time control signal to the row decoder circuit, wherein the row decoder circuit is controlled by the time control signal such that the RWL signal has one enable pulse and such that the WWL signal has a plurality of enable pulses within one memory clock cycle of the pseudo multi-port memory;

a sense amplifier circuit for performing a read operation on the selected memory cell when the enable pulse of the RWL signal enables the selected RWL, and for performing at least one read operation on the selected memory cell when at least one first enable pulse of the plurality of enable pulses included in the WWL signal enables the selected WWL;

a write driver circuit for performing a write operation on the selected memory cell when a second enable pulse included in the plurality of enable pulses of the WWL signal enables the selected WWL.

2. The pseudo-multi-port memory of claim 1, wherein the dual port memory cell structure is a dual port static random access memory SRAM cell structure.

3. The pseudo multi-port memory according to claim 2, wherein the dual port SRAM cell structure is an 8T bit cell structure.

4. The pseudo-multi-port memory according to claim 1, wherein the pseudo-multi-port memory is a pseudo-three port memory, the plurality of enable pulses of the WWL signal comprising only one first enable pulse for a read operation.

5. The pseudo-multi-port memory according to claim 1, wherein the plurality of memory cells comprises a first set of memory cells and a second set of memory cells, the first set of memory cells and the second set of memory cells being in a same column, the memory array further comprising:

a hierarchical bit line, the hierarchical bit line comprising:

a first bit line wired on the first metal layer and coupled with the first group of memory cells;

and a second bit line wired on a second metal layer different from the first metal layer and coupled with the second group of memory cells.

6. The pseudo-multi-port memory according to claim 5, wherein the number of cells of the first set of memory cells is different than the number of cells of the second set of memory cells.

7. A method of accessing a memory array comprising a plurality of read word lines, RWLs, a plurality of write word lines, WWLs, and a plurality of memory cells, wherein each of the memory cells has a dual port memory cell structure and is coupled to one of the plurality of RWLs and the plurality of WWLs, the method comprising:

performing a time control operation to generate and output a time control signal;

performing a row decoding operation in accordance with the time control signal to generate and output a RWL signal for a selected RWL and a WWL signal for a selected WWL, wherein a selected one of the plurality of memory cells is coupled to the selected RWL and the selected WWL, and the RWL signal has one enable pulse and the WWL signal has a plurality of enable pulses during one memory clock cycle of the pseudo-multiport memory;

performing a read operation on the selected memory cell when the enable pulse of the RWL signal enables the selected RWL;

performing at least one read operation on the selected memory cell when at least one first enable pulse included in the plurality of enable pulses of the WWL signal enables the selected WWL;

a write operation is performed on the selected memory cell when a second enable pulse included in the plurality of enable pulses of the WWL signal enables the selected WWL.

8. The method of claim 7, wherein the dual port memory cell structure is a dual port static random access memory SRAM cell structure.

9. The method of claim 8, wherein the dual port SRAM cell structure is an 8T bit cell structure.

10. The method of claim 7, wherein the plurality of enable pulses of the WWL signal includes only one first enable pulse for a read operation.

11. The method of claim 7, wherein the plurality of memory cells includes a first set of memory cells and a second set of memory cells, the first set of memory cells and the second set of memory cells being in a same column, the method further comprising:

accessing the first set of memory cells and the second set of memory cells through a hierarchical bit line, wherein the hierarchical bit line comprises:

a first bit line routed on the first metal layer and coupled with the first group of memory cells;

and a second bit line wired on a second metal layer different from the first metal layer and coupled with the second group of memory cells.

12. The method of claim 11, wherein the number of cells of the first set of memory cells is different from the number of cells of the second set of memory cells.

13. A memory array, comprising:

a plurality of hierarchical bit lines, each of the hierarchical bit lines comprising:

a first bit line wired on the first metal layer;

a second bit line wired on a second layer metal different from the first layer metal;

a plurality of memory cells, the plurality of memory cells comprising:

a first group of memory cells coupled to the first bit line of the hierarchical bit line;

a second set of memory cells coupled to the second bit lines of the hierarchical bit lines;

the first set of memory cells and the second set of memory cells are located in the same column.

14. The memory array of claim 13, wherein each of the memory cells is a dual port memory cell.

15. The memory array of claim 13, wherein each of the memory cells is a pseudo-three port memory cell having a structure of two port memory cells, the pseudo-three port memory cell receiving a write word line signal having a plurality of enable pulses during one memory clock cycle.

16. The memory array of claim 13, wherein each of the memory cells is a single-port memory cell.

17. The memory array of claim 13, wherein each of the memory cells is a pseudo-dual port memory cell having a structure of single port memory cells, the pseudo-dual port memory cell receiving a word line signal having a plurality of enable pulses during one memory clock cycle.

18. The memory array of claim 13, wherein the memory array is used by a register file.