CN117764996A - method for detecting defects of pins of intelligent SOT packaging chip - Google Patents
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Abstract
The invention discloses a method for detecting defects of pins of an intelligent SOT packaging chip, which comprises the following steps: building a chip side view pin dataset: shooting pins of a chip in a high-speed motion state from the side by an event camera to obtain pin images of the chip, judging whether the pin images of the chip are clear or not and marking the pin images of the chip after judging whether the pin images of the chip are complete or not, generating a pin image initial dataset of the chip, and expanding the pin image initial dataset to obtain a pin image dataset; constructing a pulse neural network to identify pin defects: constructing impulse neurons, constructing impulse neural networks, clustering and optimizing impulse neural networks, optimizing model parameters, and deploying impulse neural network models to identify pin states of single chips. The invention can identify the pin defects in the pin images of the SOT packaging chip under the condition of high-speed movement.
Description
Technical Field
the invention relates to the technical field of chip packaging defect identification, in particular to a method for detecting pin defects of an intelligent SOT packaging chip.
Background
An SOT package (Small Outline Transistor Package, small-sized transistor package) chip is a small-sized package type chip, which is generally used in the microelectronics field, and the outline of the SOT package chip is similar to a square shape, and a plurality of leads are disposed at the edges of the chip.
In the SOT package chip pin soldering process, the bad influence of SOT package chip pins on soldering quality is remarkable. The poor leads cause the problems of cold joint, lack welding and the like, and further cause poor performance of the chip in practical application, and even the chip is damaged. Therefore, how to effectively detect and identify the defects of the pins of the SOT package chip becomes a key link for improving the quality of the chip.
The traditional SOT packaging chip pin detection is that a static camera shoots a top view of a static SOT packaging chip pin, the pin in the top view is identified, the pin defect of the SOT packaging chip is further judged, the selected shooting angle adopts a overlooking angle of the chip, the shooting area can be enlarged, and the pin states of all SOT packaging chips can be rapidly judged. Most of the methods for identifying the defects of the pins of the SOT packaging chip are convolutional neural networks, so that the outline information of the SOT packaging chip can be better extracted.
However, in the overlooking angle of the traditional chip, the longitudinal bending defect of the SOT package chip pin is difficult to identify, misjudgment is easy to occur, meanwhile, the traditional camera is difficult to meet the requirement of assembly line detection under the high-speed condition, and precise identification cannot be realized under the condition that the chip pin and the camera move at a relatively high speed.
Disclosure of Invention
in view of this, the present invention provides a method for detecting defects of pins of an intelligent SOT package chip, which identifies defects of the SOT package chip under the condition of high-speed movement of the SOT package chip, and particularly, problems of longitudinal bending of pins.
the invention discloses a method for detecting pin defects of an intelligent SOT packaging chip, which comprises the following steps:
building a chip side view pin dataset: shooting pins of a chip in a high-speed motion state from the side by an event camera to obtain pin images of the chip, judging whether the pin images of the chip are clear or not and marking the pin images of the chip after judging whether the pin images of the chip are complete or not, generating a pin image initial dataset of the chip, and expanding the pin image initial dataset to obtain a pin image dataset;
Constructing a pulse neural network to identify pin defects: constructing impulse neurons, constructing impulse neural networks, clustering and optimizing impulse neural networks, optimizing model parameters, and deploying impulse neural network models to identify pin states of single chips.
Further, the method further comprises the following steps:
Optimizing the number of hidden layer neurons and neuron threshold values of the impulse neural network through a sparrow search algorithm so as to identify pin defects of the chip;
the optimizing the hidden layer neuron number and neuron threshold of the impulse neural network by the sparrow search algorithm comprises the following steps:
initializing a discoverer and a joiner: selecting super parameters of a pulse neural network, wherein the super parameters comprise the number of neurons in a hidden layer and a neuron threshold value, and initializing the positions of sparrows and the duty ratio of predators and jointers;
Calculating the fitness: carrying out normalized coding according to the super parameters of the impulse neural network, wherein the coded data can be mapped to the super parameters of the impulse neural network; the objective function selects the maximum value of the accuracy of the impulse neural network model, which represents the maximum function of the accuracy, and the model accuracy corresponding to the super parameter of the encoded impulse neural network represents the fitness of sparrow;
Updating the discoverer and enrollee locations: updating the positions of the discoverer and the joiner, moving towards a place with high accuracy of the impulse neural network model, and further updating the position of the predator;
updating the sparrow position: according to the fitness, the positions of all sparrows are timely adjusted, and the iterative parameters of the algorithm are adjusted;
And (3) loop iteration: and repeatedly and iteratively finding out the number of hidden layer neurons and neuron threshold values of the optimal impulse neural network model to obtain an optimal optimization result.
further, the shooting the pins of the chip in the high-speed motion state from the side by the event camera to obtain the pin image of the chip includes:
The event camera is positioned on the side surface of the chip in a high-speed motion state to shoot the pins of the chip, so that pin images of the chip are obtained; the pin image of the chip is a gray level image generated by accumulating pulse data of the chip pins for a period of time, and the event camera moves at a high speed relative to the SOT packaged chip in the shooting process.
Further, the determining whether the pin image of the chip is clear includes:
If the pin image of the chip is clear, judging whether the pin is complete, and if the pin image of the chip is not clear, marking the pin image of the chip as an invalid sample; judging whether the pin image of the chip is clear or not according to the standard that the pin feature and the background feature are obviously distinguished and no overlap exists between the pin features;
After marked as an invalid sample, the pin image of the chip does not participate in training of the model, and a new pin image of the chip needs to be shot again;
Judging whether the pin image of the chip is complete or not comprises the following steps:
If all pins in the pin image of the chip are complete, labeling the pin state of the pin image of the chip, and if the pin image of the chip has incomplete pins, labeling the pin image of the chip as an invalid sample; the standard of the complete pin is that the characteristics of a single pin are complete and the missing of the characteristics of the pin does not exist; after marked as an invalid sample, the pin image of the chip does not participate in training of the model, and a new pin image of the chip needs to be shot again.
further, the labeling the pin image of the chip to generate the initial data set of the pin image of the chip includes:
Firstly, dividing pin images of a chip: finding out the initial position of the edge of a pin in the pin image of the chip, and dividing the image according to the relative position proportion relation of the pins of the SOT packaging chip to form the pin image of a single chip of the pins of the SOT packaging chip; a large amount of noise and obvious SOT packaging chip pin outline characteristics exist in the pin image of the single chip;
Marking according to the pin states of the pin images of the single chip, wherein the pin states are respectively marked as a normal state, a twisted state, a longitudinal bending state and a transverse bending state; the twisting state is that the SOT package chip pins rotate along the axis; the longitudinal bending state is that the pins of the SOT packaging chip are bent inwards and outwards, and the bending direction is perpendicular to the pin image of the chip; the transverse bending state is that the pins of the SOT package chip are bent towards two sides.
Further, the expanding the initial data set of the pin image to obtain the data set of the pin image includes:
The pin images of the chips are turned over, rotated, sheared and randomly added with noise, but the pin characteristics of the chips are not destroyed, and the pin images of the single chips are randomly combined and expanded;
Forming a pin image dataset of the chip based on the pin image initial dataset of the expanded chip by adjusting the classification category; the classification category is the pin state corresponding to the pin image of the single chip; the adjustment targets are that the duty ratio of the torsion state, the longitudinal bending state and the transverse bending state is the same; the method for adjusting is to expand the pin images of the single chip classified into a twisted state, a vertical bending state and a horizontal bending state, and the method for expanding is to randomly shield, twist and locally change gray values of the pin images of the single chip.
further, the constructing impulse neurons includes:
At the initial time, performing numerical integration on the membrane potential by using an Euler method; firstly, determining the time interval of the Euler integral as a period of time before pulse generation, wherein the initial membrane potential is zero, and then carrying out gradual integral calculation along with the change of time to describe the dynamic change of the integral;
Comparing the integral value with the membrane potential in a time interval, and generating a pulse if the current membrane potential is greater than a neuron threshold value; after the pulse is generated, the decay factor is increased over a time interval to indicate that the rate of increase of the neuron membrane potential is slowed.
Further, constructing the impulse neural network is divided into an input layer, a hidden layer and an output layer;
The method for constructing the input layer comprises the following steps:
The neuron number of the input layer is the same as the product of the pixel height and the width of the pin image of the single chip, and the neuron value is the normalized gray value of the pin image of the single chip;
The method for constructing the hidden layer comprises the following steps:
the initial value of the neuron number of the first hidden layer adopts the average value of the neuron numbers of the input layer and the output layer, and the initial value of the neuron number of other hidden layers is consistent with the initial value of the neuron number of the first hidden layer; the input layer and the hidden layer are connected through synapses, and the synapses represent the connection weights among neurons;
The method for constructing the output layer comprises the following steps:
The output layer has 4 neurons, which respectively represent a normal state, a twisted state, a longitudinally bent state and a transversely bent state; the output layer and the hidden layer are directly connected through synapses; wherein the weight of the synaptic connection is used to adjust the pulse transmission intensity between two neurons.
Further, the method for clustering and optimizing the impulse neural network comprises the following steps:
Carrying out poisson coding on pin images of a single chip according to poisson distribution, and converting the pin images of the chip into pulse signals; extracting intervals of pulse signals as characteristic vectors of clusters, and converting each pulse signal into characteristic vectors with different characteristics;
Respectively calculating Euclidean distances of the two feature vectors; adopting hierarchical clustering to gather feature vectors with similar features into clusters;
Labeling each pulse data with a label of a cluster, dividing a pin image dataset of a chip into pin image sub-datasets of a plurality of chips according to the label, and respectively adjusting the number of hidden neurons and neuron thresholds in a pulse neural network model corresponding to the pin image sub-datasets of the chips.
Further, the optimizing model parameters includes: optimizing the super parameters of all impulse neural networks according to a sparrow search algorithm; the super-parameters include hidden layer neuron number and neuron threshold;
the deploying the impulse neural network model to identify pin states includes:
After training all the impulse neural networks, saving parameters of a model, deploying the parameters on a computing platform, and outputting a result to be a pin state in a pin image of a single chip generated by voting of a plurality of impulse neural networks; the voting method adopts weights to carry out voting weighting; if the finally identified pin state is a twisted state, a longitudinal bending state or a transverse bending state, the pin state and corresponding chip number information in the pin image of the single chip are recorded and an alarm is given.
Due to the adoption of the technical scheme, the invention has the following advantages: the pin defect of the SOT packaging chip under the condition of high-speed movement can be identified; the defects of longitudinal bending of the pins of the SOT packaging chip can be effectively identified by combining the pin images of the chip; the recognition time is saved, and the production line manufacturing efficiency of SOT packaging chips is improved.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments described in the embodiments of the present invention, and other drawings may be obtained according to these drawings for those skilled in the art.
FIG. 1 is a flow chart of intelligently detecting SOT package chip pin defects in an embodiment of the invention;
FIG. 2 is a flow chart of constructing SOT package chip pin data sets according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for constructing a pulsed neural network according to an embodiment of the present invention;
fig. 4 is a flowchart of a sparrow search algorithm according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples, wherein the examples are shown only in a partial, but not in all embodiments of the invention. All other embodiments obtained by those skilled in the art are intended to fall within the scope of the embodiments of the present invention.
referring to fig. 1, the present invention provides an embodiment of a method for detecting pin defects of an intelligent SOT package chip, which includes the following steps:
S1, constructing a pin image dataset of a chip: the method comprises the steps of shooting pins of a chip in a high-speed motion state from the side face through an event camera to obtain pin images of the chip, judging whether the pin images of the chip are clear or not and marking the pin images of the chip after judging whether the pin images of the chip are complete or not, generating a pin image initial dataset of the chip, and expanding the pin image initial dataset to obtain a pin image dataset.
referring to fig. 2, S1 specifically includes the following steps:
S101, acquiring a pin image of a chip through an event camera: the event camera is positioned on the side surface of the chip in a high-speed motion state to shoot the pins of the chip, so that pin images of the chip are obtained; the pin image of the chip is a gray level image generated by accumulating pulse data of the chip pins for a period of time, and the event camera moves at a high speed relative to the SOT packaging chip in the shooting process;
two event cameras are required to be aligned on the two sides of the SOT packaging chip on the side face of the shooting chip, and shooting of chip pins is completed together; the event cameras are fixedly arranged in an aligned manner relative to the SOT packaging chip in a high-speed movement mode, and the SOT packaging chip moves at a high speed through a production line;
S102, judging whether the pin image of the chip is clear: if the pin image of the chip is clear, judging whether the pin is complete, and if the pin image of the chip is not clear, marking the pin image of the chip as an invalid sample; judging whether the pin image of the chip is clear or not according to the standard that the pin feature and the background feature are obviously distinguished and no overlap exists between the pin features; after marked as an invalid sample, the pin image of the chip does not participate in training of the model, and a new pin image of the chip needs to be shot again;
S103, judging whether the pin image of the chip is complete: if all pins in the pin image of the chip are complete, labeling the pin state of the pin image of the chip, and if the pin image of the chip has incomplete pins, labeling the pin image of the chip as an invalid sample; the standard of the complete pin is that the characteristics of a single pin are complete and the missing of the characteristics of the pin does not exist; after marked as an invalid sample, the pin image of the chip does not participate in training of the model, and a new pin image of the chip needs to be shot again;
S104, labeling the pin image of the chip to generate an initial data set of the pin image of the chip: firstly, dividing pin images of a chip: finding out the initial position of the edge of a pin in the pin image of the chip, and dividing the image according to the relative position proportion relation of the pins of the SOT packaging chip to form the pin image of a single chip of the pins of the SOT packaging chip; a large amount of noise and obvious SOT packaging chip pin outline characteristics exist in the pin image of the single chip;
Marking according to the pin states of the pin images of the single chip, wherein the pin states are respectively marked as a normal state, a twisted state, a longitudinal bending state and a transverse bending state; the twisting state is that the SOT package chip pins rotate along the axis; the longitudinal bending state is that the pins of the SOT packaging chip are bent inwards and outwards, and the bending direction is perpendicular to the pin image of the chip; the transverse bending state is that the pins of the SOT package chip are bent towards two sides.
S105, expanding a pin image initial data set of the chip: the pin images of the chips are turned over, rotated, sheared and randomly added with noise, but the pin characteristics of the chips are not destroyed, and the pin images of the single chips are randomly combined and expanded;
Forming a pin image dataset of the chip based on the pin image initial dataset of the expanded chip by adjusting the classification category; the classification category is the pin state corresponding to the pin image of the single chip; the adjustment targets are that the duty ratio of the torsion state, the longitudinal bending state and the transverse bending state is the same; the method for adjusting is to expand the pin images of the single chip classified into a twisted state, a vertical bending state and a horizontal bending state, and the method for expanding is to randomly shield, twist and locally change gray values of the pin images of the single chip.
s2, constructing a pulse neural network to identify pin defects: constructing impulse neurons, constructing impulse neural networks, clustering and optimizing impulse neural networks, optimizing model parameters, and deploying impulse neural network models to identify pin states of single chips.
Referring to fig. 3, S2 specifically includes the following steps:
s201, the method for constructing the impulse neuron comprises the following steps:
At the initial time, performing numerical integration on the membrane potential by using an Euler method; firstly, determining the time interval of the Euler integral as a period of time before pulse generation, wherein the initial membrane potential is zero, and then carrying out gradual integral calculation along with the change of time to describe the dynamic change of the integral;
Comparing the integral value with the membrane potential in a time interval, and generating a pulse if the current membrane potential is greater than a neuron threshold value; after the pulse is generated, the decay factor is increased over a time interval to indicate that the rate of increase of the neuron membrane potential is slowed.
S202, constructing a pulse neural network: dividing a pulse neural network into an input layer, a hidden layer and an output layer;
The method for constructing the input layer comprises the following steps:
The neuron number of the input layer is the same as the product of the pixel height and the width of the pin image of the single chip, and the neuron value is the normalized gray value of the pin image of the single chip;
The method for constructing the hidden layer comprises the following steps:
the initial value of the neuron number of the first hidden layer adopts the average value of the neuron numbers of the input layer and the output layer, and the initial value of the neuron number of other hidden layers is consistent with the initial value of the neuron number of the first hidden layer; the input layer and the hidden layer are connected through synapses, and the synapses represent the connection weights among neurons;
The method for constructing the output layer comprises the following steps:
The output layer has 4 neurons, which respectively represent a normal state, a twisted state, a longitudinally bent state and a transversely bent state; the output layer and the hidden layer are directly connected through synapses; wherein the weight of the synaptic connection is used to adjust the pulse transmission intensity between two neurons.
s203, clustering optimization pulse neural network: the method for clustering and optimizing the impulse neural network comprises the following steps:
Carrying out poisson coding on pin images of a single chip according to poisson distribution, and converting the pin images of the chip into pulse signals; extracting intervals of pulse signals as characteristic vectors of clusters, and converting each pulse signal into characteristic vectors with different characteristics;
Respectively calculating Euclidean distances of the two feature vectors; adopting hierarchical clustering to gather feature vectors with similar features into clusters;
Labeling each pulse signal with a label of a cluster, dividing a pin image dataset of a chip into pin image sub-datasets of a plurality of chips according to the label, and respectively adjusting the number of hidden neurons and neuron thresholds in a pulse neural network model corresponding to the pin image sub-datasets of the chips.
s204, optimizing model parameters: optimizing super parameters of all impulse neural networks according to a sparrow search algorithm, wherein the super parameters comprise the number of hidden layer neurons and neuron thresholds;
S205, deploying a pulse neural network model to identify the pin state. After training all the impulse neural networks, saving parameters of a model, deploying the parameters on a computing platform, and outputting a result to be a pin state in a pin image of a single chip generated by voting of a plurality of impulse neural networks; the voting method adopts weights to carry out voting weighting; if the finally identified pin state is a twisted state, a longitudinal bending state or a transverse bending state, the pin state and corresponding chip number information in the pin image of the single chip are recorded and an alarm is given.
S3, optimizing a sparrow search algorithm: and optimizing the number of hidden layer neurons and neuron threshold values of the impulse neural network through a sparrow search algorithm so as to identify pin defects of the chip.
Referring to fig. 4, S3 includes the steps of:
s301, initializing a discoverer and a joiner: selecting super parameters of a pulse neural network, wherein the super parameters comprise the number of neurons in a hidden layer and a neuron threshold value, and initializing the positions of sparrows and the duty ratio of predators and jointers;
S302, calculating fitness: carrying out normalized coding according to the super parameters of the impulse neural network, wherein the coded data can be mapped to the super parameters of the impulse neural network; the objective function selects the maximum value of the accuracy of the impulse neural network model, which represents the maximum function of the accuracy, and the model accuracy corresponding to the super parameter of the encoded impulse neural network represents the fitness of sparrow;
S303, updating the positions of the discoverers and the joiners: updating the positions of the discoverer and the joiner, moving towards a place with high accuracy of the impulse neural network model, and further updating the position of the predator;
s304, updating sparrow positions: according to the fitness, the positions of all sparrows are timely adjusted, and the iterative parameters of the algorithm are adjusted;
s305, loop iteration: and repeatedly and iteratively finding out the number of hidden layer neurons and neuron threshold values of the optimal impulse neural network model to obtain an optimal optimization result.
finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the invention without departing from the spirit and scope of the invention, which is intended to be covered by the claims.
Claims (10)
1. The method for detecting the defects of the pins of the intelligent SOT packaging chip is characterized by comprising the following steps:
building a chip side view pin dataset: shooting pins of a chip in a high-speed motion state from the side by an event camera to obtain pin images of the chip, judging whether the pin images of the chip are clear or not and marking the pin images of the chip after judging whether the pin images of the chip are complete or not, generating a pin image initial dataset of the chip, and expanding the pin image initial dataset to obtain a pin image dataset;
Constructing a pulse neural network to identify pin defects: constructing impulse neurons, constructing impulse neural networks, clustering and optimizing impulse neural networks, optimizing model parameters, and deploying impulse neural network models to identify pin states of single chips;
Constructing impulse neurons includes: at the initial time, performing numerical integration on the membrane potential by using an Euler method; the construction of the impulse neural network is divided into an input layer, a hidden layer and an output layer;
The method for clustering and optimizing the impulse neural network comprises the following steps: carrying out poisson coding on pin images of a single chip according to poisson distribution, converting the pin images of the chip into pulse signals, and labeling each pulse signal with a label of a clustering cluster through clustering based on the pulse signals;
the optimization model parameters include: optimizing the super parameters of all impulse neural networks according to a sparrow search algorithm;
deploying a pulsed neural network model to identify pin states, comprising: and after training all the impulse neural networks, saving parameters of the model, deploying the parameters on a platform, and outputting the result as a pin state in a pin image of a single chip.
2. The method for detecting pin defects of an intelligent SOT package chip according to claim 1, further comprising:
Optimizing the number of hidden layer neurons and neuron threshold values of the impulse neural network through a sparrow search algorithm so as to identify pin defects of the chip;
the optimizing the hidden layer neuron number and neuron threshold of the impulse neural network by the sparrow search algorithm comprises the following steps:
initializing a discoverer and a joiner: selecting super parameters of a pulse neural network, wherein the super parameters comprise the number of neurons in a hidden layer and a neuron threshold value, and initializing the positions of sparrows and the duty ratio of predators and jointers;
Calculating the fitness: carrying out normalized coding according to the super parameters of the impulse neural network, and mapping the coded data to the super parameters of the impulse neural network; the objective function selects the maximum value of the accuracy of the impulse neural network model, which represents the maximum function of the accuracy, and the model accuracy corresponding to the super parameter of the encoded impulse neural network represents the fitness of sparrow;
Updating the discoverer and enrollee locations: updating the positions of the discoverer and the joiner, moving towards a place with high accuracy of the impulse neural network model, and further updating the position of the predator;
updating the sparrow position: according to the fitness, the positions of all sparrows are timely adjusted, and the iterative parameters of the algorithm are adjusted;
And (3) loop iteration: and repeatedly and iteratively finding out the number of hidden layer neurons and neuron threshold values of the optimal impulse neural network model to obtain an optimal optimization result.
3. the method for detecting the pin defect of the intelligent SOT package chip according to claim 1, wherein the step of photographing the pins of the chip in a high-speed motion state from the side by the event camera to obtain the pin image of the chip comprises the following steps:
The event camera is positioned on the side surface of the chip in a high-speed motion state to shoot the pins of the chip, so that pin images of the chip are obtained; the pin image of the chip is a gray level image generated by accumulating pulse data of the chip pins for a period of time, and the event camera moves at a high speed relative to the SOT packaged chip in the shooting process.
4. The method for detecting pin defects of an intelligent SOT package chip according to claim 1, wherein the determining whether the pin image of the chip is clear comprises:
If the pin image of the chip is clear, judging whether the pin is complete, and if the pin image of the chip is not clear, marking the pin image of the chip as an invalid sample; judging whether the pin image of the chip is clear or not according to the standard that the pin feature and the background feature are obviously distinguished and no overlap exists between the pin features;
After marked as an invalid sample, the pin image of the chip does not participate in training of the model, and a new pin image of the chip needs to be shot again;
Judging whether the pin image of the chip is complete or not comprises the following steps:
If all pins in the pin image of the chip are complete, labeling the pin state of the pin image of the chip, and if the pin image of the chip has incomplete pins, labeling the pin image of the chip as an invalid sample; the standard of the complete pin is that the characteristics of a single pin are complete and the missing of the characteristics of the pin does not exist; after marked as an invalid sample, the pin image of the chip does not participate in training of the model, and a new pin image of the chip needs to be shot again.
5. The method for detecting pin defects of an intelligent SOT package chip according to claim 1, wherein the labeling the pin image of the chip to generate the initial data set of the pin image of the chip includes:
Firstly, dividing pin images of a chip: finding out the initial position of the edge of a pin in the pin image of the chip, and dividing the image according to the relative position proportion relation of the pins of the SOT packaging chip to form the pin image of a single chip of the pins of the SOT packaging chip; a large amount of noise and obvious SOT packaging chip pin outline characteristics exist in the pin image of the single chip;
Marking according to the pin states of the pin images of the single chip, wherein the pin states are respectively marked as a normal state, a twisted state, a longitudinal bending state and a transverse bending state; the twisting state is that the SOT package chip pins rotate along the axis; the longitudinal bending state is that the pins of the SOT packaging chip are bent inwards and outwards, and the bending direction is perpendicular to the pin image of the chip; the transverse bending state is that the pins of the SOT package chip are bent towards two sides.
6. The method for detecting pin defects of an intelligent SOT package chip according to claim 1, wherein expanding the initial pin image dataset to obtain a pin image dataset includes:
The pin images of the chips are turned over, rotated, sheared and randomly added with noise, but the pin characteristics of the chips are not destroyed, and the pin images of the single chips are randomly combined and expanded;
Forming a pin image dataset of the chip based on the pin image initial dataset of the expanded chip by adjusting the classification category; the classification category is the pin state corresponding to the pin image of the single chip; the adjustment targets are that the duty ratio of the torsion state, the longitudinal bending state and the transverse bending state is the same; the method for adjusting is to expand the pin images of the single chip classified into a twisted state, a vertical bending state and a horizontal bending state, and the method for expanding is to randomly shield, twist and locally change gray values of the pin images of the single chip.
7. the method for detecting pin defects of a smart SOT packaged chip according to claim 1, wherein said constructing impulse neurons comprises:
At the initial time, performing numerical integration on the membrane potential by using an Euler method; firstly, determining the time interval of the Euler integral as a period of time before pulse generation, wherein the initial membrane potential is zero, and then carrying out gradual integral calculation along with the change of time to describe the dynamic change of the integral;
Comparing the integral value with the membrane potential in a time interval, and generating a pulse if the current membrane potential is greater than a neuron threshold value; after the pulse is generated, the decay factor is increased over a time interval to indicate that the rate of increase of the neuron membrane potential is slowed.
8. The method for detecting pin defects of an intelligent SOT package chip according to claim 1, wherein the method for constructing an input layer is as follows:
The neuron number of the input layer is the same as the product of the pixel height and the width of the pin image of the single chip, and the neuron value is the normalized gray value of the pin image of the single chip;
The method for constructing the hidden layer comprises the following steps:
the initial value of the neuron number of the first hidden layer adopts the average value of the neuron numbers of the input layer and the output layer, and the initial value of the neuron number of other hidden layers is consistent with the initial value of the neuron number of the first hidden layer; the input layer and the hidden layer are connected through synapses, and the synapses represent the connection weights among neurons;
The method for constructing the output layer comprises the following steps:
The output layer has 4 neurons, which respectively represent a normal state, a twisted state, a longitudinally bent state and a transversely bent state; the output layer and the hidden layer are directly connected through synapses; wherein the weight of the synaptic connection is used to adjust the pulse transmission intensity between two neurons.
9. The method for detecting the pin defects of the intelligent SOT package chip according to claim 1, wherein the method for clustering and optimizing the impulse neural network is as follows:
Carrying out poisson coding on pin images of a single chip according to poisson distribution, and converting the pin images of the chip into pulse signals; extracting intervals of pulse signals as characteristic vectors of clusters, and converting each pulse signal into characteristic vectors with different characteristics;
Respectively calculating Euclidean distances of the two feature vectors; adopting hierarchical clustering to gather feature vectors with similar features into clusters;
Labeling each pulse signal with a label of a cluster, dividing a pin image dataset of a chip into pin image sub-datasets of a plurality of chips according to the label, and respectively adjusting the number of hidden neurons and neuron thresholds in a pulse neural network model corresponding to the pin image sub-datasets of the chips.
10. The method for detecting pin defects of a smart SOT packaged chip according to claim 1, wherein the super parameters include hidden layer neuron number and neuron threshold;
the deploying the impulse neural network model to identify pin states includes:
After training all the impulse neural networks, saving parameters of a model, deploying the parameters on a computing platform, and outputting a result to be a pin state in a pin image of a single chip generated by voting of a plurality of impulse neural networks; the voting method adopts weights to carry out voting weighting; if the finally identified pin state is a twisted state, a longitudinal bending state or a transverse bending state, the pin state and corresponding chip number information in the pin image of the single chip are recorded and an alarm is given.
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