CN117764019A - Noise simulation circuit of back power supply distribution network of integrated circuit - Google Patents
Noise simulation circuit of back power supply distribution network of integrated circuit Download PDFInfo
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Abstract
The invention discloses a noise simulation circuit of a back power supply distribution network of an integrated circuit, which relates to the technical field of integrated circuits, and comprises the following steps: a power supply voltage source, a back power supply distribution network equivalent circuit model and an on-chip load equivalent current source; the back power distribution network equivalent circuit model specifically comprises: the circuit comprises a welding point equivalent circuit, a back metal grid equivalent circuit, a micro silicon through hole equivalent circuit and a buried power rail equivalent circuit; the power supply voltage source is connected with the welding point equivalent circuit; the welding point equivalent circuit is connected with the back metal grid equivalent circuit; the back metal grid equivalent circuit is connected with the micro silicon through hole equivalent circuit; the micro through silicon via equivalent circuit is connected with the buried power rail equivalent circuit; the buried power rail equivalent circuit is connected with an on-chip load equivalent current source. The invention realizes higher accuracy and can simulate the real situation more.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a noise simulation circuit for a back side power distribution network of an integrated circuit.
Background
In integrated circuit systems, most transistors are fabricated on monocrystalline silicon wafers, which are connected by metal lines for the transmission of signals and power. However, as the number of transistors of integrated circuits increases and the size of the integrated circuits decreases, the size of the interconnect lines also decreases and the interconnect wiring becomes more and more congested. The reduction in interconnect line size results in an increase in parasitic parameters of the interconnect lines, thereby increasing delay and introducing noise. Congestion of the interconnect lines can lead to increased crosstalk, severely affecting circuit performance. The supply lines inevitably compete for space with the signal lines, and while there are many solutions that can improve efficiency and reduce the footprint of the active part of the supply network (Power Delivery Network, PDN), the on-chip power distribution network design must be reconsidered to address the current power supply challenges of integrated circuits.
Currently, a new back side PDN (BS-PDN) scheme is proposed. In this approach, the back side of the wafer is metallized and used for power, and the front side is still used to implement logic functions and signal interconnections. The Bonding pads (Bonding) transfer power from outside the die to a Backside Metal (BSM) on the back side of the wafer, and the buried power rails (Buried Power Rail, BPR) and Micro Through-Silicon Via (μtsv) can also effectively transfer power from the back side of the wafer to the front-end active devices. The novel method for back side power supply can reduce congestion of interconnection line wiring, thereby reducing noise on the interconnection lines and crosstalk between the interconnection lines and improving chip performance. By the method for establishing the noise simulation circuit for the back power supply distribution network, noise can be analyzed and optimized.
The equivalent resistance of the supply grid is taken into account in the published papers "Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and. Mu. TSVs" (doi: 10.1109/TED.2019.2954301) Md Obaidul Hossen and Geert Van der Plas et al, and a noise simulation circuit of a back side power supply distribution network of an integrated circuit is built.
The model in the prior art is rough, the actual back power distribution network structure is not considered, parasitic parameters of the power supply line are not fully considered, and the actual working condition of the on-chip load is not considered.
Disclosure of Invention
The invention solves the problems that the actual back power supply distribution network structure is not considered, parasitic parameters of a power supply line are not fully considered, and the working condition of an actual on-chip load is not considered in the prior art, thereby realizing higher accuracy and simulating the real condition.
The invention provides a noise simulation circuit of a back side power supply distribution network of an integrated circuit, which comprises: the power supply voltage source, the back power supply distribution network equivalent circuit model and the on-chip load equivalent current source, wherein the back power supply distribution network equivalent circuit model specifically comprises: the circuit comprises a welding point equivalent circuit, a back metal grid equivalent circuit, a micro silicon through hole equivalent circuit and a buried power rail equivalent circuit;
The power supply voltage source is connected with the welding point equivalent circuit;
the welding point equivalent circuit is connected with the back metal grid equivalent circuit;
the back metal grid equivalent circuit is connected with the micro through silicon via equivalent circuit, wherein the back metal grid equivalent circuit comprises a plurality of same unit back metal grid equivalent circuits;
the micro through silicon via equivalent circuit is connected with the buried power rail equivalent circuit;
the buried power rail equivalent circuit is connected with the on-chip load equivalent current source, wherein the buried power rail equivalent circuit is formed by connecting a plurality of same unit buried power rail equivalent circuits in series.
In one possible implementation manner, the welding point equivalent circuit specifically includes: first parasitic resistance R of welding point Bond Second parasitic resistance R of welding point Bond First parasitic inductance L of welding point/2 Bond Second parasitic inductance L of welding point Bond Parasitic capacitance C around/2 and solder joint Bond ；
First parasitic resistance R of the welding point Bond First parasitic inductance L of the welding point Bond Second parasitic inductance L of the welding point Bond 2 and a second parasitic resistance R of said solder joint Bond 2, sequentially connecting in series;
Parasitic capacitance C around the solder joint Bond A first parasitic resistor R connected in parallel with the welding point Bond /2 and saidSecond parasitic resistance R of the welding point Bond Between/2.
In one possible implementation manner, the unit back metal grid equivalent circuit specifically includes: a first and second lateral circuit, a longitudinal circuit and a series circuit;
the first and second lateral circuits each include: first parasitic inductance L of unit BSM2 layer grid line BSM2 First parasitic resistance R of/2, cell BSM2 layer grid line BSM2 Second parasitic resistance R of/2, cell BSM2 layer grid lines BSM2 Second parasitic inductance L of/2, unit BSM2 layer grid line BSM2 2 and MIM capacitor C MIM ；
First parasitic inductance L of the cell BSM2 layer grid line BSM2 First parasitic resistance R of the cell BSM2 layer grid line BSM2 Second parasitic resistance R of the cell BSM2 layer grid line BSM2 Second parasitic inductance L of/2 and the cell BSM2 layer grid line BSM2 2, sequentially connecting in series; the MIM capacitor C MIM First parasitic resistor R connected in parallel with grid line of BSM2 layer of the unit BSM2 Second parasitic resistance R of/2 and the cell BSM2 layer grid line BSM2 Between/2;
the longitudinal circuit comprises: n units of BSM1 layer grid line equivalent circuits connected in series in sequence, wherein n is expressed as the interval p of adjacent BSM2 layer grid lines BSM2 Distance p from adjacent buried power rail BPR Is a ratio of (2);
the equivalent circuit of the cell BSM1 layer grid line comprises parasitic inductance L of the cell BSM1 layer grid line connected in series BSM1 Parasitic resistance R of cell BSM1 layer grid line BSM1 ；
The series circuit comprises parasitic resistance R of through holes connected in series in sequence Via Parasitic inductance L of the sum via Via ；
The first lateral circuit and the longitudinal circuit are connected by the series circuit.
In one possible implementation, the parasitic resistance R of the cell BSM1 layer grid line BSM1 The specific calculation formula of (2) is expressed as follows:
parasitic resistance R of the cell BSM2 layer grid line BSM2 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the cell BSM1 layer grid line BSM1 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the cell BSM2 layer grid line BSM2 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the via hole Via The specific calculation formula of (2) is expressed as follows:
parasitic resistance R of the via hole Via The specific calculation formula of (2) is expressed as follows:
wherein ρ is Cu Represents the resistivity of copper; l (L) BSM1 Representing the length of the unit BSM1 layer grid line; h is a BSM1 Representing the height of the BSM1 layer grid lines; w (w) BSM1 Representing the width of the BSM1 layer grid line; l (L) BSM2 Representing the length of the unit BSM2 layer grid lines; h is a BSM2 Representing the height of the BSM2 layer grid lines; w (w) BSM2 Representing the width of the BSM2 layer grid lines; mu (mu) 0 Magnetic permeability representing vacuum; gamma represents an empirical constant; h is a Via Representing the height of the through hole; w (w) Via Representing the side length of the through hole.
In one possible implementation manner, the equivalent circuit of the micro through silicon via specifically includes:
first parasitic resistance R of micro silicon through hole μTSV Second parasitic resistance R of micro silicon through hole μTSV First parasitic inductance L of micro silicon through hole μTSV Second parasitic inductance L of micro silicon through hole μTSV Parasitic capacitance C of/2, oxide layer μTSV_ox Parasitic capacitance C of silicon substrate μTSV_Si And parasitic conductance G of silicon substrate μTSV_Si ；
First parasitic inductance L of the micro silicon through hole μTSV First parasitic resistance R of micro silicon through hole μTSV Second parasitic inductance L of micro silicon through hole μTSV Second parasitic inductance L of/2 and said micro through silicon via μTSV 2, sequentially connecting in series;
parasitic capacitance C of the oxide layer μTSV_ox A first parasitic resistor R connected in parallel with the micro silicon through hole μTSV 2 and a second parasitic resistance R of the micro through silicon via μTSV Between/2;
parasitic conductance G of the silicon substrate μTSV_Si And parasitic capacitance C of the silicon substrate μTSV_Si Parasitic capacitance C connected in series with two oxide layers μTSV_ox Between them.
With reference to the first aspect, in one possible implementation manner, the first parasitic resistance R of the micro through silicon via μTSV Second parasitic resistance R of/2 and micro through silicon via μTSV Adding/2 to obtain parasitic resistance R of micro silicon through hole μTSV ；
First parasitic inductance L of the micro silicon through hole μTSV Second parasitic inductance L of/2 and said micro through silicon via μTSV Adding/2 to obtain parasitic inductance L of micro silicon through hole μTSV 。
In one possible implementation of the present invention,parasitic resistance R of the micro silicon through hole μTSV The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the micro silicon through hole μTSV The specific calculation formula of (2) is expressed as follows:
parasitic capacitance C of the oxide layer μTSV_ox The specific calculation formula of (2) is expressed as follows:
parasitic capacitance C of the silicon substrate μTSV_Si The specific calculation formula of (2) is expressed as follows:
parasitic conductance G of the silicon substrate μTSV_Si The specific calculation formula of (2) is expressed as follows:
wherein ρ is Cu Represents the resistivity of copper; h is a μTSV Representing the height of the micro through silicon vias; r is (r) μTSV Representing the radius of the micro through silicon via; mu (mu) 0 Magnetic permeability representing vacuum; epsilon ox Represents the relative dielectric constant of the oxide layer; epsilon 0 Dielectric constant representing vacuum; t is t μTSV_ox Indicating the thickness of the oxide layer; epsilon Si Represents the relative dielectric constant of silicon; s is(s) μTSV Representing the distance between the microsilicon via and the surrounding microsilicon via.
In one possibilityIn an implementation manner, the equivalent circuit of the unit buried power rail specifically comprises: first parasitic resistance R of unit buried power rail BPR Second parasitic resistance R of unit buried power supply rail BPR First parasitic inductance L of unit buried power rail BPR Second parasitic inductance L of unit buried power supply rail BPR First parasitic capacitance C of oxide layer BPR_ox Second parasitic capacitance C of oxide layer BPR_ox Parasitic capacitance C of silicon substrate BPR_Si And parasitic conductance G of silicon substrate BPR_Si ；
First parasitic inductance L of the unit buried power rail BPR First parasitic resistance R of said unit buried power rail BPR 2, a second parasitic resistance of the unit buried power supply rail and a second parasitic inductance L of the unit buried power supply rail BPR 2, sequentially connecting in series;
first parasitic capacitance C of the oxide layer BPR_ox First parasitic resistance R of the unit buried power rail connected in parallel BPR 2, the second parasitic resistance of the unit buried power rail is between;
parasitic conductance G of the silicon substrate BPR_Si And parasitic capacitance C of the silicon substrate BPR_Si A first parasitic capacitance C connected in series with the oxide layer BPR_ox And a second parasitic capacitance C of the oxide layer BPR_ox Between them.
In one possible implementation, the first parasitic resistance R of the unit buried power rail BPR Second parasitic resistance R of/2 and cell buried power supply rail BPR Adding/2 to obtain parasitic resistance R of unit buried power rail BPR ；
First parasitic inductance L of the unit buried power rail BPR 2 and a second parasitic inductance L of the unit buried power supply rail BPR Parasitic inductance L of unit buried power rail obtained by adding/2 BPR 。
In one possible implementation, the parasitic resistance R of the unit buried power rail BPR The specific calculation formula of (2) is as follows:
parasitic inductance L of the unit buried power rail BPR The specific calculation formula of (2) is as follows:
parasitic capacitance C of the oxide layer BPR_ox The specific calculation formula of (2) is as follows:
parasitic capacitance C of the silicon substrate BPR_Si The specific calculation formula of (2) is as follows:
parasitic conductance G of the silicon substrate BPR_Si The specific calculation formula of (2) is as follows:
wherein ρ is W Representing the resistivity of tungsten in a high temperature process; l (L) BPR Representing the length of the unit buried power rail; h is a BPR Representing the height of the buried power rail; w (w) BPR Representing the width of the buried power rail; mu (mu) 0 Magnetic permeability representing vacuum; gamma represents an empirical constant; epsilon ox Represents the relative dielectric constant of the oxide layer; epsilon 0 Dielectric constant representing vacuum; t is t BPR_ox Indicating the thickness of the oxide layer; epsilon Si Represents the relative dielectric constant of silicon; t is t BPR_Si Representing the thickness of the silicon medium between buried power rails; sigma (sigma) Si Indicating the conductivity of silicon.
One or more technical schemes provided by the invention have at least the following technical effects or advantages:
(1) The invention considers the structure of the actual back power supply distribution network, performs segmentation modeling on the back power supply distribution network, and considers the influence of various parasitic parameters, thereby having higher accuracy compared with the prior art.
(2) The actual working condition of the on-chip load is considered, and the on-chip load is closer to the actual condition than the prior art.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments of the present invention or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a noise simulation circuit of a back side power distribution network of an integrated circuit according to an embodiment of the present invention;
FIG. 2a is a block diagram of a back side power distribution network according to an embodiment of the present invention;
FIG. 2b is a schematic diagram of a back side power distribution network according to an embodiment of the present invention;
FIG. 3a is a diagram illustrating a solder joint configuration according to an embodiment of the present invention;
FIG. 3b is a diagram illustrating an arrangement of solder joints according to an embodiment of the present invention;
Fig. 3c is a diagram of a solder joint equivalent circuit according to an embodiment of the present invention;
FIG. 4a is a schematic diagram of a back metal grid according to an embodiment of the present invention;
FIG. 4b is a schematic diagram of an arrangement of a back side metal grid according to an embodiment of the present invention;
fig. 4c is an equivalent circuit diagram of a metal grid on the back of a unit according to an embodiment of the present invention;
FIG. 5a is a block diagram of a micro through silicon via provided by an embodiment of the present invention;
fig. 5b is a layout diagram of micro through silicon vias according to an embodiment of the present invention;
fig. 5c is an equivalent circuit diagram of a micro through silicon via according to an embodiment of the present invention;
FIG. 6a is a block diagram of a buried power rail provided by an embodiment of the present invention;
FIG. 6b is a schematic diagram of an embodiment of a buried power rail;
FIG. 6c is an equivalent circuit diagram of a unit buried power rail provided by an embodiment of the present invention;
fig. 7 is a schematic diagram of an equivalent current source of an on-chip load according to an embodiment of the present invention;
fig. 8 is a noise simulation circuit diagram of a back side power distribution network according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a noise simulation circuit of a back side power supply distribution network of an integrated circuit, as shown in fig. 1, the noise simulation circuit comprises: the power supply voltage source, the back power supply distribution network equivalent circuit model and the on-chip load equivalent current source, wherein the back power supply distribution network equivalent circuit model specifically comprises: the circuit comprises a welding point equivalent circuit, a back metal grid equivalent circuit, a micro silicon through hole equivalent circuit and a buried power rail equivalent circuit; the power supply voltage source is connected with the welding point equivalent circuit; the welding point equivalent circuit is connected with the back metal grid equivalent circuit; the back metal grid equivalent circuit is connected with the micro silicon through hole equivalent circuit; the micro through silicon via equivalent circuit is connected with the buried power rail equivalent circuit; the buried power rail equivalent circuit is connected with an on-chip load equivalent current source.
Illustratively, the noise simulation circuit of the back side power distribution network of the present invention belongs to an on-chip power distribution network, and therefore omits package-level and board-level power distribution networks. The noise simulation circuit is mainly divided into three parts: a supply voltage source, a back side power distribution network equivalent circuit and an on-chip load equivalent current source. The back side power distribution network mainly considers parasitic parameters of the power line, and the ground line is treated as ideal.
A supply voltage source: and setting a proper voltage source according to the actual circuit working voltage.
Back side power distribution network equivalent circuit: according to the structure of the back power distribution network, the back power distribution network equivalent circuit can be divided into equivalent circuit models of welding points (Bonding), back Metal grids (Backside Metal), micro Through-Silicon Via (μtsv), and buried power supply rails (Buried Power Rail, BPR). And respectively obtaining four partial parasitic parameters, establishing an equivalent circuit model, and connecting the equivalent circuit models together to form a back power supply distribution network equivalent circuit.
On-chip load equivalent current source: the on-chip load can be equivalent to a current source of triangular wave to simulate the switching behavior of the on-chip load of the integrated circuit. The minimum current and the maximum current are set according to the power consumption condition of the actual operation.
And finally, connecting an on-chip load equivalent current source to the buried power rail equivalent circuit of each section of unit, and connecting a voltage source to the welding point equivalent circuit to obtain a complete noise simulation circuit of the back power distribution network.
Illustratively, as shown in fig. 2a and 2b, the structure of the back side power distribution network is divided into four components, namely, solder joints, back side metal grids, micro through silicon vias, and buried power rails. Therefore, the back side power distribution network equivalent circuit is also divided into equivalent circuit models of these four parts.
Specifically, as shown in fig. 3c, the equivalent circuit of the welding point specifically includes: first parasitic resistance R of welding point Bond Second parasitic resistance R of welding point Bond First parasitic inductance L of welding point/2 Bond Second parasitic inductance L of welding point Bond Parasitic capacitance C around/2 and solder joint Bond 。
First parasitic resistance R of welding point Bond 2, weldingFirst parasitic inductance L of contact Bond Second parasitic inductance L of welding point Bond Second parasitic resistance R of/2 and welding point Bond 2, sequentially connecting in series;
parasitic capacitance C around the solder joint Bond First parasitic resistor R connected in parallel with welding point Bond Second parasitic resistance R of/2 and welding point Bond Between/2.
Illustratively, as shown in fig. 3a and 3b, the weld comprises: solder bumps (Solder bumps) and pads (pads). The parasitic parameters of the materials, the sizes and the distances are known, and the parasitic parameters are obtained through the electromagnetic parameter extraction function of electromagnetic simulation software. Specifically, the solder bump is generally composed of various alloys, and is an oval ball wrapped by a polymer insulating material, and is usually manufactured on a pad base made of copper. h is a Bump Indicating the height of the solder bump, h Pad Representing the height of the bonding pad, r Bump Represents the radius of the solder bump, r Pad Represents the radius of the bonding pad, p Bond Indicating the pitch of the solder joints.
The equivalent circuit of the welding point considers the parasitic resistance R of the welding point Bond Parasitic inductance L of welding point Bond And parasitic capacitance C around the solder joint Bond . The interaction of the solder joint with the surrounding four solder joints is mainly considered when extracting the parasitic capacitance related to the solder joint. Parasitic parameters were extracted using Q3D tools.
Specifically, the back metal grid equivalent circuit is composed of repeated unit grid equivalent circuits. As shown in fig. 4c, the equivalent circuit of the metal grid on the back of the unit specifically includes: the first and second lateral circuits, the longitudinal circuit and the series circuit.
The first and second lateral circuits respectively include: first parasitic inductance L of unit BSM2 layer grid line BSM2 First parasitic resistance R of/2, cell BSM2 layer grid line BSM2 Second parasitic resistance R of/2, cell BSM2 layer grid lines BSM2 Second parasitic inductance L of/2, unit BSM2 layer grid line BSM2 2 and MIM capacitor C MIM ；
First parasitic inductance of unit BSM2 layer grid lineL BSM2 First parasitic resistance R of/2, cell BSM2 layer grid line BSM2 Second parasitic resistance R of/2, cell BSM2 layer grid lines BSM2 Second parasitic inductance L of/2 and cell BSM2 layer grid lines BSM2 2, sequentially connecting in series; MIM capacitor C MIM First parasitic resistor R connected in parallel with grid line of BSM2 layer of unit BSM2 Second parasitic resistance R of/2 and cell BSM2 layer grid lines BSM2 Between/2;
the vertical circuit includes: n units of BSM1 layer grid line equivalent circuits connected in series in sequence, wherein n is expressed as the interval p of adjacent BSM2 layer grid lines BSM2 Distance p from adjacent buried power rail BPR Is a ratio of (2);
the equivalent circuit of the cell BSM1 layer grid line comprises parasitic inductance L of the cell BSM1 layer grid line connected in series BSM1 Parasitic resistance R of cell BSM1 layer grid line BSM1 ；
Series circuit, in particular parasitic resistance R comprising vias connected in series in sequence Via Parasitic inductance L of the sum via Via ；
The first transverse circuit and the first longitudinal circuit are connected by a series circuit.
As illustrated in fig. 4a and 4b, the back metal grid is exemplarily composed of repeated unit back metal grids, each of which is divided into a unit BSM1 layer grid line, a unit BSM2 layer grid line and a Via (Via), and the materials, sizes and pitches are known, and the parasitic parameters thereof are obtained through a parasitic parameter calculation formula or an electromagnetic parameter extraction function of electromagnetic simulation software. Specifically, the unit BSM1 layer grid lines, the unit BSM2 layer grid lines and the through holes in the unit back metal grid are generally made of copper and are wrapped in an insulating filling material. In modeling, the space p between adjacent buried power supply rails is used to take into account that the BSM1 grid lines are physically connected with the buried power supply rails through micro-silicon through holes and are mutually perpendicular to the buried power supply rails BPR Length l of the grid line of the BSM1 layer of the display unit BSM1 I.e. l BSM1 ＝2p BPR The method comprises the steps of carrying out a first treatment on the surface of the Considering that the BSM2 layer grid lines are physically connected with the BSM1 layer grid lines through the through holes and are perpendicular to each other, the spacing p of the adjacent BSM1 layer grid lines is used BSM1 Representation sheetLength of the primary BSM2 layer grid line BSM2 I.e. l BSM2 ＝2p BSM1 . The lateral side of each unit grid is a section of unit BSM2 layer grid lines, the longitudinal side is connected by n sections of unit BSM1 layer grid lines, n is dependent on the interval p of adjacent BSM2 layer grid lines BSM2 And the spacing p between adjacent buried power rails BPR I.e.
Equivalent circuit of cell back metal grid considers parasitic resistance R of cell BSM1 layer grid line BSM1 Parasitic inductance L of cell BSM1 layer grid line BSM1 Parasitic resistance R of cell BSM2 layer grid line BSM2 Parasitic inductance L of cell BSM2 layer grid line BSM2 Parasitic resistance R of via hole Via Parasitic inductance L of via hole Via MIM capacitor C between power line and ground line of back metal grid MIM . Parasitic parameters are extracted using Q3D tools or determined by the following formulas.
Specifically, the parasitic resistance R of the cell BSM1 layer grid line BSM1 The specific calculation formula of (2) is expressed as follows:
parasitic resistance R of cell BSM2 layer grid line BSM2 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of cell BSM1 layer grid line BSM1 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of cell BSM2 layer grid line BSM2 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of via hole Via The specific calculation formula of (2) is expressed as follows:
parasitic resistance R of via Via The specific calculation formula of (2) is expressed as follows:
wherein ρ is Cu Represents the resistivity of copper; l (L) BSM1 Representing the length of the unit BSM1 layer grid line; h is a BSM1 Representing the height of the BSM1 layer grid lines; w (w) BSM1 Representing the width of the BSM1 layer grid line; l (L) BSM2 Representing the length of the unit BSM2 layer grid lines; h is a BSM2 Representing the height of the BSM2 layer grid lines; w (w) BSM2 Representing the width of the BSM2 layer grid lines; mu (mu) 0 Magnetic permeability representing vacuum; gamma represents an empirical constant; h is a Via Representing the height of the through hole; w (w) Via Representing the side length of the through hole.
Specifically, as shown in fig. 5c, an equivalent circuit of the micro through silicon via specifically includes: first parasitic resistance R of micro silicon through hole μTSV Second parasitic resistance R of micro silicon through hole μTSV First parasitic inductance L of micro silicon through hole μTSV Second parasitic inductance L of micro silicon through hole μTSV Parasitic capacitance C of/2, oxide layer μTSV_ox Parasitic capacitance C of silicon substrate μTSV_Si And parasitic conductance G of silicon substrate μTSV_Si ；
First parasitic inductance L of micro silicon through hole μTSV First parasitic resistance R of micro silicon through hole μTSV Second parasitic inductance L of micro silicon through hole μTSV Second parasitic inductance L of/2 and micro silicon through hole μTSV Serial/2A link;
parasitic capacitance C of oxide layer μTSV_ox First parasitic resistor R connected in parallel with micro silicon through hole μTSV Second parasitic resistance R of/2 and micro through silicon via μTSV Between/2;
parasitic conductance G of silicon substrate μTSV_Si And parasitic capacitance C of silicon substrate μTSV_Si Parasitic capacitance C of the parallel circuit connected in series with two oxide layers μTSV_ox Between them.
Specifically, a first parasitic resistance R of the micro through silicon via μTSV Second parasitic resistance R of/2 and micro through silicon via μTSV Adding/2 to obtain parasitic resistance R of micro silicon through hole μTSV ；
First parasitic inductance L of micro silicon through hole μTSV Second parasitic inductance L of/2 and micro silicon through hole μTSV Adding/2 to obtain parasitic inductance L of micro silicon through hole μTSV 。
Illustratively, as shown in fig. 5a and 5b, the materials, sizes and pitches of the through-silicon-via are known, and the parasitic parameters thereof are obtained by a parasitic parameter calculation formula or an electromagnetic parameter extraction function of electromagnetic simulation software. Specifically, the micro through silicon via is manufactured in a silicon substrate on the back of a thinned wafer, and is a solid cylindrical copper column wrapped by a thin insulating layer of silicon dioxide for current transmission. They can transfer current from the back side of the wafer to the active devices at the front end in the most efficient manner. h is a μTSV Representing the height of the micro through silicon vias; r is (r) μTSV Representing the radius of the micro through silicon via; t is t μTSV_ox Indicating the thickness of the oxide layer. P is p μTSV Representing the pitch of adjacent microsilicon vias in microsilicon vias connected to the same backside metal gridlines. s is(s) μTSV Representing the distance between a microsilicon via and a surrounding microsilicon via, the pitch p of adjacent microsilicon vias can be used, taking into account both nearest and next-nearest neighbors μTSV Spacing p of adjacent buried power rails BPR And the pitch p of adjacent BSM1 layer grid lines BSM1 The calculation results are respectively as follows:or->
The equivalent circuit of the micro through silicon via considers the parasitic resistance R of the micro through silicon via μTSV Parasitic inductance L of micro silicon through hole μTSV Parasitic capacitance C of oxide layer μTSV_ox Parasitic capacitance C of silicon substrate μTSV_Si And parasitic conductance G of silicon substrate μTSV_Si . When the parasitic capacitance and parasitic conductance related to the micro through silicon vias are extracted, the interaction between the micro through silicon vias and four surrounding micro through silicon vias is mainly considered. Parasitic parameters are extracted using Q3D tools or determined by the following formulas.
Specifically, parasitic resistance R of micro through silicon via μTSV The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of micro silicon through hole μTSV The specific calculation formula of (2) is expressed as follows:
parasitic capacitance C of oxide layer μTSV_ox The specific calculation formula of (2) is expressed as follows:
parasitic capacitance C of silicon substrate μTSV_Si The specific calculation formula of (2) is expressed as follows:
parasitic conductance G of silicon substrate μTSV_Si The specific calculation formula of (2) is expressed as follows:
Wherein ρ is Cu Represents the resistivity of copper; h is a μTSV Representing the height of the micro through silicon vias; r is (r) μTSV Representing the radius of the micro through silicon via; mu (mu) 0 Magnetic permeability representing vacuum; epsilon ox Represents the relative dielectric constant of the oxide layer; epsilon 0 Dielectric constant representing vacuum; t is t μTSV_ox Indicating the thickness of the oxide layer; epsilon Si Represents the relative dielectric constant of silicon; s is(s) μTSV Representing the distance between the microsilicon via and the surrounding microsilicon via.
Specifically, the buried power rail equivalent circuit is formed by connecting unit buried power rail equivalent circuits in series. As shown in fig. 6c, the equivalent circuit of the unit buried power rail specifically includes: first parasitic resistance R of unit buried power rail BPR Second parasitic resistance R of unit buried power supply rail BPR First parasitic inductance L of unit buried power rail BPR Second parasitic inductance L of unit buried power supply rail BPR First parasitic capacitance C of oxide layer BPR_ox Second parasitic capacitance C of oxide layer BPR_ox Parasitic capacitance C of silicon substrate BPR_Si And parasitic conductance G of silicon substrate BPR_Si ；
First parasitic inductance L of unit buried power rail BPR First parasitic resistance R of unit buried power rail BPR 2, second parasitic resistance of the unit buried power supply rail and second parasitic inductance L of the unit buried power supply rail BPR 2, sequentially connecting in series;
first parasitic capacitance C of oxide layer BPR_ox First parasitic resistance R of parallel and unit buried power rail BPR 2, the second parasitic resistance of the unit buried power rail;
parasitic conductance G of silicon substrate BPR_Si And parasitic capacitance C of silicon substrate BPR_Si A first parasitic capacitor C connected in series with the oxide layer BPR_ox And a second parasitic capacitance C of the oxide layer BPR_ox Between them.
Specifically, the first parasitic resistance R of the unit buried power supply rail BPR Second parasitic resistance R of/2 and cell buried power supply rail BPR Adding/2 to obtain parasitic resistance R of unit buried power rail BPR ；
First parasitic inductance L of unit buried power rail BPR Second parasitic inductance L of/2 and unit buried power supply rail BPR Adding/2 to obtain parasitic inductance L of unit buried power rail BPR 。
Illustratively, as shown in fig. 6a and 6b, the buried power supply rail is formed by connecting repeated unit buried power supply rails, and the parasitic parameters of the buried power supply rails are obtained through a parasitic parameter calculation formula or an electromagnetic parameter extraction function of electromagnetic simulation software by knowing materials, sizes and intervals. Specifically, the buried power rail is a metal line buried under the transistor, typically tungsten, partially encased in a silicon substrate by a thin insulating layer of silicon dioxide, and partially in a shallow trench isolation oxide. t is t BPR_Si Representing the thickness of the silicon medium between adjacent buried power rails, can be calculated, i.e., t BPR_Si ＝p BPR -2t BPR_ox -w BPR ；w BPR Representing the width of the buried power rail; h is a BPR Representing the height of the buried power rail; t is t BPR_ox Indicating the thickness of the oxide layer. According to the connection relation between the buried power rail and the micro silicon through holes, the buried power rail can be disassembled into a section of unit buried power rail, and the length l of each section of unit buried power rail BPR Can use the distance p between adjacent buried power rails BPR Spacing p of adjacent BSM1 layer grid lines BSM1 And pitch p of adjacent microsilicon vias μTSV Expressed, i.e
Equivalent circuit of unit buried power supply rail considers parasitic resistance R of unit buried power supply rail BPR Parasitic inductance L of unit buried power supply rail BPR Parasitic capacitance C of oxide layer BPR_ox Parasitic capacitance C of silicon substrate BPR_Si And parasitic conductance G of silicon substrate BPR_Si . The buried power rail and two adjacent buried power rails are mainly considered in the process of extracting the parasitic capacitance and parasitic conductance related to the buried power railInteraction of ground power rails. Parasitic parameters are extracted using Q3D tools or determined by the following formulas.
Specifically, parasitic resistance R of the unit buried power supply rail BPR The specific calculation formula of (2) is as follows:
parasitic inductance L of unit buried power supply rail BPR The specific calculation formula of (2) is as follows:
parasitic capacitance C of oxide layer BPR_ox The specific calculation formula of (2) is as follows:
parasitic capacitance C of silicon substrate BPR_Si The specific calculation formula of (2) is as follows:
Parasitic conductance G of silicon substrate BPR_Si The specific calculation formula of (2) is as follows:
wherein ρ is W Representing the resistivity of tungsten in a high temperature process; l (L) BPR Representing the length of the unit buried power rail; h is a BPR Representing the height of the buried power rail; w (w) BPR Representing the width of the buried power rail; mu (mu) 0 Magnetic permeability representing vacuum; gamma represents an empirical constant; epsilon ox Represents the relative dielectric constant of the oxide layer; epsilon 0 Dielectric constant representing vacuum; t is t BPR_ox Representing an oxide layerThickness; epsilon Si Represents the relative dielectric constant of silicon; t is t BPR_Si Representing the thickness of silicon medium between adjacent buried power rails; sigma (sigma) Si Indicating the conductivity of silicon.
As shown in fig. 7, which is a schematic diagram of an on-chip load equivalent current source, the on-chip load can be modeled as havingRise time, & gt>Fall time and->Periodic triangular wave current source for rest time. Setting a minimum current I according to actual power consumption conditions min And maximum current I max . The calculation formula is as follows:
P＝P Static +P Dynamic (1.19)
wherein P is Static Representing static power consumption, P Dynamic Represents dynamic power consumption, P represents total power consumption, V dd Representing the supply voltage.
As shown in fig. 8, an on-chip load equivalent current source is connected to each section of unit buried power supply rail, and a voltage source is connected to a welding point, so that a complete noise simulation circuit of the back power supply distribution network is obtained.
Further, the present embodiment describes the above method by experiments. And constructing a noise simulation circuit of a back power supply distribution network at the ADS, wherein model parameters are as follows:
table 1 basic parameters of noise simulation circuit for back side power distribution network
By controlling the variable method, different parameters in the noise simulation circuit of the back power supply distribution network are changed, the influence of each parameter on noise can be studied, and the simulation result is shown in the following table:
TABLE 2 Effect of solder joint spacing on Back Power distribution network noise
TABLE 3 influence of spacing of backside metal gridlines on backside Power distribution network noise
TABLE 4 influence of the spacing of micro through silicon vias on the Back Power distribution network noise
TABLE 5 influence of buried Power Rail aspect ratio on Back Power distribution network noise
TABLE 6 influence of MIM capacitance on backside Power distribution network noise
TABLE 7 influence of static Power consumption ratio on Back Power distribution network noise
Although the invention provides method operational steps as an example or a flowchart, more or fewer operational steps may be included based on conventional or non-inventive labor. The order of steps recited in the present embodiment is only one way of performing the steps in a plurality of steps, and does not represent a unique order of execution. When implemented by an actual device or client product, the method of the present embodiment or the accompanying drawings may be performed sequentially or in parallel (e.g., in a parallel processor or a multithreaded environment).
The apparatus or module set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. For convenience of description, the above devices are described as being functionally divided into various modules, respectively. The functions of the various modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention. Of course, a module that implements a certain function may be implemented by a plurality of sub-modules or a combination of sub-units.
The methods, apparatus or modules described in this invention may be implemented in computer readable program code means and the controller may be implemented in any suitable way, for example, the controller may take the form of a microprocessor or processor and a computer readable medium storing computer readable program code (e.g. software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (english: application Specific Integrated Circuit; abbreviated: ASIC), programmable logic controller and embedded microcontroller, examples of the controller including but not limited to the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller can be regarded as a hardware component, and means for implementing various functions included therein can also be regarded as a structure within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.
Some of the modules of the apparatus of the present invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
From the above description of embodiments, it will be apparent to those skilled in the art that the present invention may be implemented in software plus necessary hardware. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product or may be embodied in the implementation of data migration. The computer software product may be stored on a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., comprising instructions for causing a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to perform the methods described in the various embodiments or portions of the embodiments of the invention.
In this specification, each embodiment is described in a progressive manner, and the same or similar parts of each embodiment are referred to each other, and each embodiment is mainly described as a difference from other embodiments. All or portions of the present invention are operational with numerous general purpose or special purpose computer system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the present invention; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A noise simulation circuit for a back side power distribution network of an integrated circuit, comprising: the power supply voltage source, the back power supply distribution network equivalent circuit model and the on-chip load equivalent current source, wherein the back power supply distribution network equivalent circuit model specifically comprises: the circuit comprises a welding point equivalent circuit, a back metal grid equivalent circuit, a micro silicon through hole equivalent circuit and a buried power rail equivalent circuit;
the power supply voltage source is connected with the welding point equivalent circuit;
the welding point equivalent circuit is connected with the back metal grid equivalent circuit;
the back metal grid equivalent circuit is connected with the micro through silicon via equivalent circuit, wherein the back metal grid equivalent circuit comprises a plurality of same unit back metal grid equivalent circuits;
the micro through silicon via equivalent circuit is connected with the buried power rail equivalent circuit;
the buried power rail equivalent circuit is connected with the on-chip load equivalent current source, wherein the buried power rail equivalent circuit is formed by connecting a plurality of same unit buried power rail equivalent circuits in series.
2. The noise simulation circuit of a back side power distribution network of an integrated circuit according to claim 1, wherein the solder joint equivalent circuit specifically comprises: first parasitic resistance R of welding point Bond Second parasitic resistance R of welding point Bond First parasitic inductance L of welding point/2 Bond Second parasitic inductance L of welding point Bond Parasitic capacitance C around/2 and solder joint Bond ；
First parasitic resistance R of the welding point Bond First parasitic inductance L of the welding point Bond Second parasitic inductance L of the welding point Bond 2 and a second parasitic resistance R of said solder joint Bond 2, sequentially connecting in series;
parasitic capacitance C around the solder joint Bond A first parasitic resistor R connected in parallel with the welding point Bond 2 and a second parasitic resistance R of said solder joint Bond Between/2.
3. The noise simulation circuit of a back side power distribution network of an integrated circuit according to claim 1, wherein the unit back side metal grid equivalent circuit specifically comprises: a first and second lateral circuit, a longitudinal circuit and a series circuit;
the first and second lateral circuits each include: first parasitic inductance L of unit BSM2 layer grid line BSM2 First parasitic resistance R of/2, cell BSM2 layer grid line BSM2 Second parasitic resistance R of/2, cell BSM2 layer grid lines BSM2 Second parasitic inductance L of/2, unit BSM2 layer grid line BSM2 2 and MIM capacitor C MIM ；
First parasitic inductance L of the cell BSM2 layer grid line BSM2 First parasitic resistance R of the cell BSM2 layer grid line BSM2 Second parasitic resistance R of the cell BSM2 layer grid line BSM2 2 and the unit BSM2 layer grid linesSecond parasitic inductance L BSM2 2, sequentially connecting in series; the MIM capacitor C MIM First parasitic resistor R connected in parallel with grid line of BSM2 layer of the unit BSM2 Second parasitic resistance R of/2 and the cell BSM2 layer grid line BSM2 Between/2;
the longitudinal circuit comprises: n units of BSM1 layer grid line equivalent circuits connected in series in sequence, wherein n is expressed as the interval p of adjacent BSM2 layer grid lines BSM2 Distance p from adjacent buried power rail BPR Is a ratio of (2);
the equivalent circuit of the cell BSM1 layer grid line comprises parasitic inductance L of the cell BSM1 layer grid line connected in series BSM1 Parasitic resistance R of cell BSM1 layer grid line BSM1 ；
The series circuit comprises parasitic resistance R of through holes connected in series in sequence Via Parasitic inductance L of the sum via Via ；
The first lateral circuit and the longitudinal circuit are connected by the series circuit.
4. The noise simulation circuit of a back side power distribution network of an integrated circuit according to claim 3, wherein said parasitic resistance R of cell BSM1 layer grid lines BSM1 The specific calculation formula of (2) is expressed as follows:
parasitic resistance R of the cell BSM2 layer grid line BSM2 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the cell BSM1 layer grid line BSM1 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the cell BSM2 layer grid line BSM2 The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the via hole Via The specific calculation formula of (2) is expressed as follows:
parasitic resistance R of the via hole Via The specific calculation formula of (2) is expressed as follows:
wherein ρ is Cu Represents the resistivity of copper; l (L) BSM1 Representing the length of the unit BSM1 layer grid line; h is a BSM1 Representing the height of the BSM1 layer grid lines; w (w) BSM1 Representing the width of the BSM1 layer grid line; l (L) BSM2 Representing the length of the unit BSM2 layer grid lines; h is a BSM2 Representing the height of the BSM2 layer grid lines; w (w) BSM2 Representing the width of the BSM2 layer grid lines; mu (mu) 0 Magnetic permeability representing vacuum; gamma represents an empirical constant; h is a Via Representing the height of the through hole; w (w) Via Representing the side length of the through hole.
5. The noise simulation circuit of a back side power distribution network of an integrated circuit according to claim 1, wherein the equivalent circuit of the micro through silicon via specifically comprises:
first parasitic resistance R of micro silicon through hole μTSV Second parasitic resistance R of micro silicon through hole μTSV First parasitic inductance L of micro silicon through hole μTSV Second parasitic electricity of micro silicon through holeSense of L μTSV Parasitic capacitance C of/2, oxide layer μTSV_ox Parasitic capacitance C of silicon substrate μTSV_Si And parasitic conductance G of silicon substrate μTSV_Si ；
First parasitic inductance L of the micro silicon through hole μTSV First parasitic resistance R of micro silicon through hole μTSV Second parasitic inductance L of micro silicon through hole μTSV Second parasitic inductance L of/2 and said micro through silicon via μTSV 2, sequentially connecting in series;
parasitic capacitance C of the oxide layer μTSV_ox A first parasitic resistor R connected in parallel with the micro silicon through hole μTSV 2 and a second parasitic resistance R of the micro through silicon via μTSV Between/2;
parasitic conductance G of the silicon substrate μTSV_Si And parasitic capacitance C of the silicon substrate μTSV_Si Parasitic capacitance C connected in series with two oxide layers μTSV_ox Between them.
6. The noise simulation circuit of a back side power distribution network of an integrated circuit of claim 5, wherein the first parasitic resistance R of the micro through silicon via μTSV Second parasitic resistance R of/2 and micro through silicon via μTSV Adding/2 to obtain parasitic resistance R of micro silicon through hole μTSV ；
First parasitic inductance L of the micro silicon through hole μTSV Second parasitic inductance L of/2 and said micro through silicon via μTSV Adding/2 to obtain parasitic inductance L of micro silicon through hole μTSV 。
7. The noise simulation circuit of a back side power distribution network of an integrated circuit according to claim 6, wherein the parasitic resistance R of the micro through silicon via μTSV The specific calculation formula of (2) is expressed as follows:
parasitic inductance L of the micro silicon through hole μTSV The specific calculation formula of (2) is expressed as follows:
parasitic capacitance C of the oxide layer μTSV_ox The specific calculation formula of (2) is expressed as follows:
parasitic capacitance C of the silicon substrate μTSV_Si The specific calculation formula of (2) is expressed as follows:
parasitic conductance G of the silicon substrate μTSV_Si The specific calculation formula of (2) is expressed as follows:
wherein ρ is Cu Represents the resistivity of copper; h is a μTSV Representing the height of the micro through silicon vias; r is (r) μTSV Representing the radius of the micro through silicon via; mu (mu) 0 Magnetic permeability representing vacuum; epsilon ox Represents the relative dielectric constant of the oxide layer; epsilon 0 Dielectric constant representing vacuum; t is t μTSV_ox Indicating the thickness of the oxide layer; epsilon Si Represents the relative dielectric constant of silicon; s is(s) μTSV Representing the distance between the microsilicon via and the surrounding microsilicon via.
8. The noise simulation circuit of a back side power distribution network of an integrated circuit according to claim 1, wherein the equivalent circuit of the unit buried power rail comprises in particular: first parasitic resistance R of unit buried power rail BPR Second of unit buried power supply railParasitic resistance R BPR First parasitic inductance L of unit buried power rail BPR Second parasitic inductance L of unit buried power supply rail BPR First parasitic capacitance C of oxide layer BPR_ox Second parasitic capacitance C of oxide layer BPR_ox Parasitic capacitance C of silicon substrate BPR_Si And parasitic conductance G of silicon substrate BPR_Si ；
First parasitic inductance L of the unit buried power rail BPR First parasitic resistance R of said unit buried power rail BPR 2, a second parasitic resistance of the unit buried power supply rail and a second parasitic inductance L of the unit buried power supply rail BPR 2, sequentially connecting in series;
first parasitic capacitance C of the oxide layer BPR_ox First parasitic resistance R of the unit buried power rail connected in parallel BPR 2, the second parasitic resistance of the unit buried power rail is between;
parasitic conductance G of the silicon substrate BPR_Si And parasitic capacitance C of the silicon substrate BPR_Si A first parasitic capacitance C connected in series with the oxide layer BPR_ox And a second parasitic capacitance C of the oxide layer BPR_ox Between them.
9. The noise simulation circuit of a back side power distribution network of an integrated circuit of claim 8 wherein the first parasitic resistance R of the cell-buried power rail BPR Second parasitic resistance R of/2 and cell buried power supply rail BPR Adding/2 to obtain parasitic resistance R of unit buried power rail BPR ；
First parasitic inductance L of the unit buried power rail BPR 2 and a second parasitic inductance L of the unit buried power supply rail BPR Adding/2 to obtain parasitic inductance L of unit buried power rail BPR 。
10. The noise simulation circuit of a back side power distribution network of an integrated circuit according to claim 9, wherein the parasitic resistance R of the cell-buried power rail BPR The specific calculation formula of (2) is：
Parasitic inductance L of the unit buried power rail BPR The specific calculation formula of (2) is as follows:
parasitic capacitance C of the oxide layer BPR_ox The specific calculation formula of (2) is as follows:
parasitic capacitance C of the silicon substrate BPR_Si The specific calculation formula of (2) is as follows:
parasitic conductance G of the silicon substrate BPR_Si The specific calculation formula of (2) is as follows:
wherein ρ is W Representing the resistivity of tungsten in a high temperature process; l (L) BPR Representing the length of the unit buried power rail; h is a BPR Representing the height of the buried power rail; w (w) BPR Representing the width of the buried power rail; mu (mu) 0 Magnetic permeability representing vacuum; gamma represents an empirical constant; epsilon ox Represents the relative dielectric constant of the oxide layer; epsilon 0 Dielectric constant representing vacuum; t is t BPR_ox Indicating the thickness of the oxide layer; epsilon Si Represents the relative dielectric constant of silicon; t is t BPR_Si Representing the thickness of silicon medium between buried power railsA degree; sigma (sigma) Si Indicating the conductivity of silicon.
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