CN117762713A

CN117762713A - Method and device for testing register and electronic equipment

Info

Publication number: CN117762713A
Application number: CN202311811954.6A
Authority: CN
Inventors: 孙也婷; 芦蓉; 巫瑞
Original assignee: Ziguang Tongxin Microelectronics Co Ltd
Current assignee: Ziguang Tongxin Microelectronics Co Ltd
Priority date: 2023-12-26
Filing date: 2023-12-26
Publication date: 2024-03-26

Abstract

The application relates to the technical field of chip testing, and discloses a method for testing registers, which comprises the following steps: determining the type of the register; the register is protected by a hardware security mechanism; and carrying out illegal operation on a security mechanism of the register according to the type of the register to obtain a test result. The CPU identifies the type of the register protected by the hardware security mechanism, and tests the register by illegally operating the security mechanism of the register according to the type of the register. In the related art, a register protected by a hardware security mechanism cannot be tested by aiming at read-write attribute test of a key register, and the application can realize the test of the register protected by the hardware security mechanism. The application also discloses a device for testing the register and electronic equipment.

Description

Method and device for testing register and electronic equipment

Technical Field

The present invention relates to the technical field of chip testing, and for example, to a method and apparatus for testing registers, and an electronic device.

Background

At present, with the rapid development of automobile electronic technology, the functional complexity of the automobile is higher and higher, and the safety requirement on an automobile chip is higher and higher. The road vehicle function safety indicates that the automobile operating system and the hardware security chip should detect faults in the configuration registers of the processing unit as early as possible. The implementation of the chip function is accomplished by performing different configurations on the registers, so that functional security verification on the registers is required in the chip verification process.

In order to perform functional security verification on a register in a chip, in related technology, a test module is developed for the register in the chip to test, a key register is selected from the registers, and read-write attribute tests are performed on the key registers through the test module to verify the functions of the registers.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

in the related art, in order to verify the function of a register in a chip, a test module is used for testing the read-write attribute of a key register. However, the read-write attribute test cannot be applied to registers protected by the hardware security mechanism, so that the related art cannot test registers protected by the hardware security mechanism in the chip, and the reliability of the functional security verification result is reduced.

It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a method and a device for testing a register and electronic equipment, so as to test the register protected by a hardware security mechanism.

In some embodiments, the method comprises: determining the type of the register; the register is protected by a hardware security mechanism; and carrying out illegal operation on a security mechanism of the register according to the type of the register to obtain a test result.

Optionally, the types of registers include a register protected by a specified password, a register protected by chip lifecycle rights, a register protected by user/administrator access rights, a register protected by system watchdog clock controlled access time, a register protected by bit redundancy security mechanism, or a register protected by acceptor server access rights.

Optionally, in the case that the register is a register protected by a specified password, performing an illegal operation on a security mechanism of the register includes: acquiring a physical address, a locking password and a locking mode of a register; and performing illegal operation on a security mechanism of the register according to the physical address, the locking password and the locking mode of the register.

Optionally, performing illegal operations on a security mechanism of the register according to a physical address, a locking password and a locking manner of the register includes: judging whether the physical address of the register is legal or not; checking whether a test value can be written into the register by using a wrong locking mode to input a wrong locking password under the condition that the physical address of the register is legal; it is checked whether an interrupt signal is issued.

Optionally, in the case that the register is a register protected by the chip lifecycle authority, performing an illegal operation on a security mechanism of the register includes: acquiring a physical address of a register and a life cycle of allowed access; and performing illegal operation on the security mechanism of the register according to the physical address of the register and the life cycle of the allowed access.

Optionally, performing illegal operations on a security mechanism of the register according to a physical address of the register and a life cycle of the allowed access, including: judging whether the physical address of the register is legal or not; under the condition that the physical address of the register is legal, the register is illegally configured in a life cycle state of non-allowed access; it is checked whether an exception is entered.

Optionally, in the case that the register is a register protected by user/administrator access rights, performing an illegal operation on a security mechanism of the register includes: acquiring a physical address of a register; and performing illegal operation on a security mechanism of the register according to the physical address of the register.

Optionally, performing illegal operation on a security mechanism of the register according to a physical address of the register includes: judging whether the physical address of the register is legal or not; under the condition that the physical address of the register is legal, the register of the manager attribute is illegally accessed in a user mode; it is checked whether an exception is entered.

Optionally, in the case that the register is a register whose access time is controlled by a system watchdog clock, performing an illegal operation on a security mechanism of the register includes: acquiring a physical address and a time threshold of a register; and performing illegal operation on a security mechanism of the register according to the physical address and the time threshold of the register.

Optionally, performing illegal operations on a security mechanism of the register according to a physical address and a time threshold of the register includes: judging whether the physical address of the register is legal or not; accessing the physical address of the register outside the time threshold under the condition that the physical address of the register is legal; it is checked whether a reset is generated.

Optionally, in the case that the register is a register that is cared for by a bit redundancy security mechanism, performing an illegal operation on the security mechanism of the register includes: acquiring the physical address and the position of redundant bits of a register; and performing illegal operation on a security mechanism of the register according to the physical address of the register and the position of the redundant bit.

Optionally, performing illegal operations on the security mechanism of the register according to the physical address of the register and the position of the redundancy bit includes: judging whether the physical address of the register is legal or not; under the condition that the physical address of the register is legal, an illegal value is injected at the position of the redundant bit; it is checked whether an alarm signal is issued or whether emergency braking actions are occurring.

Optionally, in the case that the register is a register protected by access rights of the host server, performing illegal operations on a security mechanism of the register includes: acquiring a physical address of a register and a main server type; and performing illegal operation on a security mechanism of the register according to the physical address of the register and the type of the main server.

Optionally, performing illegal operations on the security mechanism of the register according to the physical address of the register and the type of the main server includes: judging whether the physical address of the register is legal or not; under the condition that the physical address of the register is legal, switching to a main server without access permission designated by a user; it is checked whether an exception is entered.

In some embodiments, the apparatus comprises: a processor and a memory storing program instructions, characterized in that the processor is configured to perform the above-mentioned method for register testing when running the program instructions.

In some embodiments, the electronic device comprises: an electronic device body; the device for testing the register is arranged on the electronic equipment body.

The method and the device for testing the register and the electronic equipment provided by the embodiment of the disclosure can realize the following technical effects:

the embodiment of the disclosure can identify the type of the register protected by the hardware security mechanism, and according to the type of the register, the security mechanism of the register is illegally operated to realize the test of the register. In the related art, a register protected by a hardware security mechanism cannot be tested for read-write attribute test of a key register, and the embodiment of the disclosure can realize the test of the register protected by the hardware security mechanism.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a system environment for register testing provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a method for register testing provided by embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a test processing unit provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a method for testing a user/administrator access rights protected register provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another method for register testing provided by embodiments of the present disclosure;

FIG. 6 is a schematic diagram of an apparatus for register testing provided by an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.

As shown in connection with fig. 1, a system environment for register testing includes: a central processor 100 and a memory controller 200.

In the embodiment of the disclosure, the cpu 100 is capable of receiving a data instruction sent by the memory controller 200, and the cpu 100 is capable of determining a corresponding physical storage address according to the data instruction, so as to operate a register. In the process of operating the register, the cpu 100 checks whether the phenomenon meets the expectations after writing the test value according to the hardware security mechanism. Further, the cpu 100 can illegally access registers protected by the hardware security mechanism, check whether the phenomenon meets the expected design of the fault response circuit, automatically generate test results using script, and print register information of test failure.

As shown in conjunction with fig. 2, an embodiment of the present disclosure provides a method for register testing, including:

s01, the central processing unit determines the type of a register, wherein the register is protected by a hardware security mechanism.

S02, the central processing unit carries out illegal operation on a security mechanism of the register according to the type of the register to obtain a test result.

In the embodiment of the disclosure, the embodiment of the disclosure can identify the type of the register protected by the hardware security mechanism, and according to the type of the register, the security mechanism of the register is illegally operated to realize the test of the register. In the related art, a register protected by a hardware security mechanism cannot be tested for read-write attribute test of a key register, and the embodiment of the disclosure can realize the test of the register protected by the hardware security mechanism.

In the embodiment of the disclosure, the registers include a plurality of different types of registers, and are all registers protected by a hardware security mechanism. The embodiment of the disclosure can test the register to realize the test of the register protected by the hardware security mechanism and improve the coverage rate of the test. Further, the embodiment of the disclosure can test according to the type of the register so as to improve the accuracy of the register test.

In practical application, as shown in fig. 3, the central processing unit can select different test functions and processing functions in the test processing unit according to different types of registers to perform functional security verification. And, the result of the verification is stored in the test information storage unit.

In the embodiment of the disclosure, the central processing unit can acquire the physical address of the register to judge whether the physical address of the register is legal or not, so that the verification system can be prevented from triggering abnormality, and further the normal operation of the verification system is ensured to be free from being interfered by other fault factors. For the register protected by the appointed password, the central processing unit can acquire the locking password and locking mode configured by the user. According to the locking password and the locking mode, the central processing unit can perform illegal operation on the security mechanism of the register to obtain a test result.

In the embodiment of the disclosure, the central processing unit can judge whether the physical address of the register is legal or not, and can prevent the verification system from triggering abnormality, thereby ensuring that the verification system operates normally and is not interfered by other fault factors. Under the condition that the physical address of the register is legal, the functional safety of the register can be verified by checking whether a test value can be written into the register and whether an interrupt signal is sent out, so that the test of the register protected by the appointed password is realized.

In the embodiment of the disclosure, the central processing unit can acquire the physical address of the register to judge whether the physical address of the register is legal or not, so that the verification system can be prevented from triggering abnormality, and further the normal operation of the verification system is ensured to be free from being interfered by other fault factors. For registers protected by the chip lifecycle rights, the central processor can acquire the lifecycle of the allowed access. According to the life cycle of the allowed access, the central processing unit can perform illegal operation on the security mechanism of the register to obtain a test result.

In the embodiment of the disclosure, the central processing unit can judge whether the physical address of the register is legal or not, and can prevent the verification system from triggering abnormality, thereby ensuring that the verification system operates normally and is not interfered by other fault factors. Under the condition that the physical address of the register is legal, whether the register enters an abnormality or not can be checked, the functional safety of the register can be verified, and the test of the register protected by the life cycle authority of the chip can be realized.

In the embodiment of the disclosure, the central processing unit can acquire the physical address of the register to judge whether the physical address of the register is legal or not, so that the verification system can be prevented from triggering abnormality, and further the normal operation of the verification system is ensured to be free from being interfered by other fault factors. Aiming at the register protected by the access authority of the user/manager, the central processing unit can perform illegal operation on the security mechanism of the register to obtain a test result.

In the embodiment of the disclosure, the central processing unit can judge whether the physical address of the register is legal or not, and can prevent the verification system from triggering abnormality, thereby ensuring that the verification system operates normally and is not interfered by other fault factors. Under the condition that the physical address of the register is legal, whether the register enters an abnormality or not can be checked, the functional safety of the register can be verified, and the test of the register protected by the access authority of a user/manager can be realized.

In practical application, if the register is a register protected by the access authority of the user/administrator, as shown in fig. 4, when the system is legal, the system should be at EL2 (Exception Level 2) Level, and the system needs to be switched to the user mode for illegal writing.

In the embodiment of the disclosure, the central processing unit can acquire the physical address of the register to judge whether the physical address of the register is legal or not, so that the verification system can be prevented from triggering abnormality, and further the normal operation of the verification system is ensured to be free from being interfered by other fault factors. The central processor is able to obtain a time threshold for registers that are clocked by the system watchdog clock to access time. According to the time threshold, the central processing unit can perform illegal operation on the security mechanism of the register to obtain a test result.

In the embodiment of the disclosure, the central processing unit can judge whether the physical address of the register is legal or not, and can prevent the verification system from triggering abnormality, thereby ensuring that the verification system operates normally and is not interfered by other fault factors. Under the condition that the physical address of the register is legal, whether reset is generated or not is checked, the functional safety of the register can be verified, and the test of the register with access time controlled by the system watchdog clock is realized.

In the embodiment of the disclosure, the central processing unit can acquire the physical address of the register to judge whether the physical address of the register is legal or not, so that the verification system can be prevented from triggering abnormality, and further the normal operation of the verification system is ensured to be free from being interfered by other fault factors. For registers that are under the care of the bit redundancy security mechanism, the central processor can obtain the location of the redundancy bits. According to the position of the redundant bit, the central processing unit can perform illegal operation on the security mechanism of the register to obtain a test result.

In the embodiment of the disclosure, the central processing unit can judge whether the physical address of the register is legal or not, and can prevent the verification system from triggering abnormality, thereby ensuring that the verification system operates normally and is not interfered by other fault factors. Under the condition that the physical address of the register is legal, whether an alarm signal is sent or whether emergency braking action is generated is checked, so that the functional safety of the register can be verified, and the test of the register cared by a bit redundancy safety mechanism is realized.

In the embodiment of the disclosure, the central processing unit can acquire the physical address of the register to judge whether the physical address of the register is legal or not, so that the verification system can be prevented from triggering abnormality, and further the normal operation of the verification system is ensured to be free from being interfered by other fault factors. The central processor is able to obtain the main server type for the register protected by the access rights of the main server. According to the type of the main server, the central processing unit can perform illegal operation on the security mechanism of the register to obtain a test result.

In the embodiment of the disclosure, the central processing unit can judge whether the physical address of the register is legal or not, and can prevent the verification system from triggering abnormality, thereby ensuring that the verification system operates normally and is not interfered by other fault factors. Under the condition that the physical address of the register is legal, whether the register enters an exception or not can be checked, the functional safety of the register can be verified, and the test of the register cared by a bit redundancy safety mechanism can be realized.

Optionally, the method for register testing further comprises generating a test report according to the test result.

As shown in conjunction with fig. 5, an embodiment of the present disclosure provides another method for register testing, comprising:

s11, the central processing unit determines the type of a register, wherein the register is protected by a hardware security mechanism.

S12, the central processing unit performs illegal operation on a security mechanism of the register according to the type of the register to obtain a test result.

S13, the central processing unit generates a test report according to the test result, the physical address of the register and the type of the register.

In the embodiment of the disclosure, the embodiment of the disclosure can identify the type of the register protected by the hardware security mechanism, and according to the type of the register, the security mechanism of the register is illegally operated to realize the test of the register. In the related art, a register protected by a hardware security mechanism cannot be tested by a read-write attribute test of a key register, and the embodiment of the disclosure can realize the test of the register protected by the hardware security mechanism through a test processing unit.

Further, the generated test report comprises a test result, a physical address of the register and a type of the register, and a user can obtain test information from the test report.

As shown in connection with FIG. 6, an embodiment of the present disclosure provides an apparatus 70 for register testing, including a processor 700 and a memory 701. Optionally, the apparatus 70 may further comprise a communication interface (Communication Interface) 702 and a bus 703. The processor 700, the communication interface 702, and the memory 701 may communicate with each other through the bus 703. The communication interface 702 may be used for information transfer. The processor 700 may call logic instructions in the memory 701 to perform the method for register testing of the above-described embodiments.

Further, the logic instructions in the memory 701 may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product.

The memory 701 is used as a computer readable storage medium for storing a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 700 performs functional applications as well as data processing by running program instructions/modules stored in the memory 701, i.e. implements the method for register testing in the above-described embodiments.

Memory 701 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory, and may also include a nonvolatile memory.

The embodiment of the disclosure provides an electronic device, comprising: an electronic device body, and the above-described apparatus 70 for register testing. The means 70 for register testing is mounted to the electronic device body. The mounting relationship described herein is not limited to being placed inside the body of the electronic device, but also includes mounting connections with other components of the electronic device, including but not limited to physical connections, electrical connections, or signal transmission connections, etc. Those skilled in the art will appreciate that the means 70 for register testing may be adapted to a viable electronics body, thereby enabling other viable embodiments.

Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. While the aforementioned storage medium may be a non-transitory storage medium, such as: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, or the like, which can store program codes.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A method for register testing, comprising:

determining the type of the register; the register is protected by a hardware security mechanism;

and carrying out illegal operation on a security mechanism of the register according to the type of the register to obtain a test result.

2. The method of claim 1, wherein the type of register comprises a register protected by a specified password, a register protected by chip lifecycle rights, a register protected by user/administrator access rights, a register clocked by a system watchdog clock access time, a register protected by a bit redundancy security mechanism, or a register protected by a host server access rights.

3. The method of claim 2, wherein, in the case where the register is a register protected by a specified password, performing an illegal operation on a security mechanism of the register comprises:

acquiring a physical address, a locking password and a locking mode of a register;

and performing illegal operation on a security mechanism of the register according to the physical address, the locking password and the locking mode of the register.

4. The method of claim 2, wherein, in the case where the register is a register protected by chip lifecycle rights, performing an illegal operation on a security mechanism of the register comprises:

acquiring a physical address of a register and a life cycle of allowed access;

and performing illegal operation on the security mechanism of the register according to the physical address of the register and the life cycle of the allowed access.

5. The method of claim 2, wherein, in the case that the register is a register protected by user/administrator access rights, performing an illegal operation on a security mechanism of the register comprises:

acquiring a physical address of a register;

and performing illegal operation on a security mechanism of the register according to the physical address of the register.

6. The method of claim 2, wherein, in the case where the register is a register whose access time is controlled by a system watchdog clock, performing an illegal operation on a security mechanism of the register comprises:

acquiring a physical address and a time threshold of a register;

and performing illegal operation on a security mechanism of the register according to the physical address and the time threshold of the register.

7. The method of claim 2, wherein, in the case where the register is a register that is cared for by a bit redundancy security mechanism, performing an illegal operation on the security mechanism of the register comprises:

acquiring the physical address and the position of redundant bits of a register;

and performing illegal operation on a security mechanism of the register according to the physical address of the register and the position of the redundant bit.

8. The method of claim 2, wherein, in the case where the register is a register protected by access rights of the host server, performing an illegal operation on a security mechanism of the register comprises:

acquiring a physical address of a register and a main server type;

and performing illegal operation on a security mechanism of the register according to the physical address of the register and the type of the main server.

9. An apparatus for register testing comprising a processor and a memory storing program instructions, wherein the processor is configured, when executing the program instructions, to perform the method for register testing of any of claims 1 to 8.

10. An electronic device, comprising:

an electronic device body;

the apparatus for register testing of claim 9, mounted to the electronic device body.