CN117762500B - High-precision data optimization method for line parameters and operation system thereof - Google Patents
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Abstract
The invention belongs to the technical field of power systems, and particularly relates to a high-precision data optimization method of line parameters and an operation system thereof. The high-precision data optimizing operation system of the line parameters comprises 6 paths of ADC chips, an FPGA chip, a memory chip and a singlechip, wherein the 6 paths of ADC chips are electrically connected with the FPGA chip, the FPGA chip is respectively electrically connected with the memory chip and the singlechip, and an IP core is burnt in the FPGA chip. The invention changes the uncontrollable accuracy of the analog circuit from component error into a customized IP core with high accuracy, fixed and controllable, simplifies the test flow of producing the analog circuit, and solves the problem that the component affects the accuracy along with the aging of time. By adopting a three-phase parity data acquisition method, parity data is synchronously acquired into a data cache, further harmonic components of signals are rapidly analyzed through an IP core customized by an FPGA, the harmonic components are synchronously filtered, phase angles and voltage and current parameters with higher precision are reversely calculated, and therefore higher-precision data calculation is participated.
Description
Technical Field
The invention belongs to the technical field of power systems, and particularly relates to a high-precision data optimization method of line parameters and an operation system thereof.
Background
The electric power system is one of the important infrastructures of modern society and plays a vital role in human life and economic development. Line parameters, such as resistance, inductance, capacitance, etc., are important factors in determining the stability and reliability of the power system. With the increase of the scale of the power system and the progress of the technology, the requirement on the measurement accuracy of the line parameters is also higher and higher. However, due to the influence of many factors, such as equipment aging, environmental changes, etc., the actual values of the line parameters often deviate from the theoretical values to some extent. Therefore, it is necessary to build a high-precision data optimization system to ensure the accuracy of line parameters.
The conventional line parameter testing equipment is divided into a pure power frequency signal line parameter tester and a different frequency normal line parameter tester. The most traditional power frequency adopts 50Hz pure power frequency to test the signal line parameters, and the product has the characteristics of large volume, heavy weight and low price because of being easily interfered by the signal of the edge line. The different frequency rule adopts SPWM waves to carry out signal modulation, 55Hz and 45Hz which are close to 50Hz are respectively adopted to carry out testing, and then average value is taken, so that the power frequency interference of 50Hz is avoided, and stronger anti-interference performance is realized. The method adopts the modulated wave power component to replace the original high-power frequency voltage regulator, so that the volume is greatly reduced, and the method is gradually and widely applied.
Although the line parameter testing instrument of the different-frequency method is more commonly applied due to light weight and strong anti-interference capability, the accuracy is generally not high due to the fact that the line parameter testing instrument is tested by adopting a modulation wave method and is affected by modulation signals.
Therefore, there is a need to design a high-precision data optimization method and an operation system for line parameters, so as to optimize specific data, thereby greatly improving the precision of the existing different-frequency normal line parameter testing instrument.
Disclosure of Invention
Aiming at the technical problems, the invention provides a high-precision data optimization method of line parameters and an operation system thereof.
The technical scheme of the invention is as follows: a high-precision data optimization method of line parameters comprises the following steps:
1) Collecting a first modulated wave with the power frequency of Z1 and a second modulated wave with the power frequency of Z2, wherein Z1 is less than 50Hz, and Z1+Z2=100 Hz;
After the first modulated wave is stable, sampling three-phase voltage and current data with the size of Q at a high-speed sampling rate R which is 2 times larger than the fundamental wave frequency value of the first modulated wave, wherein the sampling period is H1;
After the second modulation wave is stable, sampling three-phase voltage and current data with the size of Q at the same high-speed sampling rate R, wherein the sampling period is H2;
The sampled data satisfies the following formula:
2) Synchronously filtering noise signals of more than 100Hz of three-phase voltage and current data by adopting a filtering algorithm, and storing a waveform diagram of the filtered signals into a memory chip for further data processing;
3) Analyzing the time of all zero crossings based on the waveform diagram obtained in the step 2), then carrying out data calculation on the time difference between the zero crossings of the unidirectional parity current and the zero crossings of the voltage to obtain phase angle information, respectively averaging the phase angles of the first modulation wave and the second modulation wave, and finally averaging the average value data of the first modulation wave and the average value data of the second modulation wave to obtain 50Hz phase angle data;
Capturing a rising zero point:
capturing a descending zero point:
And then calculating the phase difference:
Wherein R is high speed Sampling rate of/>For modulating wave basic frequency, phi is a phase angle, N1 is a digital position code of a parity voltage zero crossing point, and N2 is a digital position code of a parity current zero crossing point;
Wherein: active power on three phases of alternating current A, B, C under corresponding frequency; /(I) Reactive power on three phases of alternating current A, B, C under corresponding frequency;
4) Based on:
respectively calculating accurate effective values of the voltage and the current of the first modulation wave and the second modulation wave;
Wherein: y is the true effective value of the alternating current signal, and f (x) is the first modulated wave Data of all periods sampled or second modulated wave/>The data of all the periods sampled, T is the number of corresponding periods, the upper half is the integral of the whole over the absolute value of f (x), and the integral standard formulas are the integral.
Preferably, the Z1 is greater than 40Hz and less than 50Hz, and z1+z2=100 Hz.
Preferably, after the first modulated wave with the power frequency of 45Hz is stabilized, sampling the data size of 100M of three-phase voltage and current data at a high-speed sampling rate of 50M, wherein the sampling period is 90;
After the second modulated wave with the power frequency of 55Hz is stabilized, sampling three-phase voltage and current data with the same size at the same high-speed sampling rate, wherein the sampling period is 110;
The sampled data satisfies the following formula:
Preferably, in step 2), the filtering algorithm is:
k is the sampling length, the filtering parameter is designed as a 10-order 100Hz low-pass filter, and hann window windowing processing is adopted, wherein: x (i) is a sampling sequence signal, i is a sequence label of the sampling sequence signal, h (n) is a convolution factor of a filtering parameter, and n is a sequence number after convolution.
Preferably, in step 4), the method further comprises the step of reversely deducing the resistance and reactance data in the line based on the accurate effective values of the voltage and the current.
The high-precision data optimization operation system for the line parameters comprises 6 paths of ADC chips, an FPGA chip, a memory chip and a singlechip, wherein the 6 paths of ADC chips are electrically connected with the FPGA chip, the FPGA chip is respectively electrically connected with the memory chip and the singlechip, an IP core is burnt in the FPGA chip, and the IP core is used for operating the high-precision data optimization method for the line parameters.
Preferably, the 6-path ADC chip adopts a three-phase parity data acquisition method, and the FPGA chip processes three-phase power voltage and current signals in a parallel processing mode.
Preferably, the singlechip is provided with a Bluetooth transmission port, the singlechip is electrically connected with the display equipment, and the singlechip can output SPWM signals.
Preferably, the memory chip is a ddr3 memory chip.
The beneficial effects of the invention are as follows:
(1) The FPGA chip is used for processing a large amount of data in parallel and accurately calculating, and the calculation result is only transmitted to the singlechip, so that the working efficiency of the singlechip is greatly saved;
(2) The analog circuit precision is changed from uncontrollable component error into customized IP core with high precision, fixed and controllable, so that the test flow of producing analog circuit is simplified, and the problem of influencing the precision of components along with time aging is solved;
(3) All signals adopt unified FIR filters and filter parameters, and after all data are normalized, the result is not affected, but the data precision is greatly improved;
according to the invention, a three-phase parity data acquisition method is adopted, parity data is synchronously acquired into a data cache, then harmonic components of signals are rapidly analyzed through an IP core customized by an FPGA, and synchronously filtered harmonic components are filtered, so that phase angle and voltage and current parameters with higher precision are reversely calculated, and the data calculation with higher precision is participated.
Drawings
Figure 1 is a schematic diagram of the hardware architecture of the present invention,
Figure 2 is a schematic view of data acquisition,
Figure 3 is a graph of the amplitude response of the filter,
Figure 4 is a pole diagram of the filter when the system is in steady state,
Figure 5 is a graph comparing the original signal and the filtered effects,
Figure 6 is a schematic view of phase angle calculation,
Figure 7 is an internal computing scheme of an IP core,
Figure 8 is a flow chart of an IP core,
Fig. 9 is a comprehensive result diagram of the IP core.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the embodiment provides a high-precision data optimization method for line parameters, which comprises a 6-path ADC chip, an FPGA chip, a memory chip and a singlechip, wherein the 6-path ADC chip is electrically connected with the FPGA chip, the FPGA chip is electrically connected with the memory chip and the singlechip respectively, and an IP core is burned in the FPGA chip.
In this embodiment, the singlechip is equipped with bluetooth transmission mouth and is used for with mobile device linkage such as cell-phone, tablet, and the singlechip still with display device electric connection, the singlechip can output SPWM signal. The FPGA chip and the singlechip with specific functions can be selected by the person skilled in the art according to requirements, and the FPGA chip and the singlechip are conventional technology and are not repeated.
Referring to FIG. 7, in the present embodiment
1) DDR3 and FPGA interface bit fixed interface, the description is not repeated.
2) The Busy signal is the high level of the algorithm chip when the algorithm chip calculates data, and the high level of the calculation completion signal is set when the calculation is completed.
3) The Ready signal provides a signal for the singlechip, and when the calculation completion signal is set to a high level, the Ready signal can be set to be high to match with the clk data clock signal and the data_valid (data valid signal) of the FPGA and bus data, so that the data receiving process can be realized.
Referring to fig. 2, in this embodiment, a three-phase parity data acquisition method is adopted by the 6-channel ADC chip, and a parallel processing mode is adopted by the FPGA chip to process three-phase voltage and current signals.
Specifically, in this embodiment, the 6-channel ADC chip uses an AD9226 chip with a sampling rate of 65M with 12-bit precision to perform co-position high-speed acquisition on the 3-phase voltage and current signals, so as to ensure a data height and time period and perform signal processing with the same algorithm, thereby ensuring that the calculated phase signal precision reaches the highest.
The traditional 6-channel sampling analog signal enters the ADC through a direct acquisition mode, so that certain errors occur in the phases of the current and voltage filtering signals caused by factors such as errors of components and the like of the analog filtering circuit, and the product precision inconsistency caused by error attributes of the components after the product quantity is caused.
Since the multi-channel current and voltage parity data high-speed acquisition needs to have a large amount of data memory, a conventional DSP or a singlechip adopts a pipelined calculation mode, and when complex calculation of a large amount of data is involved, calculation speed and calculation accuracy are often limited due to calculation force and operation efficiency. In the embodiment, the DDR3 chip with 4Gbit is used for temporary storage of a data algorithm, and after the FPGA processes a large amount of data in parallel and calculates the data accurately, the calculation result is only transmitted to the singlechip, so that the working efficiency of the singlechip is greatly saved.
The core algorithm is used as an IP core to be burnt into the FPGA, and the FPGA is used as a special chip to work, so that the performance requirement is met, and the difficulty of product design and debugging is simplified.
Because the invention uses the IP core designed by the FPGA as a special algorithm chip, the control system is still a 32-bit singlechip. Therefore, the algorithm of the chip is designed, and meanwhile, the invention needs to synchronously design the data interaction interface of the FPGA and the singlechip, so that the data interaction is rapid, and the interface is simplified so as to perfect the later-stage upgrading of the product.
The scheme solidifies the FPGA into a conventional chip, and the interface is described by verilog language. The core difficulty in the design process is the design and verification of the IP core of the FPGA. The invention adopts the FPGA and MATLAB mixed programming on the algorithm, encapsulates the algorithm into a special IP core, thereby facilitating verification and improving the development speed of the design.
The scheme solves the problem of customized design of complex operation of a large amount of data, so that after the IP core test passes the solidification, the precision of the analog circuit is changed into the precision of the customized IP core due to uncontrollable component errors, and the problems of high precision, fixation and controllability of the analog circuit, and simplification of the production of the analog circuit test flow and the influence of the aging of components along with time are solved.
Referring to fig. 8, the operation method of the IP core in this embodiment is:
The operation method of the IP core comprises the following steps:
1) After the first modulated wave with the power frequency of 45Hz is stable, sampling the data size of 100M of three-phase voltage and current data at a high-speed sampling rate of 50M, wherein the sampling period is 90;
After the second modulated wave with the power frequency of 55Hz is stable, sampling three-phase voltage and current data with the same size at the same high-speed sampling rate, wherein the sampling period is 110;
The sampled data is as follows:
2) Referring to fig. 3 to 5, the data obtained in step 1) are filtered to remove noise signals above 100Hz of three-phase voltage and current data synchronously by adopting a filtering algorithm, and the waveform diagram of the filtered signals is saved in a memory chip for further data processing;
The customized filtering algorithm in this embodiment is:
K is the sampling length, the filtering parameter is designed as a 10-order 100Hz low-pass filter, and hann window windowing processing is adopted, wherein: x (i) is a sampling sequence signal, i is a sequence label of the sampling sequence signal, h (n) is a convolution factor of a filtering parameter, and n is a sequence number after convolution. How to set parameters for operation under the condition of knowing the filtering formula is a conventional technology in the art, and is not described in detail.
After filtering, the phase delay and waveform size attenuation result are necessarily present, and because all signals adopt unified FIR filters and filter parameters, the data accuracy is greatly improved instead of influencing the result after all data are normalized.
The filtering parameter is designed as a 10-order 100Hz low-pass filter, and hann window windowing is adopted, so that precise data can be filtered out, and the subsequent calculation of voltage, current and phase angle is convenient. The disadvantage that the interference of the traditional algorithm is superposition is avoided.
3) Analyzing the time of all zero crossings based on the waveform obtained in the step 2), then carrying out data calculation on the time difference between the zero crossings of the unidirectional parity current and the zero crossings of the voltage to obtain phase angle information, respectively averaging the frequency phase angles of the first modulation wave and the second modulation wave, and finally averaging the average value data of the first modulation wave and the average value data of the second modulation wave to obtain 50Hz phase angle data;
Referring to fig. 6, since the 45Hz signal and the 55Hz signal collect 100M data volume signals, respectively, the 45Hz signal theoretically has 180 zero crossings and the 50Hz signal has 220 zero crossings. According to the phase angle data acquisition method, only the time of all zero crossing points is needed to be analyzed, then the time difference between the zero crossing points of unidirectional parity current and the zero crossing points of voltage is calculated to obtain the phase angle information, then the phase angles of 45Hz and 55Hz frequencies are respectively averaged, and finally the average value data of 45Hz and the average value data of 55Hz are averaged to obtain the phase angle data of 50 Hz.
Capturing a rising zero point:
The normalized data takes 100 points (i.e., n=100), and the optimal normal distribution is k=50, j=50, i.e., the continuous rising data less than 0 and the continuous rising data greater than 0 are both 50, i.e., the zero point of 100% rising is determined. For the accuracy of data, the invention can adopt the rising return zero point which can be judged as the data by judging E probability (100) >95 and is used for capturing the rising zero point.
Capturing a descending zero point:
The normalized data takes 100 points (i.e., n=100), and the optimal normal distribution is k=50, j=50, i.e., the continuous decrease of data greater than 0 and data less than 0 are both 50, i.e., the zero point of 100% decrease is determined. For the accuracy of data, the invention can adopt the judgment of E (100) >95 to judge the descending zero point of the data for capturing the descending zero point.
And then calculating the phase difference:
Wherein 50M is high speed Sampling rate of/>For modulating wave basic frequency, phi is a phase angle, N1 is a digital position code of a parity voltage zero crossing point, and N2 is a digital position code of a parity current zero crossing point;
Thus, the phase data with high precision can be accurately calculated, and the phase size is +/-180 degrees. Because the relation between the voltage and the current is +/-90 degrees, the calculated size range is +/-90 degrees, and the invention expands a certain calculation range. Finally, the phase angle of the modulation frequency of 50Hz can be obtained by taking the phase of the modulation frequency of 45Hz and the phase of the modulation frequency of 55Hz as the average value, and the precision of acquiring the phase angle by adopting a multiplier chip is greatly improved.
Wherein: active power on three phases of alternating current A, B, C under corresponding frequency; /(I) Reactive power on three phases of alternating current A, B, C under corresponding frequency;
4) Based on:
respectively calculating accurate effective values of the voltage and the current of the first modulation wave and the second modulation wave; wherein: y is the true effective value of the alternating current signal, and f (x) is the first modulated wave Data of all periods sampled or second modulated wave/>The data of all the periods sampled, T is the number of the corresponding periods, i.e. H1 or H2, the upper half is the integral of the whole over the absolute value of f (x), and the integral standard formulas are given by the ≡dx.
The conventional method for collecting the current and the accurate effective value of the voltage is to collect the alternating current signals of the voltage and the current into a true effective value chip, wherein the true effective value chip is equivalent to a capacitance integrator, and the true effective value of the alternating current signals is calculated through capacitance integration. The true effective value chip has life effect at the same time, and the measurement accuracy is affected when the chip ages, but the chip is difficult to perceive, so that test personnel cannot know that test data has problems.
By means of the powerful parallel computing capability of the FPGA, the real effective value of the alternating current signal can be calculated more accurately through a mass data parallel computing method. The formula y above is the magnitude of the true effective value of the alternating current signal, and f (x) is 45HzSampled data of 90 cycles, 55 Hz/>110 Cycles of data sampled. T is the number of cycles. The method can calculate the true effective value of the data more accurately, and the precision is permanent and constant after the data is solidified through the IP core. The problem of error influence caused by ageing of the computing chip does not exist.
The accurate value of all the line parameters which need data can be calculated according to a physical formula, for example, the next calculation of the resistance and the reactance is carried out:
The 45hz frequency is calculated first:
And then, calculating 55Hz data:
and then the data are averaged to obtain:
Carrying out actual operation, and comparing measurement results:
The improvement of the calculation accuracy of the reactance and the capacitance can be obviously seen through the comparison of the optimized data algorithm. Because the scheme adopts a mode of a digital circuit curing algorithm chip to replace a traditional analog circuit, the service life and the data reliability of the product are greatly prolonged, and the method is worthy of large-scale popularization.
The invention eliminates the errors caused by ageing of the components of the product and the different precision of the components by using a complex development scheme, and the cured chip design scheme can develop the product in batches and reduce the complexity of debugging the single product. The analog circuit is replaced with a comprehensive circuit chip. Although the development difficulty is high, after the development is successful, the circuit complexity of the product is reduced, the product precision and controllability are greatly improved, and the scheme can be popularized on other products at the same time.
Referring to fig. 9, the ip core algorithm does not occupy excessive resources after being optimized for multiple time constraints.
Phase angle calculation of voltage and current in line parameter measurement is very important because of the need for resistance, capacitance and inductance parameters related to calculation of active and reactive power. And the waveform is distorted to a certain extent due to harmonic components with different sizes of the debugging wave parts, so that parameter data of a measured phase angle is influenced, and measured data parameters are influenced.
According to the invention, a three-phase parity data acquisition method is adopted, parity data is synchronously acquired into a data cache, then harmonic components of signals are rapidly analyzed through an IP core customized by an FPGA, and synchronously filtered harmonic components are filtered, so that phase angle and voltage and current parameters with higher precision are reversely calculated, and the data calculation with higher precision is participated.
The invention is not limited to the above embodiments, and based on the technical solution disclosed in the invention, a person skilled in the art may make some substitutions and modifications to some technical features thereof without creative effort according to the technical content disclosed, and all the substitutions and modifications are within the protection scope of the invention.
Claims (9)
1. The high-precision data optimization method for the line parameters is characterized by comprising the following steps of:
1) Collecting a first modulated wave with the power frequency of Z1 and a second modulated wave with the power frequency of Z2, wherein Z1 is less than 50Hz, and Z1+Z2=100 Hz;
After the first modulated wave is stable, sampling three-phase voltage and current data with the size of Q at a high-speed sampling rate R which is 2 times larger than the fundamental wave frequency value of the first modulated wave, wherein the sampling period is H1;
After the second modulation wave is stable, sampling three-phase voltage and current data with the size of Q at the same high-speed sampling rate R, wherein the sampling period is H2;
The sampled data satisfies the following formula:
2) Synchronously filtering noise signals of more than 100Hz of three-phase voltage and current data by adopting a filtering algorithm, and storing a waveform diagram of the filtered signals into a memory chip for further data processing;
3) Analyzing the time of all zero crossings based on the waveform diagram obtained in the step 2), then carrying out data calculation on the time difference between the zero crossings of the unidirectional parity current and the zero crossings of the voltage to obtain phase angle information, respectively averaging the phase angles of the first modulation wave and the second modulation wave, and finally averaging the average value data of the first modulation wave and the average value data of the second modulation wave to obtain 50Hz phase angle data;
Capturing a rising zero point:
capturing a descending zero point:
And then calculating the phase difference:
Wherein R is high speed Sampling rate of/>For modulating wave basic frequency, phi is a phase angle, N1 is a digital position code of a parity voltage zero crossing point, and N2 is a digital position code of a parity current zero crossing point;
Wherein: p A、PB、PC active power on three phases of alternating current A, B, C under corresponding frequency; q A、QB、QC reactive power on three phases of ac A, B, C at the corresponding frequency;
4) Based on:
respectively calculating accurate effective values of the voltage and the current of the first modulation wave and the second modulation wave;
Wherein: y is the true effective value of the alternating current signal, and f (x) is the first modulated wave Data of all periods sampled or second modulated wave/>The data of all the periods sampled, T is the number of corresponding periods, the upper half is the integral of the whole over the absolute value of f (x), and the integral standard formulas are the integral.
2. The method for optimizing high-precision data of line parameters according to claim 1, wherein Z1 is greater than 40Hz and less than 50Hz, and z1+z2=100 Hz.
3. The high-precision data optimization method of line parameters according to claim 2, wherein after the first modulated wave with the power frequency of 45Hz is stabilized, the data size of 100M of three-phase voltage and current data is sampled at a high-speed sampling rate of 50M, and the sampling period is 90;
After the second modulated wave with the power frequency of 55Hz is stabilized, sampling three-phase voltage and current data with the same size at the same high-speed sampling rate, wherein the sampling period is 110;
The sampled data satisfies the following formula:
。
4. the method for optimizing high-precision data of line parameters according to claim 1, wherein in step 2), the filtering algorithm is:
k is the sampling length, the filtering parameter is designed as a 10-order 100Hz low-pass filter, and hann window windowing processing is adopted, wherein: x (i) is a sampling sequence signal, i is a sequence label of the sampling sequence signal, h (n) is a convolution factor of a filtering parameter, and n is a sequence number after convolution.
5. The method of claim 1, wherein in step 4), the method further comprises the step of back-deriving the resistance and reactance data of the line based on the accurate effective values of the voltage and the current.
6. The high-precision data optimization operation system for the line parameters comprises 6 paths of ADC chips and is characterized by further comprising an FPGA chip, a memory chip and a singlechip, wherein the 6 paths of ADC chips are electrically connected with the FPGA chip, the FPGA chip is respectively electrically connected with the memory chip and the singlechip, an IP core is burnt in the FPGA chip, and the IP core is used for operating the high-precision data optimization method for the line parameters according to any one of claims 1 to 5.
7. The high-precision data optimizing operation system of line parameters according to claim 6, wherein the 6-way ADC chip adopts a three-phase parity data acquisition method, and the FPGA chip processes three-phase voltage and current signals in a parallel processing mode.
8. The line parameter high-precision data optimization operation system according to claim 6, wherein the single chip microcomputer is provided with a Bluetooth transmission port, the single chip microcomputer is further electrically connected with a display device, and the single chip microcomputer can output SPWM signals.
9. The line parameter high precision data optimized operation system as claimed in claim 6, wherein said memory chip is a ddr3 memory chip.
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