CN117762494A

CN117762494A - Data processor, conditional instruction processing method, electronic device, and storage medium

Info

Publication number: CN117762494A
Application number: CN202410039242.5A
Authority: CN
Inventors: 朱志军; 吴鹏; 杜学亮; 肖滔; 马清川; 马波; 康凯; 欧阳剑
Original assignee: Kunlun Core Beijing Technology Co ltd
Current assignee: Kunlun Core Beijing Technology Co ltd
Priority date: 2024-01-10
Filing date: 2024-01-10
Publication date: 2024-03-26

Abstract

The present disclosure provides a data processor, relates to the technical field of artificial intelligence, and in particular relates to the technical field of chips. The processor includes: a status register; a processing unit configured to: providing execution data of the conditional instruction to the reservation station prior to acquiring the target state value of the state register, wherein the execution data includes a destination physical register of the conditional instruction; in response to determining that a prior associated instruction of the conditional instruction is executed, modifying an initial state value of the state register to obtain a target state value according to an execution result of the prior associated instruction; and providing an instruction completion signal to the reorder buffer module for removal of the conditional instruction from the reorder buffer module in response to determining that the target state value indicates that the conditional instruction is not executing. The disclosure also provides a conditional instruction processing method, electronic equipment and a storage medium.

Description

Data processor, conditional instruction processing method, electronic device, and storage medium

Technical Field

The present disclosure relates to the field of artificial intelligence, and in particular, to the field of chip technology. More specifically, the present disclosure provides a data processor, a processing method of conditional instructions, an electronic device, and a storage medium.

Background

With the development of artificial intelligence technology, in order to improve the execution efficiency of instructions in a processor, a register renaming technique may be used to solve the problem of dependency between registers in an instruction stream.

Disclosure of Invention

The present disclosure provides a data processor, a method, an apparatus and a storage medium for processing conditional instructions.

According to an aspect of the present disclosure, there is provided a data processor comprising: a status register; a processing unit configured to: providing execution data of the conditional instruction to the reservation station prior to acquiring the target state value of the state register, wherein the execution data includes a destination physical register of the conditional instruction; in response to determining that a prior associated instruction of the conditional instruction is executed, modifying an initial state value of the state register to obtain a target state value according to an execution result of the prior associated instruction; and providing an instruction completion signal to the reorder buffer module for removal of the conditional instruction from the reorder buffer module in response to determining that the target state value indicates that the conditional instruction is not executing.

According to an aspect of the present disclosure, there is provided an electronic device including a processor provided by the present disclosure.

According to another aspect of the present disclosure, there is provided a method of processing a conditional instruction, the method comprising: providing execution data of the conditional instruction to the reservation station prior to acquiring the target state value of the state register, wherein the execution data includes a destination physical register of the conditional instruction; in response to determining that a prior associated instruction of the conditional instruction is executed, modifying an initial state value of the state register to obtain a target state value according to an execution result of the prior associated instruction; and providing an instruction completion signal to the reorder buffer module for removal of the conditional instruction from the reorder buffer module in response to determining that the target state value indicates that the conditional instruction is not executing.

According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method provided in accordance with the present disclosure.

According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform a method provided according to the present disclosure.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements a method provided according to the present disclosure.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of a plurality of instructions according to one embodiment of the present disclosure;

FIG. 2 is a schematic block diagram of a data processor according to one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a processor executing conditional instructions according to one embodiment of the present disclosure;

FIG. 4 is a schematic block diagram of an electronic device according to one embodiment of the present disclosure;

FIG. 5 is a schematic flow chart diagram of a method of processing a conditional instruction according to one embodiment of the disclosure; and

fig. 6 is a block diagram of an electronic device to which a conditional instruction processing method may be applied, according to one embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

In order to improve the execution efficiency of instructions in a processor, a register renaming technique may be used to solve write-after-write and write-after-read dependencies between registers in an instruction stream, and write-after-read dependencies may also be marked. In addition, by increasing the number of physical registers, the register dependence among instructions caused by the limitation of the number of the instruction set architecture registers can be relieved, and the problem of low instruction parallelism is solved.

At the instruction set level, processor designers can customize conditional operation instructions to increase the instruction density of programs, reduce the number of instructions compiled by programs, and reduce the number of branch instructions in programs. For example, the value of the post-state register may be updated according to the execution result of the instruction. This value may determine whether the current instruction needs to be executed. Therefore, the number of the branch instructions and the comparison instructions compiled by the program can be reduced, and the instruction density can be improved. In addition, the additional processor overhead due to branch prediction errors is also reduced due to the reduced number of branch instructions.

FIG. 1 is a schematic diagram of a plurality of instructions according to one embodiment of the present disclosure.

As shown in fig. 1, instruction i0 involves a logical register x1, a logical register x2, and a logical register x3. The instruction code add.m for instruction i0 includes an add. Instruction i0 may indicate: the addition operation is performed using the value of the logical register x1 and the value of the logical register x2, and the addition operation result is written into the logical register x3. Instruction i1 relates to logical register x1, logical register x3, and logical register x5. The instruction code xor.n of the instruction i1 includes xor. Instruction i1 may indicate: an exclusive or operation is performed using the value of the logical register x1 and the value of the logical register x3, and the exclusive or operation result is written into the logical register x5. Instruction i2 relates to logical register x2, logical register x3, and logical register x6. The instruction code sub.n of instruction i2 comprises sub. Instruction i2 may indicate: the subtraction is performed using the value of the logical register x2 and the value of the logical register x3, and the subtraction result is written into the logical register x6. It is understood that the status registers are registers other than the logical registers x1, x2, x3, x5, and x6.

As shown in FIG. 1, instruction code add.m of instruction i0 includes.m, which indicates that a status register needs to be modified according to the execution result of instruction i 0. The instruction code xor.n of instruction i1 and the instruction code sub.n of instruction i2 respectively comprise n, indicating that it is necessary to determine whether instruction i1 and instruction i2 are executed according to the value of the status register. Instruction i1 and instruction i2 may each be conditional instructions. Instruction i0 may be the previous associated instruction of instructions i1 and i 2.

In some embodiments, it may be desirable to determine whether the value of the status register has been updated by instruction i0 before renaming instruction i1 and instruction i 2. If the value of the status register is not updated by instruction i0, then instruction i1 and instruction i2 may be executed after instruction i0 is executed. Thus, while waiting for instruction i0 execution to complete, many pipeline bubbles (bubbles) may appear. Furthermore, in processors that customize conditional instructions, the correlation between conditional instructions increases and the control of the instruction flow by the status register increases. Thus, out of Order (OoO) processors have difficulty continuously renaming conditional instructions, resulting in lower instruction parallelism.

In other embodiments, to reduce pipeline cavitation, the status registers may be renamed to extend the number of status registers with physical registers, and also to help solve the write-after-write, read-after-write problems of the status registers. However, using physical registers to extend the number of status registers, with major modifications to the pipeline, increases processor quality risks, and the newly added physical registers increase processor area and power consumption. In addition, taking the instruction i0, the instruction i1, and the instruction i2 as examples, it is difficult to solve the cavitation problem caused by the instruction i1 and the instruction i2 by expanding the number of the status registers. However, expanding the number of status registers may alleviate the cavitation problem caused by other conditional instructions.

In order to effectively reduce pipeline cavitation, the present disclosure provides a data processor, as will be described below.

Fig. 2 is a schematic block diagram of a data processor according to one embodiment of the present disclosure.

As shown in fig. 2, apparatus 200 may include a status register 210 and a processing unit 220.

The status register 210 may store a plurality of status values. For example, the plurality of status values may indicate whether the result of instruction i0 described above overflows, is negative, or the like.

The processing unit 220 may be configured to: the execution data of the conditional instruction is provided to the reservation station (Reservation Station, RS) before the target state value of the state register is obtained.

In the disclosed embodiments, the value of the status register may not be waited for to be updated by a prior associated instruction. For example, before the execution result of instruction i0 updates the status register, the above-described instructions i1 and i2 may be renamed to determine the respective execution data of instructions i1 and i 2.

In the disclosed embodiments, the execution data may include a destination physical register of the conditional instruction. For example, as described above, instruction i1 involves logical register x1, logical register x2, and logical register x3. The logical registers x1 and x2 may be source logical registers. The logical register x3 may be a destination logical register. After renaming instruction i1, the association between the logical registers and the corresponding physical registers may be stored into a register map (Register Mapping Table, regmap). The physical register number corresponding to the logical register x3 may be obtained from the register map table to obtain the destination physical register of the instruction i 1.

The processing unit 220 may be further configured to: in response to determining that a prior associated instruction of the conditional instruction is completed, modifying an initial state value of the state register to obtain a target state value based on a result of execution of the prior associated instruction.

In the embodiment of the present disclosure, the state value modified according to the execution result of the previous associated instruction may be the target state value. For example, the value in the status register is modified according to the execution result of instruction i 0. This value may be referred to as a target state value.

The processing unit 220 may be further configured to: in response to determining that the target state value indicates that the conditional instruction is not executing, an instruction completion signal is provided to the reorder buffer module for removal of the conditional instruction from the reorder buffer module.

In embodiments of the present disclosure, the instruction completion signal may cause the reorder buffer module to adjust the state of the corresponding instruction to completion (complete). In the reorder buffer module, entries for instructions whose state is complete may be released (retire) from the reorder buffer module. Thus, the instruction may be removed from the reorder buffer module. For example, in the event that a determination is made that the target state value indicates that instructions i1 and i2 are not executing, an instruction completion signal may be provided to the reorder buffer module. Thus, instruction i1 and instruction i2 may be removed from the reorder buffer module.

By the embodiment of the invention, the execution data is provided to the reservation station before the target state value is acquired, so that pipeline cavitation can be effectively reduced. The execution data comprises a target physical register, which is equivalent to multiplexing a pipeline path, so that the control path of the conditional instruction can be simplified, and no additional renaming operation is required to be executed. The method can effectively reduce pipeline cavitation caused by conditional instructions and can also effectively improve the parallelism of instruction stages based on less control logic, less processor area and increased power consumption.

It will be appreciated that the above provides execution data to the reservation station before the target state value of the state register is obtained. However, the present disclosure is not limited thereto, and other operations may be performed before the target state value of the state register is acquired, as will be described below.

In some embodiments, the reorder cache data for a conditional instruction is determined before a target state value for a state register is obtained. For example, the reorder buffer module may allocate reorder buffer entries for instruction i1 and instruction i2, respectively, before the target state value for the state register is obtained. The reorder buffer table entry corresponds to the reorder buffer index rob _idx. At least one of the reorder buffer index and the reorder buffer table entry may be used as reorder buffer data. According to the embodiment of the disclosure, the reorder buffer data is determined before the target state value of the state register is acquired, so that the execution result of the instruction can be submitted in the correct sequence, the precision of the processor can be improved, and the processor error is reduced.

It will be appreciated that the target state value may be obtained in the event that execution data is provided to the reservation station and the state register has been modified with a previously associated instruction. The execution data may remain in the reservation station or may be sent out from the reservation station when the target state value is acquired. The following will be described taking the example that the execution data is still located in the reservation station.

In some embodiments, the processing unit may be further configured to provide an instruction completion signal to the reorder buffer module by: in the case where the execution data is at the reservation station, the memory space in the reservation station corresponding to the conditional instruction is freed. The reorder buffer data is provided to a reorder buffer module. The instruction completion signal is provided to a reorder buffer module. For example, in the case where the execution data of instruction i1 is at the reservation station and instruction i1 is not executing, the memory space of instruction i1 in the reservation station may be freed. Taking the example where the reorder buffer data is a reorder buffer index, the reorder buffer index allocated for instruction i1 and the instruction completion signal may be sent to a reorder buffer module to remove instruction i1 from the reorder buffer module. With the embodiments of the present disclosure, instructions can be effectively shifted out when conditional instructions are at the reservation station and not executing, which helps to further reduce pipeline cavitation.

It will be appreciated that the present disclosure has been described above with the example of execution data still being located in a reservation station. The following will be described taking as an example that execution data has been issued from a reservation station.

In some embodiments, the processing unit may be further configured to provide an instruction completion signal to the reorder buffer module by: in the event that the execution data is not at the reservation station, an instruction completion signal is provided to the reorder buffer module. For example, in the case where the execution data of the instruction i1 is not in the reservation station, the memory space in the reservation station corresponding to the execution data of the instruction i1 has been released. An instruction completion signal may be sent to the reorder buffer module to remove instruction i1 from the reorder buffer module.

It will be appreciated that the above description of the present disclosure has been presented with the target state value indicating that the conditional instruction is not executing as an example. The present disclosure is not limited thereto and the target state value may also indicate that a conditional instruction is to be executed, as will be described below.

In some embodiments, the processing unit may be further configured to: and responding to the determination that the target state value indicates that the conditional instruction is to be executed, and obtaining an execution result of the conditional instruction. For example, in the case where it is determined that the target state value indicates that the instruction i1 and the instruction i2 are executed, the relevant operation of the instruction i1 and the relevant operation of the instruction i2 may be respectively executed by using the arithmetic logic unit (Arithmetic Logical Unit, ALU) to obtain the execution result of the instruction i1 and the execution result of the instruction i2, respectively.

In some embodiments, the processing unit may be further configured to: and submitting the execution result of the conditional instruction according to the sequence indicated by the reorder cache data. For example, the execution results of instruction i1 and the execution results of instruction i2 may be committed (commit) in order, based on the order indicated by the reorder buffer data and the queues within the reorder buffer module, to ensure that the execution results are committed in the correct order. By the embodiment of the disclosure, the conditional instruction can be accurately executed, and the execution result can be accurately submitted, so that the precision of the processor is further improved, and the error is reduced.

It will be appreciated that the processor of the present disclosure is described above in connection with fig. 2, and that the present disclosure will be further described below in connection with various modules of the processor.

FIG. 3 is a schematic diagram of a processor executing conditional instructions according to one embodiment of the present disclosure.

In some embodiments, the processor may include a status register. The status register may include a plurality of status values. For example, the plurality of state values may indicate whether the execution result of the associated instruction is negative, 0, overflowed, or the like. For another example, the instruction i1 and the instruction i2 may be conditional instructions, respectively. In the case where the execution result of the instruction i0 does not overflow, the instruction i1 and the instruction i2 may be executed. In the case where the execution result of the instruction i0 overflows, the instruction i1 and the instruction i2 are not executed.

In some embodiments, the processor may further include a finger fetch unit and a decode unit. The instruction fetch unit may fetch instructions. The decode unit may determine the source and destination logical registers of the instruction. For example, the instruction i1 may be a conditional instruction. The decode unit may determine a first source logical register c_inst.rs0, a second source logical register c_inst.rs1, and a destination logical register c_inst.rd of instruction i 1. The first source logical register c_inst.rs0 of instruction i1 may be the logical register x1 described above. The second source logical register c_inst.rs1 of instruction i1 may be the logical register x3 described above. The destination logical register c_inst.rd of instruction i1 may be the logical register x5 described above.

In some embodiments, the processing unit may include a renaming module. The renaming module may determine a physical register corresponding to the logical register and may add the physical register corresponding to the logical register to the register map. For example, a processor may include 32 physical registers. As shown in fig. 3, the register map rm30 includes column data phy reg. The column data may indicate a physical register corresponding to the logical register. From the first source logical register c_inst.rs0, the second source logical register c_inst.rs1 and the destination logical register c_inst.rd, the first source physical register c_inst.prs0, the second source physical register c_inst.prs1 and the destination physical register c_inst.prd may be determined using the register map rm 30.

In some embodiments, the destination physical register may correspond to a logical register of a plurality of instructions. For example, the destination physical register may also correspond to a logical register of a preceding instruction of instruction i 1.

In some embodiments, the processing unit may further include a reservation station and a computing module. As shown in fig. 3, the reservation station 321 may comprise a plurality of child reservation stations. The plurality of computing modules may include an arithmetic logic unit ALU 3220, an arithmetic logic unit ALU 3221, and a miscellaneous computing unit Other 3222. The plurality of child reservation stations may include an arithmetic logic unit child reservation station ALU RS 3210, an arithmetic logic unit child reservation station ALU RS 3211, and a miscellaneous instruction child reservation station MISC RS 3212.

In some embodiments, the processing unit may further include a reorder buffer module 323. The reorder buffer module 323 may allocate a reorder buffer entry for an instruction. The reorder buffer table entry corresponds to a reorder buffer index. The reorder buffer index may be referred to as reorder buffer data. The reorder buffer entry may include the completion status of the instruction. The completion status may include completed or incomplete. The reorder buffer module 323 may move out completed instructions in order of instructions.

It will be appreciated that the processing unit and various modules of the processing unit of the present disclosure have been described above and that the manner in which conditional instructions are executed by the processing unit will be described below.

In some embodiments, the processing unit may be configured to: the execution data of the conditional instruction is provided to the reservation station before the target state value of the state register is obtained. The execution data includes a destination physical register of the conditional instruction.

In an embodiment of the present disclosure, the processing unit may be further configured to: the destination physical register is released to shift out the initial value in the destination physical register before the execution data of the conditional instruction is provided to the reservation station. For example, after the source physical register and the destination physical register are determined using the register map rm30, the mapping relationship between the destination physical register and the logical register of the preceding instruction described above may be released to shift out the initial value corresponding to the destination physical register and the preceding instruction. It will be appreciated that this initial value may be saved in other memory locations prior to the execution result of instruction i1 being committed, to avoid processor calculation errors caused by instruction i1 not executing. According to the embodiment of the disclosure, the target physical register is released so that the conditional instruction can be executed, so that the conditional instruction can be quickly executed under the condition that the target state value indicates the conditional instruction to be executed, the execution efficiency of the instruction can be fully improved, and the stream line cavitation can be reduced.

In an embodiment of the present disclosure, the renaming module may be further configured to: before the target state value of the state register is acquired, a target physical register of the conditional instruction is added to a storage space corresponding to the conditional instruction in the reservation station. For example, the rename module may add the first source physical register c_inst.prs0, the second source physical register c_inst.prs1, and the destination physical register c_inst.prd as execution data to a memory space in reservation station rs30 corresponding to instruction i 1. As shown in FIG. 3, the memory space corresponding to instruction i1 may be an entry 32111 in the arithmetic logic unit sub-reservation station ALU RS 3211. It will be appreciated that via the dispatch module, the renaming module may add a destination physical register of the conditional instruction to a memory space in the reservation station corresponding to the conditional instruction.

In an embodiment of the present disclosure, the reorder buffer module may be configured to: before the target state value of the state register is acquired, the reorder buffer data of the conditional instruction is added to a storage space corresponding to the conditional instruction in the reservation station. For example, the reorder buffer module 323 may add the reorder buffer index rob _idx1 of instruction i1 to entry 32111 in the arithmetic logic unit sub-reservation station ALU RS 3211. The reorder buffer module may add reorder buffer data of the conditional instruction to a storage space in the reservation station corresponding to the conditional instruction via the dispatch module.

It will be appreciated that after the execution data is added to the reservation station, the previous associated instruction of instruction i1 may be executed to completion. The preceding associated instruction may be instruction i0 described above.

In some embodiments, the processing unit may be further configured to: in response to determining that a prior associated instruction of the conditional instruction is completed, modifying an initial state value of the state register to obtain a target state value based on a result of execution of the prior associated instruction. For example, the processing unit may modify the value of the status register based on the execution result of instruction i0. If the result of the execution of instruction i0 overflows, the value of the status register may be modified such that the resulting target status value indicates that instructions i1 and i2 are not executing.

It will be appreciated that the processing unit may obtain the target state value after execution of the pre-associated instruction is completed. Upon acquisition of the target state value, the execution data of instruction i1 may be at the reservation station or have been issued from the reservation station. The following will take as an example an entry 32111 where the execution data of instruction i1 is still located in the arithmetic logic unit sub-reservation station ALU RS 3211.

In some embodiments, the reservation station may be further configured to: in response to determining that the execution data is at the reservation station and the target state value is obtained, a determination is made as to whether to execute the conditional instruction based on the target state value. For example, in the case where execution data is located at the reservation station 321, the reservation station 321 may determine whether to execute the instruction i1 according to the target state value.

In embodiments of the present disclosure, the reservation station may be further configured to: in response to determining that the target state value indicates that the conditional instruction is not executing, an instruction completion signal is provided to the reorder buffer module. For example, where the target state value indicates that instruction i1 is not executing, reservation station 321 may set the valid flag value valid corresponding to entry 32111 in arithmetic logic unit sub-reservation station ALU RS 3211 to release the associated data to 0. Reservation station 321 may also provide instruction complete signal cond_complete and reorder buffer index rob _idx1 to the reorder buffer. Based on the reorder buffer index, the reorder buffer module may determine a reorder buffer entry corresponding to instruction i1. Thus, based on the instruction complete signal cond_complete, the reorder buffer module may set the state of instruction i1 to complete, and may then move out of instruction i1.

It will be appreciated that, as described above, the destination physical register is released before the execution data of instruction i1 is provided to the reservation station. To ensure proper execution of the associated instruction, the value of the destination physical register may be restored, as will be described below.

In some embodiments, the processing unit may be further configured to provide an instruction completion signal to the reorder buffer module by: the initial value is written into the destination physical register. For example, an initial value corresponding to a previous instruction may be rewritten to the destination register. By the embodiment of the disclosure, the history value of the target physical register can be rewritten into the physical register, so that the subsequent instruction of the conditional instruction can obtain the correct value, and the precision of the processor can be fully improved.

It will be appreciated that, in the case that the execution result of the instruction i0 overflows, the manner in which the processing unit executes the instruction i2 is the same as or similar to the manner in which the instruction i1 is executed, which will not be described in detail herein.

It will be appreciated that the present disclosure has been described above with the example of a target state value indicating that a conditional instruction is not executing. The present disclosure will be described below with an example of indicating conditional instruction execution with a target state value.

In an embodiment of the present disclosure, the reservation station may be configured to: in response to determining that the target state value indicates that the conditional instruction is to be executed, execution data is provided to the computing module. For example, where the target state value indicates that instruction i1 is executed, reservation station 321 may provide the execution data in entry 32111 in arithmetic logic unit sub-reservation station ALU RS 3211 to arithmetic logic unit ALU 3221. Based on the execution data, the arithmetic logic unit ALU 3221 may execute an operation corresponding to the instruction i1, resulting in an execution result of the instruction i 1. The arithmetic logic unit ALU 3221 may provide the execution result to the reorder buffer module RoB 323. The reorder buffer module RoB 323 can submit the execution result in the order indicated by the reorder buffer data corresponding to the instruction i 1.

It will be appreciated that the present disclosure has been described above with the example of execution data still at the reservation station when the target state value is obtained. However, the present disclosure is not limited thereto, and execution data may be issued from the reservation station upon acquisition of the target state value, and related operations are performed by the calculation module, as will be described below.

In some embodiments, the computing module may be configured to: in response to the execution data being acquired and the target state value being acquired, a determination is made as to whether to execute the conditional instruction based on the target state value. For example, if the arithmetic logic unit ALU 3221 described above acquires execution data and acquires a target state value via a bypass network, the arithmetic logic unit ALU 3221 may determine whether to execute the instruction i1.

In an embodiment of the present disclosure, the computing module may be configured to: in response to determining that the target state value indicates that the conditional instruction is not executing, an instruction completion signal is provided to the reorder buffer module. If the arithmetic logic unit ALU 3221 determines that instruction i1 is not executing, an instruction complete signal may be provided to the reorder buffer module RoB 323. Based on the instruction completion signal, the reorder buffer module may set the status of instruction i1 to completed, and may then move out of instruction i1.

In an embodiment of the present disclosure, the computing module may be further configured to: and responding to the determination that the target state value indicates that the conditional instruction is to be executed, and obtaining an execution result according to the execution data. And providing the execution result to a reordering buffer module. For example, if it is determined that the instruction i1 is executed, the arithmetic logic unit ALU 3221 may execute the related operation of the instruction i1 according to the execution data, resulting in an execution result. The arithmetic logic unit ALU 3221 may provide the execution result to the reorder buffer module. The reorder buffer module RoB 323 can submit the execution result in the order indicated by the reorder buffer data of the instruction i 1.

It will be appreciated that, in the case that the execution result of the instruction i0 does not overflow, the manner in which the processing unit executes the instruction i2 is the same as or similar to the manner in which the instruction i1 is executed, which will not be described in detail herein.

It will be appreciated that while the processor of the present disclosure has been described above, an electronic device comprising the processor will be described below.

Fig. 4 is a schematic block diagram of an electronic device according to one embodiment of the present disclosure.

As shown in fig. 4, device 4000 may include a processor 400.

In the disclosed embodiment, the processor 400 may be the processor 200 described above.

It will be appreciated that while an electronic device of the present disclosure has been described above, a method of processing conditional instructions of the present disclosure will be described below.

FIG. 5 is a schematic flow chart diagram of a method of processing a conditional instruction according to one embodiment of the disclosure.

As shown in fig. 5, the method 500 may include operations S510 to S530.

In operation S510, execution data of the conditional instruction is provided to the reservation station before a target state value of the state register is acquired.

In the disclosed embodiments, the execution data includes a destination physical register of the conditional instruction.

In operation S520, in response to determining that the previous associated instruction of the conditional instruction is executed, the initial state value of the state register is modified according to the execution result of the previous associated instruction to obtain the target state value.

In response to determining that the target state value indicates that the conditional instruction is not executing, an instruction completion signal is provided to the reorder buffer module for removal of the conditional instruction from the reorder buffer module in operation S530.

It is understood that the method 500 may be performed by the processing unit 220 described above.

In some embodiments, the method 500 may further comprise: before the target state value of the state register is acquired, the reorder buffer data of the conditional instruction is determined.

In some embodiments, the method 500 may further comprise: and responding to the determination that the target state value indicates that the conditional instruction is to be executed, and obtaining an execution result of the conditional instruction according to the execution data. And submitting the execution result of the conditional instruction according to the sequence indicated by the reorder cache data.

In some embodiments, providing the instruction completion signal to the reorder buffer module includes: in the case where the execution data is at the reservation station, the memory space in the reservation station corresponding to the conditional instruction is freed. The reorder buffer data is provided to a reorder buffer module. The instruction completion signal is provided to a reorder buffer module.

In some embodiments, the destination physical register corresponds to a logical register of a plurality of instructions. The method 500 may further include: the destination physical register is released to shift out the initial value in the destination physical register before the execution data of the conditional instruction is provided to the reservation station.

In some embodiments, providing the instruction completion signal to the reorder buffer module includes: the initial value is written into the destination physical register.

In the technical scheme of the disclosure, the related processes of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user accord with the regulations of related laws and regulations, and the public order colloquial is not violated.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

Fig. 6 illustrates a schematic block diagram of an example electronic device 600 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 6, the apparatus 600 includes a computing unit 601 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 602 or a computer program loaded from a storage unit 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 may also be stored. The computing unit 601, ROM 602, and RAM 603 are connected to each other by a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

Various components in the device 600 are connected to the I/O interface 605, including: an input unit 606 such as a keyboard, mouse, etc.; an output unit 607 such as various types of displays, speakers, and the like; a storage unit 608, such as a magnetic disk, optical disk, or the like; and a communication unit 609 such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The computing unit 601 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 601 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as the processing method of conditional instructions. For example, in some embodiments, the processing method of conditional instructions may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 600 via the ROM 602 and/or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of the processing method of conditional instructions described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to execute the processing method of conditional instructions in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) display or an LCD (liquid crystal display)) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A data processor, comprising:

a status register;

a processing unit configured to:

providing execution data of a conditional instruction to a reservation station prior to acquiring a target state value of the state register, wherein the execution data includes a destination physical register of the conditional instruction;

in response to determining that a previous associated instruction of the conditional instruction is executed, modifying an initial state value of the state register according to an execution result of the previous associated instruction to obtain the target state value; and

in response to determining that the target state value indicates that the conditional instruction is not executing, an instruction completion signal is provided to a reorder buffer module for removal of the conditional instruction from the reorder buffer module.

2. The processor of claim 1, wherein the processing unit is further configured to:

And determining the reorder cache data of the conditional instruction before the target state value of the state register is acquired.

3. The processor of claim 2, wherein the processing unit is further configured to:

responding to the fact that the target state value indicates that the conditional instruction is to be executed, and obtaining an execution result of the conditional instruction according to the execution data; and

and submitting the execution result of the conditional instruction according to the sequence indicated by the reorder buffer data.

4. The processor of claim 2, wherein the processing unit is further configured to provide an instruction completion signal to the reorder buffer module by:

releasing a storage space corresponding to the conditional instruction in the reservation station under the condition that the execution data is in the reservation station;

providing the reorder buffer data to the reorder buffer module; and

and providing the instruction completion signal to the reorder buffer module.

5. The processor of claim 1, wherein the destination physical register corresponds to a logical register of a plurality of instructions, the processing unit further configured to:

the destination physical register is released to shift out an initial value in the destination physical register before the execution data of the conditional instruction is provided to a reservation station.

6. The processor of claim 4, wherein the processing unit is further configured to provide an instruction completion signal to the reorder buffer module by:

and writing the initial value into the destination physical register.

7. The processor of claim 1, wherein the processing unit comprises a renaming module configured to:

the destination physical register of the conditional instruction is added to a memory space in the reservation station corresponding to the conditional instruction before the target state value of the state register is obtained.

8. The processor of claim 2, wherein the processing unit comprises the reorder buffer module configured to:

before the target state value of the state register is acquired, the reorder buffer data of the conditional instruction is added to a memory space in the reservation station corresponding to the conditional instruction.

9. The processor of claim 1, wherein the processing unit comprises a reservation station configured to:

responsive to determining that the execution data is located at the reservation station and the target state value is obtained, determining whether to execute the conditional instruction according to the target state value;

The instruction completion signal is provided to the reorder buffer module in response to determining that the target state value indicates that the conditional instruction is not executing.

10. The processor of claim 1, wherein the processing unit comprises a computing module configured to:

determining whether to execute the conditional instruction according to the target state value in response to acquiring the execution data and acquiring the target state value;

11. An electronic device comprising a processor as claimed in any one of claims 1 to 10.

12. A method of processing conditional instructions, comprising:

13. The method of claim 12, further comprising:

14. The method of claim 13, further comprising:

15. The method of claim 13, wherein the providing an instruction completion signal to a reorder buffer module comprises:

providing the reorder buffer data to the reorder buffer module; and

and providing the instruction completion signal to the reorder buffer module.

16. The method of claim 12, wherein the destination physical register corresponds to a logical register of a plurality of instructions,

the method further comprises the steps of:

17. The method of claim 16, wherein the providing an instruction completion signal to a reorder buffer module comprises:

and writing the initial value into the destination physical register.

18. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 12 to 17.

19. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 12 to 17.

20. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 12 to 17.