CN117749176A - Closed loop DAC glitch mitigation - Google Patents

Abstract

The present disclosure relates to closed loop DAC spur mitigation. A feedback control method of an amplifier system, comprising: driving a plurality of amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set a system output of the amplifier system, operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state target output; detecting a high-glitch transition of the first set of DAC codes greater than a specified threshold transition; and changing to operate the at least one DAC circuit using a second set of DAC codes to set the system output to a substantially same steady-state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the at least one DAC circuit.

Description

Closed loop DAC glitch mitigation

Request priority

The present application claims priority from U.S. provisional application serial No. 63/376467 filed at 2022, 9, 21, which is incorporated herein by reference in its entirety.

Technical Field

This document relates generally, but not exclusively, to circuit power supply systems providing regulated output and, more particularly, to amplifier systems that use digital-to-analog converters to provide regulated output over a large dynamic range.

Background

The amplifier system may be used as a circuit power supply to provide a Direct Current (DC) output. These systems are useful, for example, in Automatic Test Equipment (ATE). For circuit power supplies in a test environment, it may be desirable to have a large dynamic range. One way to increase the dynamic range of ATE is to use a digital-to-analog converter (DAC) to switch the ATE between multiple modes of operation. However, the use of a DAC in a closed loop regulated power supply may result in glitches, which is undesirable.

Drawings

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, the various embodiments discussed in the present document.

Fig. 1 is a diagram of an example of an electronic circuit including an amplifier system.

Fig. 2 is a graphical representation of an example of a transfer function for the circuit of fig. 1.

Fig. 3 is a graphical representation of another example of a transfer function for the circuit of fig. 1.

Fig. 4 is a diagram of another example of an electronic circuit including an amplifier system.

Fig. 5 is a graphical representation of an example of a transfer function for the circuit of fig. 4.

Fig. 6 is a diagram of an example of an electronic circuit including an amplifier system with multiple digital-to-analog converters (DACs).

Fig. 7 is a diagram of another example of an electronic circuit including an amplifier system having multiple DACs.

Fig. 8 shows a graph of an example of DAC code transitions.

Fig. 9 shows a graph of output ripple that may be caused by the DAC code transitions of fig. 8.

Fig. 10 is an example of a spur waveform having a peak amplitude of 10 millivolts.

Fig. 11 is a graph of output voltage spur amplitude of a segmented DAC versus an example of DAC code variation.

Fig. 12 is an expanded version of the closed loop amplifier system of fig. 10 with multiple DACs.

Fig. 13 is a switchless version of the multi-DAC system of fig. 12.

Fig. 14 is a closed loop circuit in which one or more auxiliary DACs are used to generate the reference level for the main DAC.

Fig. 15 is a circuit diagram of another example of an amplifier system.

Fig. 16 shows the amplifier system of fig. 15 operating in a high voltage low resolution mode.

Fig. 17 shows the amplifier system of fig. 15 operating in a low voltage high resolution mode.

Fig. 18 is a circuit diagram of another example of an amplifier system.

Fig. 19 shows the amplifier system of fig. 18 operating in a high voltage low resolution mode.

Fig. 20 shows the amplifier system of fig. 18 operating in a low voltage high resolution mode.

Fig. 21 is a transmission graph of the amplifier system of fig. 16 and 19 operating in a high voltage mode.

Fig. 22 and 23 are graphs showing the circuits of fig. 15 and 16 operating in DAC code areas with relatively low glitches.

FIG. 24 is a graph of an example of peak code transitions versus spur amplitude of transitions in steady state.

Fig. 25 is a diagram of another example of an electronic circuit including an amplifier system having a plurality of DACs.

Fig. 26 is a graphical representation of an example of transfer functions for the circuits of fig. 17, 20 and 25 operating in a low voltage mode.

Fig. 27A and 27B illustrate a flow chart of an example of a method of operating an amplifier system having one or more DACs.

Fig. 28A and 28B show a flow chart of an example of a foreground calibration method for an amplifier system having one or more DACs.

Fig. 29 is a flowchart of an example of a feedback control method of an amplifier system.

Detailed Description

Fig. 1 is a diagram of an example of an electronic circuit with an amplifier system having a switch selectable transfer function gain to apply to an input signal (V _IN ) To provide a lower resolution but High Voltage (HV) range and a higher resolution but Low Voltage (LV) range. The amplifier system comprises a gain amplifier providing a higher signal gain (G _HV ) Is provided to supply a lower signal gain (G _LV ) Is provided. The HV range circuit path or LV range circuit path is selected using a switching mechanism (SW) that enables the desired circuit path.

From input (V) _IN ) To output (V) _out ) G of the signal gains specified as the low resolution HV range circuit path and the high resolution LV range circuit path, respectively _HV And G _LV Wherein G is _HV ＞G _LV . Based on the state of the gain selector switch and assuming a forward gain G _F Essentially uniform, the transfer function of the input to the output is determined by one of the following equations:

V _OUT(HVRangs) ＝V _IN δ _HV ，

V _OUT(LVRange) ＝V _IN δ _LV .

input V _IN Normalization may be performed to: v is more than or equal to 0V _IN ≤1V。

FIG. 2 is V as HV and LV ranges _IN Output voltage V of a function of (2) _OUT Is shown in the figures. HV range map has slope G _HV And the LV range diagram has a slope G _LV . When operating at a common output voltage across the HV and LV ranges, it may be desirable to set up in both rangesWithout causing voltage disturbances (e.g., signal glitches) or aberrations at the output. This glitch mitigation is only common to the operating voltage V for spans of HV and LV ranges _OUT Is possible.

However, even for those output voltages common only to the HV and LV ranges, the voltage is varied for a constant input voltage (V _A ) When the switch changes between circuit paths, there will be aberrations on the output. This is true for all operating points except the one where the two graphs intersect (for the example of FIG. 2, at V _IN At=0v). This is because for all points not at the intersection, the output will be the corresponding input V according to the different transfer functions defined above _A Different voltages are taken.

FIG. 3 shows V as HV and LV ranges _IN V of the function of (2) _OUT Is a graph of (2). The graph shows the operating point V _IN ＝V _A Wherein the two output graphs do not intersect (V _A > 0V). As shown in the graph of fig. 3, when the position of the switch in fig. 1 changes between the HV range circuit path and the LV range circuit path, for input V _A The aberration will be the difference V _A [G _HV -G _LV ]。

Fig. 4 is a circuit schematic of an example of an amplifier system for switching between HV and LV ranges. G _HV The amplifier has been removed and the switch SW is located _G L _V And G _X An input side of the amplifier.

The transfer function across the LV range is now:

V _OUT ＝V _IN G _LV +V _X G _X ，

wherein gain G _X May be arbitrarily selected.

The Feedback Amplifier (FA) automatically outputs an input voltage V _IN Is adjusted to an appropriate voltage so that the output (V _OUT ) Toward the desired target signal V _{Target object} And (5) moving. When output (V) _OUT ) Maintain at or near (e.g., within error margin) the desired target signal V _{Target object} When the amplifier system is in a stable stateStatus of the device. Switch SW allows the amplifier system to be switched off without G _HV Implementing gain G in the case of an amplifier _HV . In the case of a switch in the upper setting (as shown in fig. 4), the slave V _IN To V _OUT The gain is G _LV +G _X ＝G _HV And by changing the switch to a lower setting the total gain is G _LV But has a cross-section of V _X And G _X The static offset is determined. Even though the LV range transfer function shown in the LV range diagram is modified by changing V _X The feedback mechanism will also keep the output at this target, slowly transitioning from one common mode range to another common mode span. Logic circuitry 402 may include one or more of a processor, a state machine, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or other logic circuitry to vary V _IN And V _X Is a value of (2).

Fig. 5 is a graph showing HV range and LV range of operation of the circuit of fig. 4, where the LV range is converted back from an intersecting condition to a preferred common mode span. In the example shown in FIG. 5, V _X Voltage from V _A The tilt was reduced to 0V. The feedback mechanism is in this way (from V _A To V _B ) Automatically and dynamically adjusting V _IN To maintain V at the output end _{Target object} Even when V is adjusted _X When (e.g., using a digital-to-analog converter (DAC) or other logic circuitry) to move the LV map without disturbing the output. As long as V _X And V before the switch setting is changed _IN Matching, the bias in the output can be eliminated.

FIG. 6 is a circuit schematic of another example of an amplifier system in which the input voltage V _IN 、V _X By digital-to-analogue converters (DAC) _IN And DAC _X ) And (5) creating. In addition, the Feedback Amplifier (FA) is replaced by an analog-to-digital converter (ADC) 606, the analog-to-digital converter 606 being combined with a control circuit 602 that provides appropriate control of the DAC and ADC 606. The control circuit 602 may be implemented using a processor (e.g., a microprocessor), a state machine, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or other logic circuitry. The amplifier system may be included in a system-on-a-chip (SoC) IC, a system-in-package (SiP), or by multiple componentsIs prepared.

G _X And G _LV Auxiliary signal gain G of amplifier circuit _X And LV signal gain G _LV May be adjustable. In the case where the switch SW is in the HV low resolution mode (as shown in FIG. 6), the switch SW is turned off from V _IN To V _OUT The gain is G _LV +G _X ＝G _HV And by changing the switch to LV high resolution mode, the total gain is G _LV But with V as in the example of FIG. 4 _X And G _X The static offset is determined. Forward gain G _F Reverse gain G, which may be added to the output in the forward path or in the feedback path _R . The second ADC 608 may be selectively used to use the sense impedance R _S To monitor the output current. Sense impedance R _S An impedance circuit element, such as a resistor or active device impedance, may be included. The sense impedance may include a unit resistor or unit impedance, which may be composed of a combination of different types and magnitudes of impedances to achieve a particular characteristic (e.g., a balanced temperature coefficient). Such impedance may be calibrated, trimmed or tuned. Gain G for monitoring output current _M May also be adjustable.

Fig. 7 is a circuit schematic of another example of an amplifier system with the range control Switch (SW) removed. The action of the switch SW is replaced by appropriate control of the DAC by the control circuit 702. For example, when operation is required in the HV low resolution mode, the control circuit 702 drives the DACs simultaneously so that they are directed to G _IN Amplifier and G _X The inputs of the amplifiers provide equal voltages. Thus, the composite gain is G _LV +G _X ＝G _HV . When operation is required in LV high resolution mode, control circuit 702 will DAC _X The path is frozen at V _X And continue through the DAC _IN Any subsequent control of the path to produce a gain G _LV . Because when passing through DAC _IN When the exclusive control of the path is started, G _LV And G _X The inputs to the amplifiers are equal so that any discontinuities or glitches are alleviated during the range switching operation. Reverse range switching (switching back from LV mode)HV mode) is achieved by making the DAC _X To DAC _IN Implemented by tilting, while letting the digital feedback continue as DAC _IN Providing a servo such that V _{Target object} Held at the output. When DAC _IN And DAC _X When the content of (a) is re-matched, any subsequent feedback control from this point forward is achieved by driving the DACs again simultaneously, thereby maintaining V _X ＝V _IN Conditions. This effectively returns the system to the HV range while mitigating any discontinuities, glitches or aberrations at the output.

In the examples of fig. 6 and 7, the feedback path (G _R ) May be set to scale the output voltage so that the voltage swing at the input of ADC 1006 is within the limits of the full scale range of a given ADC. In addition, gain (or attenuation) G _R The ADC input range for each of the HV and LV modes may be optimized by switching between two or more levels, respectively. In practice, in LV mode, the loop-back signal from DAC can be removed in the return path _X The offset is introduced to further optimize the input range of the ADC 1006. In addition, has a gain G _R An input of the amplifier of (2) may be connected to a gain G _F Or in combination with the output of the amplifier of (c).

The closed loop architecture in fig. 6 and 7 (where the input voltage is generated using a DAC (e.g., V _IN 、V _X Etc.) reduces glitches in the output caused by variations in the voltage range between HV and LV modes. However, during DAC code conversion, when the loop is operating at V _OUT ＝V _{Target object} When the vicinity remains stable, a glitch in the output of the DAC may occur. For example, the control circuit 702 may change the DAC input code by one or two LSBs to adjust the analog output of the DAC to maintain a steady state. Altering the digital input may cause the analog output to glitch. If the magnitude of the glitch is sufficiently high, the control circuit loop compensation may become cyclic, with the compensation of the glitch returning the DAC code to a state where the glitch is again generated and the compensation is repeated. This may be at V _OUT Causing undesirable fluctuations. Output ripple or continuous oscillation in steady state is particularly of concern in power supply applications.

Fig. 8 shows a graph of an example of DAC code transitions for a control loop that operates to maintain a steady state around a region of DAC code with a relatively large transition (in this example +/-10 LSB). Fig. 9 shows a graph of ripple that may be generated on the output. The control loop is stable around 20.15V, and DAC code transitions cause glitches in the output, resulting in 50mV ripple in the output.

The spur energy of the spur produced by the DAC may be defined as the worst case net integrated area of the spur voltage waveform over time minus the end point adjustment step of the DAC. Fig. 10 is an example of a spur waveform having a peak amplitude of 10 millivolts (10 mV). The glitch energy of a DAC depends on the circuit architecture, micro-architecture, design, and implementation layout. One class of DAC known as nyquist DAC (including binary weighted, thermometer coded, segmented DAC, etc.) requires synchronous switching of multiple elements and is therefore prone to undesirable glitches on the analog output. For example, a binary weighted DAC utilizes a capacitor or resistor array that switches between two reference levels. Clock skew between the corresponding logic circuits of the different array elements results in imperfect switching and causes glitches during transitions. Care should be taken in circuit and layout design to reduce such defects. Binary weighted DACs may exhibit higher spur energies than other DAC architectures (e.g., a binary scaling architecture). The glitches are typically more severe where all bits are at the Most Significant Bit (MSB) transition of the switch. The glitches generated during the main carry transition may result in amplitudes exceeding a few Least Significant Bits (LSBs), even though the glitches generated during any other DAC code transition are benign.

The segmented DAC is implemented as a combination of multiple DAC architectures to achieve better linearity characteristics. Segmented DACs typically include binary weighted (LSB) and binary weighted (MSB) segments, and also require synchronous switching of multiple branches, and are therefore also prone to glitches, especially during MSB segment transitions. In a segmented DAC, the high energy spur is typically repeated periodically within the DAC code, depending on the number of MSB segments present.

Fig. 11 is a graph of output voltage spur amplitude versus DAC code variation for an 18-bit segmented DAC. The figure shows the 64 high energy glitch peaks present in the DAC code space, which correspond to MSB segment code transitions. Further, higher glitch peaks may be observed at other DAC code transitions in other portions of the DAC code range, such as during a mesoscale code transition in the LSB sub-DAC of the segmented DAC. Such glitches depend on DAC circuit structure and microstructure details.

Fig. 12 is an expanded version of the closed loop amplifier system of fig. 6 with multiple DACs or multiple DAC channels. The system of fig. 12 shows an ADC 606, which ADC 606 may optionally be used to monitor the output voltage and output current using any of the circuit paths a-D, depending on the state of the Multiplexer (MUX) 1210. In some examples, the system includes multiple ADCs, and the MUX 1210 is positioned at the output of the ADCs. The MUX 1210 selects which ADC output is fed back to the control circuit 1202. In some examples, the current and voltage information may be processed simultaneously, or the current and voltage from all four circuit paths A-D may be processed simultaneously. Some circuit paths may be included in the control circuit loop and some circuit paths may be monitored for other purposes such as glitch detection. The DAC may be combined with a switch to form a multi-DAC system with DACs connected in parallel, in series, or a mixture of parallel and series.

Fig. 13 is a switchless version of the multi-DAC system of fig. 12. In these multi-DAC multi-amplifier systems, the voltage (or current) range of each DAC channel path is based on the range of the DAC in each channel and the gain of the subsequent amplification stage. In fig. 12 and 13, the high reference level and the low reference level (V _REFPi 、V _REFNi ) The range of the DAC is determined. These reference levels are voltages that may be fixed or programmable (e.g., using additional DACs). A gain or attenuation network may also be used to provide the reference voltage.

Fig. 14 is the closed loop circuit of fig. 12 wherein one or more auxiliary DACs are used to generate the reference level for the main DAC. In the case of a current-mode DAC, the feedback ADC may be a differential ADC 608 that monitors the sense impedance R _S To measure the current.

In the multiple DAC systems of fig. 12-14, the gain (G can be varied _i ) Or reference level (V) _REFPi ) Has a completely or partially overlapping transfer curve. Thus, the mapping from DAC codes to output voltages (or output currents) can be deliberately made many-to-one. In other words, there will be a plurality of different combinations of DAC codes that produce exactly the same output voltage (or current) in steady state. Thus, for each target output level (voltage or current), the control circuit may determine a combination of DAC codes that are sufficiently far from the high-glitch code transitions. The DAC code may be determined iteratively or algorithmically based on a closed form solution. Depending on the range and resolution requirements, the control circuit 1402 may continuously update one or more DACs (e.g., the master DAC) simultaneously while keeping the other DAC codes fixed (e.g., the auxiliary DACs).

If the spur energy characteristics of the DACs (e.g., master DACs) for all the different code transitions are known a priori from previous measurements, the DAC codes may be stored in memory along with their spur characteristics. Because the control circuit knows the current steady state of the amplifier system, the control circuit can avoid loading DAC codes with high glitch code transitions near steady state. Some examples of the spur feature data include spur amplitude (e.g., peak-to-peak amplitude), positive spur amplitude, negative spur amplitude, total or net spur energy, positive spur energy, negative spur energy. A combination of these metrics may be used to optimize the response of the system. The spur feature data may also be converted or compressed to reduce memory requirements and reduce data processing time or power when loading the appropriate DAC code.

This many-to-one DAC code approach may also be used to avoid glitches in "black box" DACs where high glitch code transitions may not be known or feature glitch data may not be available. For example, the amplitude and sign of the DAC-code correction applied by the control circuit may be monitored as the control loop of the amplifier system attempts to stabilize the output at or near a steady state target. When the control loop is at V _OUT ≈V _{Target object} When the vicinity reaches a stable state, the control circuit can be small under normal conditionsIs updated to the DAC by an increment or decrement (e.g., one or two LSBs) _IN Code to compensate for gradual changes due to noise, drift, etc., for example. If loading a new set of DAC codes does not result in a reduction in the spur energy at the DAC analog output, another set of DAC codes may be loaded (e.g., from memory) and the spur energy at the DAC analog output may be rechecked.

The monitoring may be performed in the digital domain (or software domain) and may be performed using control circuitry as part of the code adjustment algorithm, or may be performed using separate monitoring circuitry included in an ASIC, FPGA, microcontroller, or processor (e.g., microprocessor). When it is detected that the update exceeds a predetermined threshold (e.g., a threshold number N of LSBs _{Threshold value} ) A high glitch flag signal may be generated in the digital domain upon code update of (a). For example, in fig. 8, a high-glitch flag signal (N _{Threshold value} ＝10LSB)。

Other methods may be used to detect the high-spur transition condition. In some examples, the analog output or system output of the DAC may be monitored to detect glitches. A high spur condition may be detected by a spur exceeding a specified spur peak threshold (in volts or amperes). In other examples, a high spur condition may be detected by a spur exceeding a specified Mao Cineng amount (e.g., volt-seconds or amp-seconds). The high glitch flag signal may be generated when the control circuit detects a high glitch transition that exceeds a specified threshold transition. The high glitch threshold transition may be specified as a number of LSBs or in volts or amperes. In some examples, crowd-based analysis may be used. A combination of DAC codes and target values may be tracked. Worst case combinations may be tracked (e.g., by machine learning) to identify which DAC code versions may result in a high-glitch transition condition for a given target value. The high-spur threshold transitions may be adaptive based on the design of the system or a machine learning algorithm of the system.

The size of the DAC code set (sub-population to be relieved) for which small glitch mitigation is available is limited by redundancy or contingency built into the design so that codes can be avoided. Thus, while analysis may determine the code that needs to be alleviated, typically the worst case code, the DAC design needs to ensure that there are enough emergency measures to meet the expected worst case requirements. In some applications, there may be specific codes or code regions of transfer functions that are more important in the end use situation, so that glitch mitigation may be prioritized from these regions as part of the analysis described above.

When the high-glitch flag is raised, one or more codes for the DAC may be changed to a different one or more codes, with the steady-state DAC code being far enough away from the high-glitch transition so that no high-glitch occurs in steady-state. This predetermined threshold value N, which causes code updating, can be changed _{Threshold value} . In some examples, when the high-glitch flag is raised, an offset voltage is introduced in the loop such that the control circuitry allows one or more primary DACs in the loop to settle at one or more DAC codes far enough away from the high-glitch transition. The offset may be introduced at any point in the loop using analog means (e.g., opamp-based adder circuitry) or may be introduced directly into the DAC code in the digital domain. In addition, the reference level of one or more of the main DACs may be adjusted to create an offset effect or to change the gain.

The spur feature data may be stored in memory and may be used to calculate the offset required for a given spur DAC code transition according to a predefined function, optimization, approximation, or machine learning algorithm. The spur characterization technique may be implemented as a foreground calibration when the system is idle or as a background calibration when the system is running. Foreground calibration may be performed during system manufacturing. Foreground calibration may also be done by the user (e.g., as part of a system reset or calibration process). The amplifier system may adaptively adjust the offset when a new high-glitch code transition is encountered during operation. The glitch characterization technique may also be used to respond to load changes in the amplifier system that result in a new steady state approaching a high glitch transition.

Fig. 15 is a circuit diagram of another example of an amplifier system. To simplify the drawing, this example shows an ADC606. A main DAC (DAC) _IN ) And an auxiliary DAC ((DAC) _X ). The example of FIG. 15 shifts the voltage by V _{Offset of} A control loop of a dual DAC architecture with a range control switch SW of the amplifier system of fig. 6 is introduced. The ADC 606 may monitor the output voltage or the output current, or may include two ADCs to monitor the output voltage and the output current. In the example of FIG. 15, a voltage offset is added to G _LV And G _X The summing node at the output of the amplifier, but the voltage offset may be introduced at any other circuit node within the control loop of the amplifier system. The switch SW changes the operation of the system between a high voltage mode and a low voltage mode.

Fig. 16 shows the amplifier system of fig. 15 operating in HV low resolution mode. During HV mode, DAC _X Becomes redundant and the amplifier system effectively becomes a single DAC system as shown in fig. 16. The voltage offset may be introduced at any point in the loop or may be introduced digitally into the DAC by control circuit 1502 _IN Is a code of (a). Fig. 17 shows the amplifier system of fig. 15 operating in LV high resolution mode. During LV mode, switch SW is in LV mode position to switch DAC _X To G _X Input of the amplifier, thus DAC _X Can be used to set the minimum and maximum ranges of the LV range.

Fig. 18 is a circuit schematic of another example of an amplifier system. In the example of fig. 18, at the DAC _X Is added with another switch SW at the output _A To offset the voltage by V _{Offset of} Introduction of G _LV And G _X A summing node at the output of the amplifier. Optionally with amplifier providing gain G _Y May also be included in the switch SW _A This is then dependent on the amount of offset to be applied relative to the DAC _X The size of the full scale range.

Fig. 19 shows the amplifier system of fig. 18 in HV mode. In HV mode, switch SW will be V _IN Applied to G _LV And G _X The amplifier and control circuit 1802 closes switch SW _A To V (V) _X Or G _Y V _X Is applied to the summing node.The control circuit 1802 may load DAC codes into the DAC in HV mode _X To generate a value of the offset provided to the summing node. Fig. 20 shows the amplifier system of fig. 18 in LV mode. In LV mode, switch SW is turned to G _X Amplifier application V _X Switch SW _A Disconnect, DAC _X For setting the minimum and maximum ranges of the LV range.

FIG. 21 is a V of the amplifier system of FIG. 15 operating in a high voltage low resolution (HV) mode _OUT For V _IN Graph of transmission curve. The transfer curve shows that the added offset (+DeltaV) has a move up and down V when the switch SW is in HV mode _OUT And V is equal to _IN Effect of the transfer curve. The vertical dashed line corresponds to an exemplary DAC that causes high glitches at the DAC output _IN Code transition boundaries. In the example of fig. 21, the control loop of the amplifier system of fig. 15 attempts to converge to V _OUT ≈V _{Target object} This results in an input V _IN ≈V _A At the high-glitch code transition boundary. To avoid such high-glitch DAC code boundaries, the system is expected to operate within an offset (high or low) HV range, which also covers V _OUT ≈V _{Target object} But V _IN The value is not close to the DAC high-glitch boundary.

For example, if application V _{Offset of} The transfer function will move to the upper V _{Offset of} Row = +Δv. The control loop will V _IN the value of t is reduced toTo hold V _OUT ≈V _{Target object} . As shown in fig. 21, this offset causes the control loop to shift to V _IN Corresponding to the lower value of the corresponding burr-free DAC code area, and the loop will converge to a main DAC (DAC) far from the high burr transition in the code space _IN ) And (5) code. Fig. 22 and 23 show the result of shifting to the new DAC code area. FIG. 22 shows DAC code conversion less than N of FIG. 8 _{Threshold value} And fig. 23 shows that the output ripple is reduced from fig. 9. The output voltage at steady state with offset will have significantly reduced glitches and ripple compared to steady state without offset.

Fig. 24 is a graph of an example of peak code transitions (in LSBs) versus spur amplitude for a code transition in steady state. The graph shows that the relationship between signed glitch amplitude and code transition is substantially linear. The figure also shows that the required DAC code update is inversely proportional to the signed glitch amplitude. At the system level, when the high-glitch flag is raised, this glitch energy characteristic information about the glitch sign and amplitude may be recorded in memory (e.g., using a control circuit or a separate monitoring circuit) and may be used to determine the appropriate offset to achieve a given code transition.

The peak amplitude of the glitch is relevant in closed loop applications, since the glitch can be directly manifested as an output (V _OUT ) A burr waveform or ripple at the location. Furthermore, if the ADC samples the glitch at the output, it may also cause instability in the control loop and cause additional unwanted ringing or ringing response at the output.

As previously described, the spur energy may be defined as the net integrated area of the spur waveform. In some applications, the spur energy may be more critical than the spur peak amplitude in terms of the response of the control circuit, depending on the aperture window of the feedback ADC. In other words, if the ADC has a sufficiently wide aperture window due to averaging effects, the control circuit may not significantly respond to a glitch waveform (e.g., a narrow glitch) having low energy but high amplitude. Thus, depending on the system, it may be advantageous to reduce the burr amplitude, the burr energy, or both, for a given application. An advantage of the spur self-characterization and calibration techniques described herein is that the DAC code update used for characterization relies on the response to the DAC spur of an ADC in closed-loop control (e.g., ADC 606 of fig. 15), and thus eliminates reliance on the exact shape of the spur waveform.

FIG. 24 shows that when the DAC glitch amplitude is further reduced (e.g., less than +1mV peak within the vertical dashed line), V is maintained _OUT ≈V _{Target object} The required code update amount becomes less than 1LSB and the control circuit keeps the code constant. Thus (2)Due to DAC code update, even if the loop tries to stabilize around a code transition with a given Mao Cineng amount (if the spur energy at the transition is less than the threshold), V _OUT And also becomes substantially ripple free. The threshold spur amplitude or spur energy may depend on the shape of the spur waveform, system parameters, and the dynamics of the control loop.

Fig. 25 is a circuit schematic of another example of an amplifier system. The example of fig. 25 shifts the voltage V without the range control switch SW of the amplifier system of fig. 15 _{Offset of} A control loop introduced into the two DAC architectures. During HV mode, control circuit 2502 drives the DACs simultaneously _IN And DAC _X So that the effective total gain becomes G _LV +G _X ＝G _HV . In one example embodiment, for a given V _{Target object} The control loop may attempt to control the power supply in the DAC as known _IN And DAC _X Is stabilized near the code transition that produces the high energy glitch in one or both. Alternatively, if the glitch profile of the code transition is unknown, then the glitch event may be detected at the system level, as in the block example described previously herein. In either case, if V _{Target object} The control circuit 2502 may introduce any offset in the DAC code while maintaining V, if the value corresponds to a high-glitch code boundary _OUT ≈V _{Target object} 。

For example, DAC _X The code may be incremented to force V _X Increasing the offset DeltaV _X And DAC _IN The code may be decremented to force V _IN Reducing DeltaV _X *G _X /G _LV Thereby maintaining V _OUT ＝G _X *V _X +G _LV *V _IN . The offset may be controlled (e.g., using another DAC to shift the adjustable offset (V _{Offset of} ) Added to the summing node). Furthermore, the offset value may be gradually increased, or a successive approximation or other more complex search algorithm may be used, until both DACs are comfortably in a glitch-free code space. After the offset in the code space is introduced between the two DACs, the control circuit 2502 will allow the control loop to control both DACs while maintaining a fixed offset. In this way the first and second components,both DACs will be located in code areas away from the high-spur boundary to minimize ripple in the output. When the system receives the pair V _{Target object} Control circuit 2502 may stabilize the loop to a new target V at the time of update of (a) _OUT The values are first combined together before the DAC codes.

Regarding the LV high resolution mode operation of the amplifier system of FIG. 15 shown in FIG. 17, the range switch SW will assist the DAC _X Is connected to G _X An input of the amplifier, and the main DAC _IN The output of (2) is connected to G _LV An amplifier. Thus, the amplifier systems of fig. 15 and 25 may become virtually identical in the LV high resolution mode.

As previously described herein with respect to the amplifier system of fig. 15, a DAC _X Is frozen and control circuit 1502 is attempting to freeze V _OUT ≈V _{Target object} Updating a DAC while remaining in a steady state _IN DAC code of (c). If DAC _IN The control circuit may perform the cyclic compensation described previously herein and cause undesirable ripple at the output, just near the DAC code where there is a high glitch boundary. The same is true for the amplifier system of fig. 25.

For the system architecture of fig. 15, 18 and 25 with multiple DACs, it is assumed that the auxiliary DAC (DAC in the example _X ) With sufficient resolution, then multiple points in the DAC code space can satisfy steady state V _OUT ≈V _{Target object} Conditions. If a high-glitch steady-state condition is detected, one or more DAC codes may be moved to another DAC code value far enough away from the high-glitch DAC code boundary to minimize ripple on the output due to DAC code transitions.

Fig. 26 is a diagram of the amplifier system of fig. 15 and 25 for different V in a low voltage high resolution (LV) mode _IN And V _X V of value _OUT For V _IN Graph of transmission curve. The vertical dashed line shows a DAC with high glitches _IN Code transition points. The area between the vertical dashed lines is free of burrs. Suppose the loop tries to be at point V _IN ＝V _A Near convergence, which is just atNear the high burr boundary. The amplifier system can infer that the convergence point is near the high-glitch code boundary by observing the DAC code. To avoid such high glitch conditions, the amplifier system should operate in the LV range, which also covers V _OUT ＝V _{Target object} But at V not near the boundary of the high-burr code _IN Operate at the value.

The multiple DAC architectures in the examples of fig. 15 and 25 increment the DAC up and down by _X The code or by adding an offset (+Δv) achieves a shift up and down of the LV range transfer curve. FIG. 26 shows a method for constant V _X Is a transmission line of different values. By combining DAC' s _X Code adjustment + deltax or addition of an offset (+deltav) to obtain the LV transmission line. For example, if DAC _X The code increases so that the voltage output increases +DeltaV (curve V _X ＝V _A +ΔV), then the loop will V _IN The value of (2) is reduced to

Thereby can maintain V _OUT ＝V _{Target object} . Thus, the control loop will converge to a DAC that is far from the high-glitch code boundary _IN Code.

Fig. 27A and 27B illustrate a flow chart of an example of a method 2700 of closed loop spur suppression in an amplifier system. Method 2700 uses the offset to divert the DAC code away from the high-spur DAC code condition. The control circuit may determine what offset to apply based on the glitch condition of the system.

Fig. 27A shows an initialization phase. At block 2710, a determination is made as to whether the offset list is stored in memory or otherwise available. If an offset list is available, the offset list and the spur code list are loaded from memory into a control circuit or a dedicated monitoring circuit. At block 2720, the system waits for a set target (V _{Target object} ) Sum burr threshold (N) _{Threshold value} )。

At block 2730 in fig. 27B, if the offset list is not available, the control circuit sets the master DAC (DAC _IN ) And auxiliary DAC (DAC) _X ) To satisfy the DAC codes of (1)Targets (e.g. V _OUT ＝V _{Target object} ). No offset is applied. Reference level (e.g. V _REFS ) And may also be arranged to determine the range of the primary DAC and the auxiliary DAC.

At block 2740, if an offset list is available, the control circuitry applies the offset to the control loop. The offset may be applied in different ways. For example, the system may include an analog adder or subtractor circuit to apply an offset (voltage offset or current offset) to the summing node of the system, as in the example of fig. 15. In some examples, as in the example of fig. 18, the offset is applied using one or more auxiliary DACs. In some examples, the offset is included in a DAC code, and the control circuit loads the DAC code containing the offset. In other examples, the reference of the DAC may be adjusted (e.g., by analog means or using an auxiliary DAC) to include the offset.

When the DAC code is set, the control loop of the system directs the output of the system to a steady state output target (e.g., V _OUT ≈V _{Target object} ). The control circuit may make small changes (e.g., one or two LSBs) to the DACIN code that are less than the threshold to compensate for the small changes in conditions. Code updates are monitored and, at block 2750, if the change is less than a threshold (N _{Threshold value} LSB), the control circuit continues to monitor system stability and the glitch flag is not raised or activated.

If it is required to be greater than N _{Threshold value} The main DAC code of the LSB is changed and the high spur flag signal is asserted or activated. At 2760, when a high-glitch code transition is encountered, the DAC code may be recorded in memory. The control circuit (or dedicated monitoring circuit) may also record the sign amplitude of the spur at a given transition based on the peak or average code update observed in steady state. Subsequently, the control circuit may apply a predetermined offset value when a previously recorded high-glitch transition condition is expected. The predetermined offset value may be used as part of the starting approximation to find a new steady state of the system.

At block 2770, the offset to be applied to a given transition may be fixed or continuously updated based on an optimization algorithm or a Machine Learning (ML) algorithm. For example, the amplifier system may observe the DAC code and, based on the DAC code and the detected spur, the system may determine the location of the spur in the DAC code and how much energy the spur has. The system may infer that the current DAC code space is in a high-glitch state and may apply one or both of DAC code changes and offsets to keep one or more master DACs away from instability. Thus, the amplifier system can self-characterize the current system conditions.

At block 2780, the system may calculate the required offset from the spur amplitude, spur sign, and DAC code and update the offset list. The process returns to block 2740 to apply the calculated offset and to monitor system stability.

To date, the small glitch mitigation methods described herein may operate in the background without interfering with the normal operation of the system for an extended period of time. The spur mitigation method may detect when the control loop is stabilized near a high spur DAC code transition and may capture information about the sign and relative amplitude of the spur based on DAC code updates made by the control circuit in steady state. The control circuit may then apply the offset calculated by the amplifier system with a fixed or varying amplitude as a function of the characteristic glitch parameter.

If writable memory is available in the amplifier system, the control circuit or dedicated monitoring circuit can record high energy glitch code with relative amplitude as well as sign information. Other key artifacts may be recorded to achieve effective glitch mitigation. The offset for a given code transition may be proportional or inversely proportional to the relative amplitude and sign of the glitch, and the offset may be continuously updated as the system encounters a new code transition with a high glitch.

Alternatively, a system level foreground calibration may be designed that may run periodically (e.g., where operating conditions such as temperature, power consumption, or load have changed significantly) at power-up, when the system is idle and inoperable, or during system operation. The result of the calibration is a list of offsets that can be stored in memory and loaded when configuring the amplifier system.

Fig. 28A and28B shows a flowchart of an example of a method 2800 for foreground calibration for spur characterization and offset calculation in a closed loop amplifier system. Assuming that the target voltage ranges from V _MIN To V _MAX During calibration of a given DAC of a single DAC system or a multiple DAC system, V _{Target object} Value of value from V _MIN Sweep up to V _MAX Then from V _MAX Sweep down to V _MIN (and vice versa).

At 2810, V _{Target object} The value sets the corresponding target measurement ADC code). At 2820, the system records DAC spur amplitude and sign information in memory at each code transition based on the amplitude and direction of the DAC code update required for steady state. Only the amplitude (or energy) is greater than the set threshold (N _{Threshold value} ) Can be recorded to save memory space.

Once the high energy DAC code transition with sign and magnitude information is captured and recorded, the system may calculate an offset that should be applied to each case during normal operation at block 2830. The offset may be calculated as a function of the spur code, the spur size, and the spur symbol. In this way, all relevant spur characteristics can be determined for a system with multiple DACs without having to obtain any spur characteristic data in advance. The system may also utilize previous characterization data and/or complete faster system characterization during normal operation.

At block 2840, the calculated offset is stored in memory. This offset list may then be used to load into the control circuit of the system or a separate monitoring circuit to move the DAC code away from the high-glitch transition. An advantage of system perspective calibration is that by applying a predetermined offset based on glitch information (e.g., glitch feature data) stored in memory, the system can systematically avoid high glitch code transitions during normal operation.

The spur mitigation process may include machine learning as part of the process of identifying DAC code changes when high spur transfer conditions are detected. The glitch in the DAC code transition is a negative attribute of the system and needs to be minimized. The burr optimization may be a minimization exercise. In machine learning, the minimization of the spur may be determined by optimizing a loss function or a cost function. The loss function may be a combination of spike attributes, the goal of machine learning being to minimize these attributes.

Overall based analysis can be used to determine which DAC code sets are needed and which are to be avoided in DAC code changes. The glitch performance of the amplifier system may have a multi-modal distribution in which low-glitch code packets are different from high-glitch codes. The distribution may be DAC architecture dependent or system design dependent. For example, a multi-level DAC may tend to have multiple modes, while a trapezoidal DAC does not tend to have discrete sub-levels, and thus may have different code distributions, and may not exhibit a distinct multi-mode distribution. The optimization algorithm may analyze the spur performance to determine the spur transitions that should be avoided. The energy or amplitude of the DAC spur may be characterized or quantified. Code panic may be performed on the most severe glitches specific to the system to maintain a stable output. The characterized spur data may be stored. The occasional DAC code set may be selected based on the previously recorded DAC spur data. Code conversion may be limited to codes available to the system. The spur data analysis may be used to determine a DAC code set to mitigate the spur, thereby avoiding potential mitigation of code changes that do not significantly affect.

Fig. 29 is a flow chart of an example of a method 2900 of feedback control of an amplifier system. The amplifier system may be any DAC controlled amplifier system described herein. At block 2905, an amplifier circuit of the amplifier system is driven by one or more DAC circuits to set an output of the amplifier system. At block 2910, the DAC circuit is operated using the first set of DAC codes to set the system output to a steady-state target output.

At block 2915, the control circuitry of the amplifier system identifies that the first set of DAC codes includes a DAC code conversion (or multiple DAC code conversions) associated with a high-glitch condition, and that the high-glitch DAC code conversion is or will be used to set the system output to the target output. At block 2920, the control circuit changes to operate the DAC circuit using the second set of DAC codes. The second set of DAC codes sets the output to the same target output, or substantially the same target output, as the first set of DAC codes. However, the second set of DAC codes does not include DAC transcoding associated with a high spur condition. Thus, the glitch energy at the output is reduced.

The final code set selection may be hardware constrained. The optimization algorithm may use knowledge of the DAC architecture in the analysis (e.g., certain codes or bit transitions have repeatable patterns throughout the code set). The occasional DAC code set may be determined based on knowledge of the system design. An emergency code set may also be included to address unknown artifacts (e.g., due to parasitics) that may occur in the system.

The spur mitigation techniques described herein utilize a closed loop setup, allowing the DAC to stabilize at different DAC codes while maintaining a target output voltage or current. The technique provides a glitch self-characterization and background and foreground calibration for closed loop DAC glitch mitigation.

Additional description and examples

Example 1 includes a subject matter (e.g., a feedback control method of an amplifier system), comprising: driving a plurality of amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set a system output of the amplifier system; operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state target output; detecting a high spur condition at an output of the at least one DAC circuit when the first set of DAC codes is used; changing to operating the at least one DAC circuit using a second set of DAC codes to set the system output to a substantially same steady-state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the at least one DAC circuit.

In example 2, the subject matter of example 1 optionally includes: a high energy glitch transition greater than a threshold glitch transition is detected while operating the at least one DAC circuit using the first set of DAC codes.

In example 3, the subject matter of one or both of examples 1 and 2 optionally includes: identifying the first set of DAC codes includes DAC code transitions associated with the high-glitch condition when the system output is set to the steady-state target output.

In example 4, the subject matter of one or any combination of examples 1-3 optionally includes: setting the system output to the steady state target output using a control loop comprising a feedback circuit path; and adding an offset to the control loop to operate the at least one DAC circuit using the second set of DAC codes.

In example 5, the subject matter of example 4 optionally includes: a programmable offset is added to the control loop using another DAC circuit.

In example 6, the subject matter of one or any combination of examples 1-5 optionally includes: applying an output of the at least one DAC circuit to an input of a first amplifier circuit and an output of a second amplifier circuit of the plurality of amplifier circuits when the amplifier system is operated in a first mode; and in a second mode, applying an output of the at least one DAC circuit to the input of the first amplifier circuit and an output of another DAC circuit to an input of the second amplifier circuit, wherein the second mode has a lower voltage output than the first mode.

In example 7, the subject matter of one or any combination of examples 1-6 optionally includes: driving a plurality of DAC channels, wherein each DAC channel comprises a main DAC and an amplifier circuit, and the amplifier circuits of the DAC channels have different signal gains; operating a main DAC circuit of the DAC channels to set the system output using the first set of DAC codes and a summing output of the DAC channels; and setting the system output to the steady state target output using a control loop and changing to operate the main DAC circuit using the second set of DAC codes to reduce ripple of the system output caused by the plurality of DAC channels.

In example 8, the subject matter of example 7 optionally includes: detecting a high energy glitch transition greater than a threshold glitch transition when the at least one DAC circuit is operated using the first set of DAC codes; determining an offset using the magnitude of the high energy spur transition and a current DAC code; and selecting a set of DAC codes as the second set of DAC codes using the determined offset.

In example 9, the subject matter of one or any combination of examples 1-8 optionally includes: updating a DAC code of the at least one DAC circuit using a DAC code value selected from the first set of DAC codes to set the system output to the steady-state target output; detecting when a DAC code of the at least one DAC circuit stabilizes near a high-glitch DAC code transition when the system output is set to the steady-state target output; and in response to the detecting, updating the DAC code of the at least one DAC circuit with a DAC code value selected from the second set of DAC codes.

Example 10 includes a subject matter (e.g., an amplifier system), or may alternatively be combined with one or any combination of examples 1-9 to include a subject matter comprising: at least one digital-to-analog converter (DAC) circuit, wherein setting a DAC code in the at least one DAC circuit sets an output of the at least one DAC circuit; a plurality of amplifier circuits including an input connected to an output of the at least one DAC circuit; a feedback circuit path connected to a system output of the amplifier system; and a control circuit connected to the at least one DAC circuit and the feedback circuit path, wherein the control circuit is configured to: operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state output target; and changing to operate the at least one DAC circuit using a second set of DAC codes to maintain the same steady-state output target and reduce ripple at the system output caused by the at least one DAC circuit.

In example 11, the subject matter of example 10 optionally includes: a control loop including the feedback circuit and the control circuit; the control circuit is configured to: detecting a high-glitch transition of the first set of DAC codes, the high-glitch transition being greater than a threshold glitch transition; and adding an offset to the control loop to change to select the DAC codes from the second set of DAC codes.

In example 12, the subject matter of example 11 optionally includes: another DAC circuit for adding the offset to the control loop; and the control circuit is configured to set the offset according to the magnitude of the high-glitch transition and one or more DAC code values corresponding to the high-glitch transition.

In example 13, the subject matter of one or both of examples 11 and 12 optionally includes: a summing node connected to outputs of the plurality of amplifier circuits; the at least one DAC circuit comprises a plurality of DAC circuits; inputs of the plurality of amplifier circuits are connected to outputs of the plurality of DAC circuits to form a plurality of DAC channels, and outputs of the plurality of amplifier circuits are connected to the summing node. The control circuit is optionally configured to: updating DAC codes of the plurality of DAC circuits to maintain the steady-state output target; and adding the offset to the summing node to change to select the DAC codes from the second set of DAC codes.

In example 14, the subject matter of one or any combination of examples 11-13 optionally includes: the plurality of amplifier circuits includes a first amplifier circuit and a second amplifier circuit, and the at least one DAC circuit includes a first DAC circuit connected to an input of the first amplifier circuit and a second DAC circuit connected to an input of the second amplifier circuit. The control circuit is configured to: updating DAC codes of both the first DAC circuit and the second DAC circuit to apply equal DAC outputs to the first amplifier circuit and the second amplifier circuit to set the system output to the steady-state output target in a first mode; and updating only the DAC code of the first DAC circuit in a second mode to set the system output to the steady-state output target, wherein the second mode has a lower output voltage range than the first mode.

In example 15, the subject matter of one or any combination of examples 10-14 optionally includes: a switching circuit; the plurality of amplifier circuits includes a first amplifier circuit and a second amplifier circuit, and the at least one DAC circuit includes a first DAC circuit and a second DAC circuit. An output of the first DAC circuit is connected to an input of the first amplifier circuit. The switching circuit is configured to: connecting an output of the first DAC circuit to an input of the second amplifier circuit in the first mode; and connecting an output of the second DAC circuit to an input of the second amplifier circuit in the second mode, wherein the second mode has a lower voltage output range than the first mode.

In example 16, the subject matter of one or any combination of examples 10-15 optionally includes: a system memory; and the control circuit is configured to: scanning the DAC code of the at least one DAC code over a specified range of DAC code values; storing DAC spur characteristic data for DAC code conversion in the system memory; and detecting the high-glitch transition using the stored DAC glitch amplitude for the DAC code transition.

In example 17, the subject matter of one or any combination of examples 10-16 optionally includes: the feedback circuit path includes an analog-to-digital converter (ADC) circuit operably coupled to the system output; and the control circuit is configured to set the DAC code of the at least one DAC circuit to set the system output voltage to a steady-state output target voltage.

In example 18, the subject matter of one or any combination of examples 10-17 optionally includes: a sensed impedance at an output of the system; the feedback circuit path includes an analog-to-digital converter (ADC) circuit operably coupled to the sense impedance; and the control circuit is configured to set the DAC code of the at least one DAC circuit to set the system output current to a steady-state target output current.

Example 19 includes a subject matter (e.g., a power system with closed loop control), or may alternatively be combined with one or any combination of examples 1-18 to include a subject matter comprising: a plurality of digital-to-analog converter (DAC) channels, each DAC channel comprising a DAC circuit connected to an input of the amplifier circuit; a summing node connected to an output of the amplifier circuit of the DAC channel to provide a system output; and a control circuit operatively coupled to the DAC channel and the system output. The control circuit is configured to: updating DAC circuitry of the DAC channel with a DAC code to adjust the system output to a steady-state target output in a steady-state, wherein the DAC code is selected from a first set of DAC codes; detecting when the DAC code selected from the first set of DAC codes causes a glitch condition at the output of the DAC circuit in the steady state; and changing to select a DAC code from a second set of DAC codes that maintain the same steady-state target output and reduce glitches at the output of the DAC circuit.

In example 20, the subject matter of example 19 optionally includes: the control circuit is configured to: determining a control loop offset from a spur amplitude of the Gao Maoci DAC code transition; and adding the control loop offset to the summing node to change to select the DAC codes from the second set of DAC codes.

These non-limiting examples may be combined in any permutation or combination. The foregoing detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings illustrate by way of example specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". All publications, patents, and patent documents mentioned in this document are incorporated by reference in their entirety as if individually incorporated by reference. If usage between the present document and the document incorporated by reference is inconsistent, the usage in the incorporated reference should be considered as a supplement to the usage of the present document; for irreconcilable inconsistencies, the usage in this document controls.

In this document, the terms "a" or "an" are used throughout the patent document to include one or more, independent of any other instance or usage of "at least one" or "one or more," unless otherwise indicated, "a or B" includes "a but not B," B but not a "and" a and B. In the appended claims, the terms "including" and "which" are used as the plain-english equivalents of the respective terms "and" wherein. Furthermore, the terms "comprising" and "including" in the following claims are open-ended, i.e., the system, apparatus, article, and process that comprises an element other than the element listed after such term in the claims is still considered to fall within the scope of the claims. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Examples of methods described herein can be at least partially machine or computer implemented.

Claims (20)

1. A feedback control method of an amplifier system, the method comprising:

driving a plurality of amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set a system output of the amplifier system;

operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state target output;

detecting a high spur condition at an output of the at least one DAC circuit when the first set of DAC codes is used; and

changing to operating the at least one DAC circuit using a second set of DAC codes to set the system output to a substantially same steady-state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the at least one DAC circuit.

2. The method of claim 1, wherein detecting the high-glitch condition comprises detecting a high-energy glitch transition greater than a threshold glitch transition when the at least one DAC circuit is operated using the first set of DAC codes.

3. The method of claim 1, wherein detecting the high-glitch condition comprises identifying that the first set of DAC codes includes DAC code transitions associated with the high-glitch condition when the system output is set to the steady-state target output.

4. The method according to claim 1, comprising:

setting the system output to the steady state target output using a control loop comprising a feedback circuit path; and

wherein the changing to operate the at least one DAC circuit using a second set of DAC codes includes adding an offset to the control loop to operate the at least one DAC circuit using the second set of DAC codes.

5. The method of claim 4, wherein adding the offset to the control loop comprises adding a programmable offset to the control loop using another DAC circuit.

6. The method according to claim 1, comprising:

applying an output of the at least one DAC circuit to an input of a first amplifier circuit and an output of a second amplifier circuit of the plurality of amplifier circuits when the amplifier system is operated in a first mode; and

in a second mode, an output of the at least one DAC circuit is applied to the input of the first amplifier circuit and an output of another DAC circuit is applied to an input of the second amplifier circuit, wherein the second mode has a lower voltage output than the first mode.

7. The method of claim 1, wherein the driving the plurality of amplifier circuits comprises:

driving a plurality of DAC channels, wherein each DAC channel comprises a main DAC and an amplifier circuit, and the amplifier circuits of the DAC channels have different signal gains;

operating a main DAC circuit of the DAC channels to set the system output using the first set of DAC codes and a summing output of the DAC channels; and

the system output is set to the steady state target output using a control loop and changed to operate the main DAC circuit using the second set of DAC codes to reduce ripple of the system output caused by the plurality of DAC channels.

8. The method of claim 7, comprising:

detecting a high energy glitch transition greater than a threshold glitch transition when the at least one DAC circuit is operated using the first set of DAC codes;

determining an offset using the magnitude of the high energy spur transition and a current DAC code; and

a set of DAC codes is selected as the second set of DAC codes using the determined offset.

9. The method according to claim 1, comprising:

updating a DAC code of the at least one DAC circuit using a DAC code value selected from the first set of DAC codes to set the system output to the steady-state target output;

Detecting when a DAC code of the at least one DAC circuit stabilizes near a high-glitch DAC code transition when the system output is set to the steady-state target output; and

in response to the detecting, the DAC code of the at least one DAC circuit is updated with a DAC code value selected from the second set of DAC codes.

10. An amplifier system, comprising:

at least one digital-to-analog converter (DAC) circuit, wherein setting a DAC code in the at least one DAC circuit sets an output of the at least one DAC circuit;

a plurality of amplifier circuits including an input connected to an output of the at least one DAC circuit;

a feedback circuit path connected to a system output of the amplifier system; and

a control circuit connected to the at least one DAC circuit and the feedback circuit path, wherein the control circuit is configured to:

operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state output target; and

changing to operate the at least one DAC circuit using a second set of DAC codes to maintain the same steady-state output target and reduce ripple at the system output caused by the at least one DAC circuit.

11. The amplifier system of claim 10, comprising:

a control loop including the feedback circuit and the control circuit;

wherein the control circuit is configured to:

detecting a high-glitch transition of the first set of DAC codes, the high-glitch transition being greater than a threshold glitch transition; and

an offset is added to the control loop to change to select the DAC codes from the second set of DAC codes.

12. The amplifier system of claim 11, comprising:

another DAC circuit for adding the offset to the control loop; and

wherein the control circuit is configured to set the offset in accordance with the magnitude of the high-glitch transition and one or more DAC code values corresponding to the high-glitch transition.

13. The amplifier system of claim 11, comprising:

a summing node connected to outputs of the plurality of amplifier circuits;

wherein the at least one DAC circuit comprises a plurality of DAC circuits;

wherein inputs of the plurality of amplifier circuits are connected to outputs of the plurality of DAC circuits to form a plurality of DAC channels, and outputs of the plurality of amplifier circuits are connected to the summing node; and

Wherein the control circuit is configured to:

updating DAC codes of the plurality of DAC circuits to maintain the steady-state output target; and

the offset is added to the summing node to change to select the DAC codes from the second set of DAC codes.

14. The amplifier system of claim 11,

wherein the plurality of amplifier circuits includes a first amplifier circuit and a second amplifier circuit, and the at least one DAC circuit includes a first DAC circuit connected to an input of the first amplifier circuit and a second DAC circuit connected to an input of the second amplifier circuit;

wherein the control circuit is configured to:

updating DAC codes of both the first DAC circuit and the second DAC circuit to apply equal DAC outputs to the first amplifier circuit and the second amplifier circuit to set the system output to the steady-state output target in a first mode; and

only the DAC code of the first DAC circuit is updated in a second mode to set the system output to the steady-state output target, wherein the second mode has a lower output voltage range than the first mode.

15. The amplifier system of claim 10, comprising:

A switching circuit;

wherein the plurality of amplifier circuits comprises a first amplifier circuit and a second amplifier circuit, and the at least one DAC circuit comprises a first DAC circuit and a second DAC circuit, wherein an output of the first DAC circuit is connected to an input of the first amplifier circuit; and

wherein the switching circuit is configured to:

connecting an output of the first DAC circuit to an input of the second amplifier circuit in the first mode; and

the output of the second DAC circuit is connected to the input of the second amplifier circuit in the second mode, wherein the second mode has a lower voltage output range than the first mode.

16. The amplifier system of claim 10, comprising:

a system memory; and

wherein the control circuit is configured to:

scanning the DAC code of the at least one DAC code over a specified range of DAC code values;

storing DAC spur characteristic data for DAC code conversion in the system memory; and

the high-glitch transition is detected using the stored DAC glitch amplitude for the DAC code transition.

17. The amplifier system of claim 10,

Wherein the feedback circuit path includes an analog-to-digital converter (ADC) circuit operably coupled to the system output; and

wherein the control circuit is configured to set the DAC code of the at least one DAC circuit to set the system output voltage to a steady-state output target voltage.

18. The amplifier system of claim 10, comprising:

a sensed impedance at an output of the system;

wherein the feedback circuit path includes an analog-to-digital converter (ADC) circuit operably coupled to the sense impedance; and

wherein the control circuit is configured to set the DAC code of the at least one DAC circuit to set the system output current to a steady-state target output current.

19. A power supply system with closed loop control, the power supply system comprising:

a plurality of digital-to-analog converter (DAC) channels, each DAC channel comprising a DAC circuit connected to an input of the amplifier circuit;

a summing node connected to an output of the amplifier circuit of the DAC channel to provide a system output; and

a control circuit operably coupled to the DAC channel and the system output, wherein the control circuit is configured to:

updating DAC circuitry of the DAC channel with a DAC code to adjust the system output to a steady-state target output in a steady-state, wherein the DAC code is selected from a first set of DAC codes;

Detecting when the DAC code selected from the first set of DAC codes causes a glitch condition at the output of the DAC circuit in the steady state; and

the method includes changing to select a DAC code from a second set of DAC codes that maintain the same steady state target output and reduce glitches at the output of the DAC circuit.

20. The power supply system of claim 19, wherein the control circuit is configured to:

determining a control loop offset from a spur amplitude of the Gao Maoci DAC code transition; and adding the control loop offset to the summing node to change to select the DAC codes from the second set of DAC codes.