CN117749166A - System and method for providing a delay locked loop with coarse tuning technique - Google Patents

Abstract

The present disclosure relates to systems and methods for providing a delay locked loop with coarse tuning techniques. In order to increase the operating frequency range of a Delay Locked Loop (DLL) while simultaneously reducing the varactor size, a coarse tuning circuit may be implemented in the DLL. The DLL may include a Voltage Controlled Delay Line (VCDL) including a plurality of switched capacitors coupled in parallel with each other. An electrical ground may be coupled to the parallel switched capacitor at a first node, and a snubber and variable capacitor may be coupled to the parallel switched capacitor at a second node. The coarse tuning circuit may be electrically coupled to the phase detector and to the plurality of switched capacitors of the VCDL such that the coarse tuning circuit may receive a signal (e.g., an indication of phase) from the phase detector and may adjust a switched capacitor load based on the signal received from the phase detector. Among other advantages, such DLL implementations can increase DLL tuning range and reduce phase noise.

Description

System and method for providing a delay locked loop with coarse tuning technique

Cross Reference to Related Applications

This patent application claims priority from U.S. provisional application 63/409,190 entitled "System and method for providing a delay locked Loop with coarse adjustment technique (SYSTEMS AND METHODS FOR PROVIDING A DELAY-LOCKED LOOP WITH COARSE TUNING TECHNIQUE)" filed on month 9 and 22 of 2022, the disclosure of which is incorporated by reference in its entirety for all purposes.

Technical Field

The present disclosure relates generally to wireless communications, and more particularly to phase shifting in wireless signals.

Background

In wireless communication devices, a Delay Locked Loop (DLL) may be used to change the phase of a clock signal (e.g., phase lock an input signal and an output signal, which may prevent or mitigate phase errors). It may be advantageous to achieve a wide operating frequency range for the DLL, which may be achieved by increasing the size of the varactors. However, increasing the varactor size may consume excessive space and may result in increased phase noise.

Disclosure of Invention

The following sets forth a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, the disclosure may encompass a variety of aspects that may not be set forth below.

In one embodiment, a delay locked loop may include: a phase detector; a loop filter coupled to the phase detector; a Voltage Controlled Delay Line (VCDL) electrically coupled to the loop filter and including a plurality of switched capacitors.

In another embodiment, a method comprises: receiving an indication of a phase of an input signal from a phase detector; activating, via the tuning circuit, the first plurality of switches to electrically couple the first plurality of capacitors to the first plurality of buffers to adjust the phase delay based on the indication of the phase; and inputting the input signal to the first plurality of buffers to apply the phase delay.

In yet another embodiment, an apparatus comprises: a plurality of antennas; and a transceiver coupled to the plurality of antennas, the transceiver including a phase detector; a loop filter coupled to the phase detector; a Voltage Controlled Delay Line (VCDL) electrically coupled to the loop filter and including a plurality of switched capacitors; and a coarse tuning circuit electrically coupled to the phase detector and the VCDL, the coarse tuning circuit configured to apply a first adjustment to an output signal of the VCDL by adjusting the plurality of switched capacitors based on an output of the phase detector.

Various refinements of the features noted above may exist in relation to various aspects of the present invention. Other features may also be added to these various aspects. These refinements and additional features may exist individually or in any combination. For example, various features discussed below in connection with one or more of the illustrated embodiments may be incorporated into any of the above aspects of the present invention, alone or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of embodiments of the present disclosure without limitation to the claimed subject matter.

Drawings

Various aspects of the disclosure may be better understood upon reading the following detailed description and upon reference to the drawings described below in which like numerals refer to like parts.

FIG. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure;

FIG. 2 is a functional diagram of the electronic device of FIG. 1 according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a transmitter of the electronic device of FIG. 1, according to an embodiment of the present disclosure; and

fig. 4 is a schematic diagram of a receiver of the electronic device of fig. 1 according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a Delay Locked Loop (DLL) that may be used in the electronic device of FIG. 1 to change the phase of a clock signal;

FIG. 6 is a schematic diagram of a DLL having coarse tuning capabilities provided by a coarse tuning circuit according to an embodiment of the present disclosure;

FIG. 7 is a flowchart of a method for adjusting the delay of the output signal of the DLL of FIG. 6 according to an embodiment of the present disclosure;

FIG. 8 is a graph illustrating the operational behavior of a simulated delay loop of a DLL; and is also provided with

Fig. 9 is a graph illustrating an operational behavior of the DLL of fig. 6 when a coarse tuning circuit is implemented, according to an embodiment of the present disclosure.

Detailed Description

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The use of the terms "substantially," "near," "about," "near," and/or "substantially" should be understood to include proximity to the target (e.g., design, value, and amount), such as within the limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.). Furthermore, it should be understood that any exact value, number, measurement, etc. provided herein is contemplated to include approximations of those exact values, numbers, measurement, etc. (e.g., within the limits of suitable or contemplated errors). In addition, the term "collection" may include one or more. That is, a collection may comprise a single collection of one member, but a collection may also comprise a collection of multiple members.

Delay Locked Loops (DLLs) may be used in electronic circuits to change the phase of a clock signal (e.g., phase lock an input signal and an output signal, which may prevent or mitigate phase errors). In some cases, the DLL may include a phase detector, a loop filter, and a Voltage Controlled Delay Line (VCDL), where the VCDL may delay an input signal and the phase detector and the loop filter may control a phase relationship between input/outputs. The VCDL may include a plurality of delay stages including buffers (e.g., inverters, etc.) and varactors or other variable capacitors (e.g., such as variable polarization capacitors). In order to increase the operating frequency range of the DLL, the size of the varactor can be increased. However, increasing the size of the varactors may consume excessive space on the DLL circuit and may result in increased phase noise.

In embodiments of the present disclosure, in order to increase the operating frequency range of a DLL while simultaneously reducing the varactor size, as well as achieving other desired advantages, a coarse tuning circuit may be implemented in the DLL. The VCDL may include a plurality of switched capacitors (e.g., a plurality of capacitors each coupled to a corresponding switch) coupled in parallel with each other. The electrical ground may be coupled to the parallel switched capacitor at a first node, and the snubber and varactor or other variable capacitor may be coupled to the parallel switched capacitor at a second node.

A coarse tuning circuit (e.g., a coarse tuning engine) may be electrically coupled to the phase detector and to the VCDL and to the plurality of switched capacitors such that the coarse tuning circuit may receive a signal (e.g., an indication of phase) from the phase detector and may adjust the switched capacitor load (e.g., by closing certain switches of the switched capacitors and/or opening certain switches of the switched capacitors) based on the signal received from the phase detector. Among other advantages, such DLL implementations can increase DLL tuning range, reduce phase noise and duty cycle distortion (e.g., due to varactors), can reduce or eliminate DLL false phase lock problems, and can improve DLL settling time.

Fig. 1 is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 may include, among other things, one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry) a memory 14, a non-volatile storage 16, a display 18, an input structure 22, an input/output (I/O) interface 24, a network interface 26, and a power supply 29. The various functional blocks shown in fig. 1 may include hardware elements (including circuits), software elements (including machine-executable instructions), or a combination of hardware and software elements (which may be referred to as logic). The processor 12, memory 14, non-volatile storage 16, display 18, input structure 22, input/output (I/O) interface 24, network interface 26, and/or power supply 29 may each be coupled directly or indirectly to each other (e.g., through or via another component, communication bus, network) to transmit and/or receive signals between each other. It should be noted that fig. 1 is only one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10.

For example, electronic device 10 may comprise any suitable computing device, including a desktop or notebook computer (e.g., available from Apple inc (Apple inc.) of Cupertino (California), california)Pro、MacBook/>mini or MacIn the form of (a), a portable electronic device, or a handheld electronic device such as a wireless electronic device or a smart phone (e.g., in the form of +_ available from apple corporation of Coptis, calif.)>Model form), tablet (e.g., in the form of +.o.available from apple Inc. of Coptis, california>Model form), wearable electronic device (e.g., in Apple ∈r available from Apple corporation of kubi, california>Forms of (c) and other similar devices. It should be noted that the processor 12 and other related items in fig. 1 may be embodied in whole or in part in software, hardware, or both. Further, the processor 12 and other related items in FIG. 1 may be a single stand-alone processing module, or may be wholly or partially incorporated within any of the other elements within the electronic device 10. Processor 12 may be implemented with a combination of general purpose microprocessors, microcontrollers, digital Signal Processors (DSPs), field Programmable Gate Arrays (FPGAs), programmable Logic Devices (PLDs), controllers, state machines, gate logic, discrete hardware components, dedicated hardware finite state machines, or any other suitable entity that can calculate or otherwise manipulate information. Processor 12 may include one or more application processors, one or more baseband processors, or both, and perform the various functions described herein.

In the electronic device 10 of fig. 1, the processor 12 may be operatively coupled with the memory 14 and the non-volatile storage 16 to execute various algorithms. Such programs or instructions for execution by the processor 12 may be stored in any suitable article of manufacture that includes one or more tangible computer-readable media. The tangible computer readable medium may include memory 14 and/or nonvolatile storage 16, alone or in combination, to store instructions or routines. Memory 14 and nonvolatile storage 16 may include any suitable articles of manufacture for storing data and executable instructions, such as random access memory, read only memory, rewritable flash memory, hard disk drives, and optical disks. Further, programs encoded on such computer program products (e.g., an operating system) may also include instructions executable by processor 12 to enable electronic device 10 to provide various functions.

In some embodiments, display 18 may facilitate viewing of images generated on electronic device 10 by a user. In some embodiments, display 18 may include a touch screen that may facilitate user interaction with a user interface of electronic device 10. Further, it should be appreciated that in some embodiments, the display 18 may include one or more Liquid Crystal Displays (LCDs), light Emitting Diode (LED) displays, organic Light Emitting Diode (OLED) displays, active Matrix Organic Light Emitting Diode (AMOLED) displays, or some combination of these and/or other display technologies.

The input structure 22 of the electronic device 10 may enable a user to interact with the electronic device 10 (e.g., press a button to increase or decrease the volume level). As with the network interface 26, the I/O interface 24 may enable the electronic device 10 to interact with various other electronic devices. In some embodiments, the I/O interface 24 may include an I/O port for hardwired connection for charging and/or content manipulation using standard connectors and protocols, such as the lighting connector provided by Apple inc. Of kubi, california, universal Serial Bus (USB), or other similar connectors and protocols. The network interface 26 may include, for example, one or more of the following interfaces: personal Area Networks (PANs), such as Ultra Wideband (UWB) orA network; local Area Network (LAN) or Wireless Local Area Network (WLAN), such as using one of the IEEE 802.11x series of protocols (e.g. +.>) Is a network of (a); and/or Wide Area Networks (WANs), such as any standard related to the third generation partnership project (3 GPP), including, for example, 3 rd generation (3G) cellular networks, universal Mobile Telecommunications System (UMTS), 4 th generation (4G) cellular networks, long term evolution->A cellular network, a long term evolution licensed assisted access (LTE-LAA) cellular network, a 5 th generation (5G) cellular network and/or a New Radio (NR) cellular network, a 6 th generation (6G) or super 6G cellular network, a satellite network, a non-terrestrial network, etc. In particular, network interface 26 may include one or more interfaces, for example, for using a cellular communication standard that defines and/or implements a 5G specification for a frequency range for wireless communication, including a millimeter wave (mmWave) frequency range (e.g., 24.25-300 gigahertz (GHz)). The network interface 26 of the electronic device 10 may allow communication over the aforementioned network (e.g., 5G, wi-Fi, LTE-LAA, etc.).

The network interface 26 may also include, for example, one or more interfaces for: a broadband fixed wireless access network (e.g.,) Mobile broadband wireless network (mobile +.>) Asynchronous digital subscriber line (e.g. ADSL, VDSL), digital video terrestrial broadcasting +.>Network and extended DVB handset>A network, an Ultra Wideband (UWB) network, an Alternating Current (AC) power line, etc.

As shown, the network interface 26 may include a transceiver 30. In some embodiments, all or part of transceiver 30 may be disposed within processor 12. The transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas, and thus may include a transmitter and a receiver. The power source 29 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and/or an Alternating Current (AC) power converter.

Fig. 2 is a functional diagram of the electronic device 10 of fig. 1 according to an embodiment of the present disclosure. As shown, the processor 12, memory 14, transceiver 30, transmitter 52, receiver 54, and/or antenna 55 (shown as 55A-55N, collectively antennas 55) may be coupled directly or indirectly to each other (e.g., through or via another component, communication bus, network) to transmit and/or receive signals between each other.

The electronic device 10 may include a transmitter 52 and/or a receiver 54 that enable transmission and reception of signals between the electronic device 10 and an external device via, for example, a network (e.g., including a base station or access point) or a direct connection, respectively. As shown, the transmitter 52 and the receiver 54 may be combined into the transceiver 30. The electronic device 10 may also have one or more antennas 55A-55N electrically coupled to the transceiver 30. Antennas 55A-55N may be configured in an omni-directional or directional configuration, in a single beam, dual beam, or multi-beam arrangement, etc. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple ones of antennas 55A through 55N of an antenna group or module are communicatively coupled to respective transceivers 30 and each transmit radio frequency signals that may be advantageously and/or destructively combined to form a beam. Electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers and/or multiple antenna for use in various communication standards. In some implementations, the transmitter 52 and the receiver 54 may transmit and receive information via other wired or wired systems or devices.

As shown, various components of the electronic device 10 may be coupled together by a bus system 56. The bus system 56 may include, for example, a data bus, a power bus other than a data bus, a control signal bus, and a status signal bus. The components of the electronic device 10 may be coupled together or accept or provide input to each other using some other mechanism.

As described above, the transceiver 30 of the electronic device 10 may include a transmitter and a receiver coupled to at least one antenna to enable the electronic device 10 to transmit and receive wireless signals. Fig. 3 is a block diagram of a transmitter 52 (e.g., a transmit circuit) that may be part of transceiver 30 according to an embodiment of the present disclosure. As shown, the transmitter 52 may receive outgoing data 60 in the form of digital signals to be transmitted via one or more antennas 55. Digital-to-analog converter (DAC) 62 of transmitter 52 may convert the digital signal to an analog signal and modulator 63 may combine the converted analog signal with a carrier signal. Mixer 64 may combine the carrier signal with a local oscillator signal 65 (which may include a quadrature component signal) from a local oscillator 66 to generate a radio frequency signal. A Power Amplifier (PA) 67 receives the radio frequency signal from mixer 64 and may amplify the modulated signal to an appropriate level to drive transmission of the signal via one or more antennas 55. A filter 68 (e.g., filter circuitry and/or software) of the transmitter 52 may then remove unwanted noise from the amplified signal to generate transmit data 70 to be transmitted via the one or more antennas 55. The filter 68 may include any suitable filter or filters that remove unwanted noise from the amplified signal, such as a band pass filter, a band reject filter, a low pass filter, a high pass filter, and/or a decimation filter. In addition, the transmitter 52 may include any suitable additional components not shown, or may not include some of the components shown, such that the transmitter 52 may transmit outgoing data 60 via one or more antennas 55. For example, the transmitter 52 may include additional mixers and/or digital up-converters (e.g., for converting an input signal from a baseband frequency to an intermediate frequency). As another example, if power amplifier 67 outputs the amplified signal within or substantially within the desired frequency range, transmitter 52 may not include filter 68 (such that filtering of the amplified signal may not be necessary).

Fig. 4 is a schematic diagram of a receiver 54 (e.g., a receive circuit) that may be part of transceiver 30 according to an embodiment of the present disclosure. As shown, the receiver 54 may receive the received data 80 from one or more antennas 55 in the form of analog signals. A Low Noise Amplifier (LNA) 81 may amplify the received analog signal to an appropriate level for processing by receiver 54. The mixer 82 may combine the amplified signal with a local oscillator signal 83 (which may include quadrature component signals) from a local oscillator 84 to generate an intermediate or baseband frequency signal. Filter 85 (e.g., filter circuitry and/or software) may remove undesirable noise, such as cross-channel interference, from the signal. The filter 85 may also remove additional signals received by the one or more antennas 55 at frequencies other than the desired signal. The filter 85 may include one or more any suitable filters for removing unwanted noise or signals from the received signal, such as a band pass filter, a band reject filter, a low pass filter, a high pass filter, and/or a decimation filter. Demodulator 86 may remove the radio frequency envelope from the filtered signal and/or extract a demodulated signal from the filtered signal for processing. Analog-to-digital converter (ADC) 88 may receive the demodulated analog signal and convert the signal to a digital signal of incoming data 90 for further processing by electronic device 10. Additionally, the receiver 54 may include any suitable additional components not shown, or may not include some of the components shown, such that the receiver 54 may receive the received data 80 via one or more antennas 55. For example, receiver 54 may include additional mixers and/or digital downconverters (e.g., for converting the input signal from an intermediate frequency to a baseband frequency).

Fig. 5 is a schematic diagram of a Delay Locked Loop (DLL) 100 that may be used in an electronic circuit (e.g., electronic device 10) to change the phase of a clock signal (e.g., phase lock an input signal and an output signal, which may prevent or mitigate phase errors). In particular, DLL 100 may be part of or coupled to local oscillator 66 of transmitter 52 and/or local oscillator 84 of receiver 54. DLL 100 includes a phase detector 102 that can receive an input signal at an input 108 and an output signal from an output 110 and can determine a first phase associated with the input signal and a second phase associated with the output signal. The phase detector 102 may determine a phase difference between the input phase and the output phase and may send an indication of the phase difference to a loop filter 104 electrically coupled to the phase detector 102. Loop filter 104 may remove unwanted components of the output signal of phase detector 102 and may provide loop stability and transient response tracking.

The loop filter 104 is electrically coupled to a Voltage Controlled Delay Line (VCDL) 106, which can adjust the phase of the output signal by adjusting the delay of the signal through the VCDL 106 based on the phase difference determined by the phase detector. The VCDL 106 includes buffers 112A and 112N (collectively referred to as buffers 112). In additional or alternative embodiments, buffer 112 may include or be replaced with any suitable circuit (e.g., an inverter circuit) that delays the signal. The VCDL 106 includes a varactor 114A electrically coupled to the output of the buffer 112A and a varactor 114N electrically coupled to the output of the buffer 112N (the varactors 114A and 114N are referred to herein as varactors 114). Each buffer/varactor pair may constitute a delay stage of the VCDL 106. Although only two delay stages are shown (e.g., only two buffers 112 and two varactors 114), the VCDL 106 may include any suitable number of delay stages (e.g., 3 or more delay stages, 5 or more delay stages, 10 or more delay stages, 50 or more delay stages, etc.). The varactors 114 may be biased by the loop filter 104 to increase or decrease the delay of the signal through the VCDL 106 to adjust the phase of the output signal. Together, the phase detector 102, loop filter 104, and VCDL 106 may form an analog delay loop capable of providing fine-tuned variations in the phase of the output signal. For example, the analog delay loop may provide a smaller granularity variation than may be provided by a coarse tuning circuit, as will be described in more detail below. While DLL 100 is shown as including varactor 114, it should be noted that DLL 100 may include other forms of variable capacitors, such as polarization variable capacitors.

In some cases, it may be desirable to increase the operating frequency range of the DLL 100. To increase the operating frequency range of the DLL 100, the size of the varactor 114 may be increased. However, increasing the size of the varactors 114 may consume excessive space on the DLL 100 and may result in increased phase noise. To increase the operating frequency range of the DLL 100 without increasing or minimizing the size of the varactor 114 and/or without increasing or minimizing the phase noise, a digital coarse tuning delay loop may be implemented in the DLL 100.

Fig. 6 is a schematic diagram of a DLL 150 with coarse tuning capabilities in accordance with an embodiment of the present disclosure. Similar to the DLL 100 of fig. 5, the DLL 150 includes an analog delay loop including the phase detector 102, the loop filter 104, and the VCDL 154, and a digital delay loop including the phase detector 102, the coarse tuning circuit 152, and the VCDL 154. The VCDL 154 includes a buffer 112, a varactor 114, a set of switched capacitors 156A and 156B coupled between the buffer 112A and the varactor 114A, and a set of switched capacitors 156C and 156D coupled between the buffer 112N and the varactor 114N. Switched capacitors 156A, 156B, 156C, and 156D are referred to herein as switched capacitors 156. Switched capacitors 156 may each include a switch (e.g., a transistor) coupled to the capacitor.

Each set of switched capacitors 156 includes two or more switched capacitors 156 in parallel. Switched capacitor 156A is coupled in parallel to switched capacitor 156B, and switched capacitors 156A and 156B are coupled to ground 158 at a first terminal 160 and to the output of buffer 112A and varactor 114A at a second terminal 162. Similarly, switched capacitor 206C is coupled in parallel to switched capacitor 156D, and switched capacitors 156C and 156D are coupled to ground 158 at first terminal 164 and to the output of buffer 112N and varactor 114N at second terminal 166.

As previously mentioned, the DLL 150 includes a digital delay loop that includes a coarse tuning circuit 152 coupled to the phase detector 102 and the VCDL 154. Coarse tuning circuit 152 may operate in parallel with loop filter 104 and may provide coarse granularity adjustment to the output signal at output 110 of DLL 150 to supplement the fine granularity adjustment provided by loop filter 104. For example, the coarse tuning circuit 152 may provide a larger granularity adjustment than may be provided by an analog delay loop as described above. The coarse tuning circuit 152 may provide coarse granularity delay tuning of the output voltage signal by opening or closing a switched capacitor 156 of the VCDL 154. For example, the coarse tuning circuit 152 may increase the delay in the signal at the output 110 by coupling to or activating one or more of the switched capacitors 156. Conversely, the coarse tuning circuit 152 may reduce the delay in the signal at the output 110 by decoupling or disabling one or more of the switched capacitors 156. The coarse tuning circuit 152 may be implemented in whole or in part as hardware, software, or a combination of both.

Fig. 7 is a flowchart of a method 200 for adjusting the delay of the output signal of DLL 150 according to an embodiment of the present disclosure. Any suitable device (e.g., controller, processor 12) that can control components of electronic device 10, such as processor 12, may perform method 200. In some implementations, the method 200 may be implemented by using the processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium, such as the memory 14 or the storage device 16. For example, the method 200 may be performed, at least in part, by one or more software components, such as an operating system of the electronic device 10, one or more software applications of the electronic device 10, and so forth. Although method 200 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps may be performed in a different order than shown and that certain described steps may be skipped or not performed at all.

In process block 202, the phase detector 102 of the DLL 150 may receive an input signal from the input 108 and an output signal from the output 110. In process block 204, the phase detector 102 may determine a phase difference between the input signal and the output signal. In process block 206, the DLL 150 may adjust the delay of the output signal (e.g., thereby adjust the phase) via the coarse adjustment circuit 152 based on the phase difference determined by the phase detector 102 in process block 204 to generate an adjusted output signal. As discussed above, the coarse tuning circuit 152 may increase or decrease the delay through or decoupled from a switched capacitor 156 coupled to the VCDL 154. For example, the coarse tuning circuit 152 may close the switch of the switched capacitor 156 to increase the delay of the output signal, or may open the switch of the switched capacitor 156 to decrease the delay of the output signal. The coarse tuning circuit 152 may adjust the delay of the output signal (e.g., thereby adjust the phase) to match the phase of the input signal or maintain a desired offset between the input signal and the output signal (e.g., maintain the output phase at ±180 degrees of the input phase).

In query block 208, processor 12 may determine whether the phase of the first adjusted output signal is within a threshold range of desired phases. For example, the threshold range may include a phase error of ±2 degrees or more, ±5 degrees or more, ±10 degrees or more, and the like. If, in query block 208, processor 12 determines that the phase of the first adjusted output signal is within the threshold range of the desired phase, method 200 may return to process block 202 without further adjustment of the output signal. If in query block 208, processor 12 determines that the phase of the first adjusted output signal is not within the threshold range of the desired phase, then in process block 210, processor 12 may cause DLL 150 to adjust the phase of the output signal via the analog delay loop to produce a subsequent adjusted output signal. That is, processor 12 may cause loop filter 104 to bias varactors 114A and/or 114N to increase or decrease the delay of the output signal at a fine granularity level based on the phase difference determined by phase detector 102. Once the analog delay loop has produced a subsequent adjusted output signal, the method 200 may return to query block 208 to determine whether the phase of the output signal is within a threshold range of the desired phase. The method 200 may be iteratively repeated until the phase of the output signal is within a threshold range of desired phases (e.g., within a desired range of input/output phase relationships). Once the phase of the output signal is within the threshold range of the desired phase, DLL 150 may close the analog loop (e.g., may cause loop filter 104 to stop biasing varactor 114), may close the digital loop (e.g., may cause the coarse tuning circuit to stop adjusting switched capacitor 156), or both.

The coarse tuning circuit 152 may provide several benefits to the DLL 150. For example, in some cases, such as with respect to DLL 100, there may be a tradeoff between the tuning range of DLL 100 and the phase noise such that as the tuning range increases (e.g., by increasing the size of varactor 114), the phase noise also increases. However, since the coarse tuning circuit 152 provides an increased tuning range by adjusting the load of the set of switched capacitors 156 over a wide range without increasing the varactor size, the increase in phase noise associated with the increased tuning range may be reduced or eliminated. In another example, the coarse tuning circuit 152 may improve the output clock duty cycle. In some cases, such as with respect to DLL 100, varactors 114 may be associated with a nonlinear capacitance that may cause duty cycle distortion. The reduced size of the varactors 114 in the DLL 150 may reduce duty cycle distortion.

In another example, the coarse tuning circuit 152 may mitigate false phase locking in the DLL 150. In some cases, such as with respect to DLL 100, false phase locking may occur due to phase ambiguity. However, the coarse tuning circuit 152 may achieve greater control than an analog feedback loop, thereby reducing the likelihood of false phase locking. In yet another example, the coarse tuning circuit 152 may improve the settling time of the DLL 150. During coarse tuning, the coarse tuning circuit 152 may quickly adjust the phase of the output signal of the DLL 150 to a desired value. When the analog loop begins, the residual phase error (e.g., the phase error remaining after adjustment by the coarse adjustment circuit 152) is much smaller than the initial phase error, thereby improving the settling time of the DLL 150.

Fig. 8 is a graph 250 illustrating the operational behavior of a simulated delay loop of DLL 150. Graph 250 includes a delay 252 on the longitudinal axis and a voltage 254 on the transverse axis. Curve 256 represents voltage tuning (e.g., without supplemental tuning from coarse tuning circuit 152) applied by the analog loop of DLL 150 (e.g., phase detector 102, loop filter 104, and VCDL 154) to achieve the desired delay. For example, curve 256 may illustrate a voltage output that may be applied by varactor 114 to provide the delay required to cover process variations and temperature drift of DLL 150. Fig. 9 is a graph 300 illustrating the operational behavior of DLL 150 when a coarse tuning circuit is implemented, in accordance with an embodiment of the present disclosure. Graph 300 includes curves 302, 304, 306, 308, 310, and 312 that represent voltage tuning applied by an analog loop of DLL 150 (e.g., phase detector 102 and loop filter 104) to achieve a desired delay. As can be appreciated, the curves 302, 304, 306, 308, 310, and 312 have shallower slopes than the curve 256 because the analog loop adjusts for residual phase errors after the coarse tuning circuit 152 performs the phase adjustment. For example, the curves 302, 304, 306, 308, 310, and 312 may represent the slope of the voltage tuning of the analog loop when the coarse tuning circuit 152 covers the delay associated with the process variation and the analog loop covers the delay associated with the temperature drift.

The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

The techniques described and claimed herein are referenced and applied to specific examples of physical and practical properties that significantly improve the art and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [ performing ] [ function ]," or "step for [ performing ]," these elements are to be interpreted in accordance with 35u.s.c.112 (f). However, for any claim containing elements specified in any other way, these elements will not be construed in accordance with 35u.s.c.112 (f).

It is well known that the use of personally identifiable information should follow privacy policies and practices that are recognized as meeting or exceeding industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of inadvertent or unauthorized access or use, and the nature of authorized use should be specified to the user.

Claims (20)

1. A delay locked loop, comprising:

a phase detector;

a loop filter coupled to the phase detector; and

a plurality of switched capacitors electrically coupled to the loop filter.

2. The delay locked loop of claim 1, wherein a Voltage Controlled Delay Line (VCDL) comprises the plurality of switched capacitors and one or more varactors, each of the one or more varactors comprising

A buffer electrically coupled to the plurality of switched capacitors, an

A variable capacitor.

3. The delay locked loop of claim 2, wherein the variable capacitor comprises a polarization variable capacitor.

4. The delay locked loop of claim 2, comprising a coarse tuning circuit configured to tune the output signal of the VCDL, wherein the variable capacitor is configured to close an analog loop in response to determining that the coarse tuning circuit has completed tuning.

5. The delay locked loop of claim 2, wherein the plurality of switched capacitors are coupled in parallel.

6. The delay locked loop of claim 2, wherein the plurality of switched capacitors are coupled to electrical ground at a first node and to the buffer and the variable capacitor at a second node.

7. The delay locked loop of claim 1, comprising a coarse tuning circuit configured to tune a phase of the output signal based on adjusting the plurality of switched capacitors.

8. A method, comprising:

receiving an indication of a phase of an input signal from a phase detector;

activating a first plurality of switches via a tuning circuit to electrically couple a first plurality of capacitors to a first plurality of buffers to adjust a phase delay based on the indication of the phase; and

the input signal is input to the first plurality of buffers to apply the phase delay.

9. The method of claim 8, comprising disabling a second plurality of switches via the tuning circuit to electrically decouple a second plurality of capacitors from a second plurality of buffers to adjust the phase delay based on the indication of the phase.

10. The method of claim 8, wherein activating the first plurality of switches via the tuning circuit comprises coupling the first plurality of capacitors to a plurality of polarization variable capacitors.

11. The method of claim 8, wherein coupling the first plurality of capacitors to the first plurality of buffers increases the phase delay.

12. The method of claim 8, comprising:

receiving another indication of a difference between a first phase of the input signal and a second phase of the output signal; and

one or more varactors are biased based on the differences to adjust the phase delays.

13. The method of claim 12, comprising biasing the one or more varactors in response to determining that the phase delay is not within a threshold range of desired phase delays.

14. An apparatus, comprising:

a plurality of antennas; and

a transceiver coupled to the plurality of antennas, the transceiver comprising

The phase detector is used to detect the phase of the light,

a loop filter coupled to the phase detector,

a Voltage Controlled Delay Line (VCDL) electrically coupled to the loop filter and including a plurality of switched capacitors, an

A coarse tuning circuit electrically coupled to the phase detector and the VCDL, the coarse tuning circuit configured to apply a first phase adjustment to an output signal of the VCDL by adjusting the plurality of switched capacitors based on an output of the phase detector.

15. The apparatus of claim 14, wherein the VCDL comprises

A buffer electrically coupled to the plurality of switched capacitors, an

A variable capacitor.

16. The apparatus of claim 15, wherein the phase detector, the loop filter, the buffer, and the variable capacitor comprise an analog delay loop configured to apply a second phase adjustment to the output signal of the VCDL.

17. The apparatus of claim 16, wherein the analog delay loop is configured to apply the second phase adjustment based on a phase of the output signal being outside a threshold range of desired phases.

18. The apparatus of claim 16, wherein the second phase adjustment comprises a finer granularity phase adjustment than the first phase adjustment.

19. The apparatus of claim 16, wherein the second phase adjustment is provided based on a variable capacitor of the loop filter biasing the VCDL.

20. The apparatus of claim 19, wherein the plurality of switched capacitors are coupled to a buffer and a variable capacitor at a first node and to an electrical ground at a second node.