CN117748627A - Method, device, equipment and medium for inhibiting overvoltage of direct current bus of inverter - Google Patents
Method, device, equipment and medium for inhibiting overvoltage of direct current bus of inverter Download PDFInfo
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Abstract
The invention relates to the technical field of inverter control, and discloses a method, a device, equipment and a medium for inhibiting overvoltage of a DC bus of an inverter, wherein the method comprises the following steps: obtaining an initial voltage angular frequency and an initial voltage amplitude based on power outer loop control; when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than a first threshold voltage, judging whether the active power of the inverter is larger than the reactive power; when the active power is larger than the reactive power, compensating and converting the angular frequency of the initial voltage to obtain a phase angle reference value, taking the initial voltage amplitude as a voltage amplitude reference value, and constructing a voltage reference instruction based on the phase angle reference value and the voltage amplitude reference value; and based on the voltage reference instruction, the switching sequence of the inverter is obtained by utilizing voltage-current inner loop control. The invention realizes the control of active or reactive circulation in the no-load parallel scene of the inverter by utilizing an active and reactive competition mechanism, thereby inhibiting bus overvoltage and improving the stability of the system.
Description
Technical Field
The invention relates to the technical field of inverter control, in particular to a method, a device, equipment and a medium for inhibiting overvoltage of a direct current bus of an inverter.
Background
In the future, new energy power supply such as photovoltaic wind power and the like gradually replaces traditional power generation modes such as firepower water power and the like, and gradually takes the dominant role. The reduction of specific gravity of the traditional power generation mode means that a power grid needs a brand new power grid support, but the current mainstream grid following control cannot provide beneficial support. The virtual synchronous machine (Virtual Synchronous Generator, VSG) control is used as the current mainstream network construction control, is externally embodied as voltage source characteristics, and has better parallel networking capability; meanwhile, virtual inertia simulation of the synchronous generator can be realized, and the inertia and damping level of the system can be effectively improved, so that friendly grid connection of new energy sources is realized.
In a parallel system, there is a certain line impedance between the inverters. When the network-structured control is adopted and the equivalent of line impedance is pure inductive, the output active power of the parallel inverter is positively correlated with the phase angle, and the output reactive power is positively correlated with the amplitude of the output voltage. Under the actual parallel scene, the output phase and amplitude of each inverter are inconsistent due to factors such as incomplete consistency of line impedance among the inverters, voltage and current sampling errors and the like, and the output power is unequal. In the no-load parallel operation scenario, especially when two-stage inverters are used and energy cannot be released to the front-stage DC/DC converter in a reverse direction, all active and reactive circulation flows between the inverters, so that a certain hazard is caused to the system. The circulation can lead the voltage of a DC bus capacitor of an inverter to rise, the rising amplitude is inversely related to the capacitance value of the bus capacitor, the phenomenon is particularly obvious under the condition that the capacitance value of the bus capacitor is smaller, the DC bus overvoltage shutdown of the inverter frequently occurs, and meanwhile, the failure of devices such as the capacitor and the like is easy to be caused.
In the conventional DC bus voltage inhibition method under the no-load parallel connection scene of the grid-structured inverter, although the probability of overvoltage of the DC bus capacitance voltage can be effectively reduced by reducing the output voltage vector difference of the two inverters, the method still has larger bus voltage overvoltage risk and still has low system stability under the scene that the load of the inverter is suddenly unloaded after the capacitance of the DC bus capacitance is further reduced.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to solve the problem that the overvoltage is easy to occur to the DC bus of the grid-structured inverter in the prior art when the grid-structured inverter runs in an idle mode, so as to provide a method, a device, equipment and a medium for inhibiting the overvoltage of the DC bus of the inverter.
In order to achieve the above purpose, the present invention provides the following technical solutions:
in a first aspect, the present invention provides a method for suppressing overvoltage of a dc bus of an inverter, comprising: obtaining an initial voltage angular frequency and an initial voltage amplitude based on power outer loop control; when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than a first threshold voltage, judging whether the active power of the inverter is larger than the reactive power; when the active power is continuously preset for more than the reactive power, compensating and converting the angular frequency of the initial voltage to obtain a phase angle reference value, taking the initial voltage amplitude as a voltage amplitude reference value, and constructing a voltage reference instruction based on the phase angle reference value and the voltage amplitude reference value; based on the voltage reference instruction, the switching sequence of the inverter is obtained by PWM modulation after the control of the voltage current inner loop.
According to the method for suppressing overvoltage of the DC bus of the inverter, when the difference between the real-time voltage of the DC side bus capacitor of the inverter and the rated voltage thereof is larger than the first threshold voltage, the active circulation adjustment or the reactive circulation adjustment is determined by judging the magnitude of the active power and the reactive power, the basic control of no-load circulation is realized by the active reactive competition mechanism, the overvoltage voltage suppression of the DC bus capacitor is completed, the stability of a power supply system under the working conditions of no-load parallel connection, sudden loading and unloading of the inverter is further improved, and the service life of the power supply system is prolonged.
In an alternative embodiment, the method further comprises: when the duration preset time of the reactive power is longer than that of the active power, compensating the initial voltage amplitude to obtain a voltage amplitude reference value, and constructing a voltage reference instruction based on the initial voltage angular frequency and the voltage amplitude reference value; based on the voltage reference instruction, the switching sequence of the inverter is obtained by PWM modulation after the control of the voltage current inner loop.
According to the method for suppressing the overvoltage of the DC bus of the inverter, the active circulation adjustment or the reactive circulation adjustment is respectively carried out according to the active power and the reactive power, the adjustment efficiency is improved through the dynamic switching of the frequency adjustment quantity and the terminal voltage adjustment quantity, and the active circulation and the reactive circulation can be respectively controlled, so that the efficiency and the accuracy for suppressing the overvoltage of the bus are improved.
In an alternative embodiment, the process of obtaining the initial voltage angular frequency includes: calculating according to the initial output voltage, the initial output current and the cosine value of the initial output voltage phase angle of the inverter to obtain the initial active power of the inverter; and calculating a difference value between the active power reference value and the initial active power, and calculating the initial voltage angular frequency by using an active control loop based on the difference value.
In an alternative embodiment, the process of obtaining the initial voltage magnitude includes: calculating according to the initial output voltage, the initial output current and the sine value of the phase angle of the initial output voltage of the inverter to obtain the initial reactive power of the inverter; calculating a difference value between the reactive power reference value and the initial reactive power, and calculating a first voltage adjustment quantity by using a reactive control loop based on the difference value; and obtaining an initial voltage amplitude value based on the first voltage adjustment amount and the reference voltage.
In an alternative embodiment, the process of compensating and converting the angular frequency of the initial voltage to obtain the phase angle reference value includes: according to the difference value between the real-time voltage of the DC side bus capacitor of the inverter and the rated voltage thereof, the angular frequency adjustment quantity is obtained by combining voltage sampling low-pass filtering and the adjustment coefficient calculation of the no-load circulation angular frequency adjustment quantity; and compensating the angular frequency of the initial voltage by using the angular frequency adjustment quantity, and obtaining a phase angle reference value after integrating and trigonometric function transformation of the compensation result.
In an alternative embodiment, the process of obtaining the voltage amplitude reference value after compensating the initial voltage amplitude includes: according to the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage of the direct-current side bus capacitor, the second voltage regulation is calculated by combining the voltage sampling low-pass filtering and the regulation coefficient of the no-load loop current end voltage regulation; and compensating the initial voltage amplitude by using the second voltage regulating quantity to obtain a voltage amplitude reference value.
In an alternative embodiment, the angular frequency adjustment is calculated as:
the calculation formula of the second voltage adjustment amount is as follows:
wherein omega 0 Is the angular frequency adjustment amount; u (U) 0 Is a second voltage adjustment amount; u (U) bus The real-time voltage of the direct-current side bus capacitor; u (U) busref The rated voltage of the direct-current side bus capacitor is used; omega n Cut-off frequency for low-pass filtering of voltage samples; k (K) pω An adjusting coefficient for the no-load circulation angular frequency adjusting quantity; k (K) pU The regulation factor is the regulation quantity of the no-load circulating current end voltage; k (K) en1 K is as follows en2 Are all enabling coefficients.
In an alternative embodiment, the method further comprises: an overvoltage absorption unit connected in parallel with a direct current side of the inverter; when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than the second threshold voltage, controlling the overvoltage absorbing unit to absorb the energy of the direct-current side no-load circulation of the inverter; the first threshold voltage is less than the second threshold voltage.
According to the method for suppressing the overvoltage of the direct-current bus of the inverter, when the circulation regulation fails under the extreme working condition, the overvoltage absorption unit works to absorb the energy of no-load circulation, and the energy is used as redundancy suppression of untimely bus voltage overvoltage suppression response, so that the reliability of the system is improved.
In a second aspect, the present invention provides an apparatus for suppressing overvoltage of a dc bus of an inverter, comprising: the initial parameter acquisition module is used for acquiring initial voltage angular frequency and initial voltage amplitude based on power outer loop control; the comparison module is used for judging whether the active power of the inverter is larger than the reactive power or not when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage of the direct-current side bus capacitor is larger than the first threshold voltage; the compensation module is used for compensating and converting the angular frequency of the initial voltage to obtain a phase angle reference value when the active power lasts for a preset time to be larger than the reactive power, taking the initial voltage amplitude as a voltage amplitude reference value, and constructing a voltage reference instruction based on the phase angle reference value and the voltage amplitude reference value; and the switching sequence adjusting module is used for obtaining the switching sequence of the inverter by PWM modulation after the voltage and current inner loop control based on the voltage reference instruction.
In a third aspect, the present invention provides a computer device comprising: the device comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, so that the method for suppressing the overvoltage of the DC bus of the inverter in the first aspect is executed.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of suppressing overvoltage of an inverter dc bus of the first aspect.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow diagram of a method of suppressing overvoltage on a DC bus of an inverter according to an embodiment of the invention;
fig. 2 is a schematic diagram of a structure in which a plurality of inverters are connected in parallel according to an embodiment of the present invention;
FIG. 3 is a specific flow chart of a power adjustment method according to an embodiment of the invention;
fig. 4 is a schematic diagram of a connection of an overvoltage absorption unit according to an embodiment of the invention;
figure 5 is a flow chart of an active reactive loop current suppression competition mechanism according to an embodiment of the present invention;
FIG. 6 is a waveform diagram of DC bus voltage overvoltage suppression for a grid-tied inverter in accordance with an embodiment of the present invention;
fig. 7 is a block diagram of an apparatus for suppressing overvoltage of a dc bus of an inverter according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The embodiment provides a method for suppressing overvoltage of a dc bus of an inverter, as shown in fig. 1, including:
step S1: and obtaining the initial voltage angular frequency and the initial voltage amplitude based on the power outer loop control.
Specifically, as shown in fig. 2, a plurality of two-stage grid-formed inverters are connected in parallel, and the ac side output of each inverter is directly connected in parallel to the common connection point PCC. Under the condition that the capacitance of the direct current bus capacitor is smaller, the larger bus voltage overvoltage risk exists, so that the bus overvoltage condition needs to be restrained in time.
Referring to FIG. 3, an initial voltage angular frequency ω is obtained * Comprises the following steps:
(1) According to the initial output voltage U of the inverter o Initial output current I o And calculating the cosine value of the initial output voltage phase angle to obtain the initial active power P of the inverter.
(2) Calculating an active power reference value P Ref And the difference value of the initial active power P, and based on the difference value, calculating the initial voltage angular frequency omega by using an active control loop * 。
Specifically, referring to fig. 3, according to the initial output voltage U of the inverter o Initial output current I o Calculating initial active power P, and referencing the active power to the reference value P Ref After comparing with the initial active power P, the calculated result is processed by an active control loop VSG_P of the virtual synchronous machine, and the active control loop VSG_P outputs the initial voltage angular frequency omega * 。
Specifically, the process of obtaining the initial voltage amplitude includes:
(1) According to the initial output voltage U of the inverter o Initial output current I o Sine of initial output voltage phase angleThe value calculation results in an initial reactive power Q of the inverter.
(2) Calculating reactive power reference value Q Ref And calculating the difference value with the initial reactive power Q by using a reactive control loop based on the difference value to obtain a first voltage adjustment quantity delta U.
(3) Based on the first voltage adjustment quantity DeltaU and the reference voltage U ref Obtaining an initial voltage amplitude U Ref 。
Specifically, referring to fig. 3, according to the initial output voltage U of the inverter o Initial output current I o Calculating initial reactive power Q, and comparing the reactive power with reference value Q ref After the comparison with the initial reactive power Q, the calculated result is processed by a reactive control loop VSG_Q of the virtual synchronous machine to obtain a terminal voltage adjustment quantity delta U and a reference voltage U ref Superposition to finally obtain initial voltage amplitude U 1 。
Step S2: when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than a first threshold voltage, judging whether the active power of the inverter is larger than the reactive power.
Specifically, each inverter acquires real-time voltage U of the bus capacitor by sampling respective direct-current bus capacitor voltage in real time bus Calculate the real-time voltage U bus Rated voltage U of direct current bus capacitor busref When the difference is greater than the first threshold voltage U pro1 And when the voltage of the direct current bus capacitor is higher than the voltage of the direct current bus capacitor, the voltage of the direct current bus capacitor is reduced.
Step S3: when the active power is continuously preset for more than the reactive power, compensating and converting the angular frequency of the initial voltage to obtain a phase angle reference value, taking the initial voltage amplitude as a voltage amplitude reference value, and constructing a voltage reference instruction based on the phase angle reference value and the voltage amplitude reference value.
Referring to fig. 3, the process of compensating and converting the initial voltage angular frequency to obtain the phase angle reference value includes:
(1) According to the real-time voltage U of the DC bus capacitor of the inverter bus And rated voltage U busref Is combined with the voltage sampling low-pass filtering and the adjustment coefficient of the no-load loop current angular frequency adjustment quantity to calculate the angular frequency adjustment quantity omega 0 。
(2) And compensating the angular frequency of the initial voltage by using the angular frequency adjustment quantity, and obtaining a phase angle reference value after integrating and trigonometric function transformation of the compensation result.
Specifically, the angular frequency adjustment amount ω 0 The calculation formula of (2) is as follows:
wherein omega 0 Is the angular frequency adjustment amount; u (U) bus The real-time voltage of the direct-current side bus capacitor; u (U) busref The rated voltage of the direct-current side bus capacitor is used; omega n Cut-off frequency for low-pass filtering of voltage samples; k (K) pω An adjusting coefficient for the no-load circulation angular frequency adjusting quantity; k (K) en1 To enable coefficients.
Specifically, in fig. 3, when the active power is continuously preset for a time t greater than the reactive power, K is set en1 =1, the angular frequency is adjusted by an amount ω 0 Angular frequency omega from initial voltage * After superposition, the angle theta is obtained through integration, and then the phase angle reference value sin theta is obtained through sine calculation on the angle theta. Then the initial voltage amplitude U 1 As voltage amplitude reference U Ref And based on the phase angle reference value sin theta and the voltage amplitude reference value U Ref A voltage reference command U is constructed.
Step S4: based on the voltage reference instruction, the switching sequence of the inverter is obtained by PWM modulation after the control of the voltage current inner loop.
Specifically, in fig. 3, after the voltage reference command U is input into the voltage-current inner loop module to perform inner loop control, a PWM modulation signal is output, so that the inverter adjusts the switching sequence based on the PWM modulation signal, thereby adjusting the voltages of the dc side and the ac side, and achieving the effect of suppressing the overvoltage of the dc bus capacitor.
Step S5: when the duration preset time of the reactive power is longer than that of the active power, the initial voltage amplitude is compensated to obtain a voltage amplitude reference value, and a voltage reference instruction is constructed based on the initial voltage angular frequency and the voltage amplitude reference value.
Referring to fig. 3, a process of obtaining a voltage amplitude reference value after compensating an initial voltage amplitude includes:
(1) According to the real-time voltage U of the DC bus capacitor of the inverter bus And rated voltage U busref The second voltage regulating quantity U is obtained by combining the voltage sampling low-pass filtering and the regulating coefficient calculation of the no-load loop current end voltage regulating quantity 0 。
(2) By means of a second voltage regulation U 0 For initial voltage amplitude U 1 The voltage amplitude reference value U is obtained after compensation Ref 。
Specifically, the calculation formula of the second voltage adjustment amount is:
wherein U is 0 Is a second voltage adjustment amount; u (U) bus The real-time voltage of the direct-current side bus capacitor; u (U) busref The rated voltage of the direct-current side bus capacitor is used; omega n Cut-off frequency for low-pass filtering of voltage samples; k (K) pU The regulation factor is the regulation quantity of the no-load circulating current end voltage; k (K) en2 To enable coefficients.
Specifically, in fig. 3, when the reactive power continues for a preset time t to be greater than the active power, K is set en2 =1, the second voltage adjustment amount U 0 And the initial voltage amplitude U 1 The voltage amplitude reference value U is obtained after superposition Ref . Then the voltage amplitude reference value U Ref And after being overlapped with the phase angle reference value sin theta, the voltage reference command U is constructed.
Step S6: based on the voltage reference instruction, the switching sequence of the inverter is obtained by PWM modulation after the control of the voltage current inner loop.
Specifically, in fig. 3, after the voltage reference command U is input into the voltage-current inner loop module to perform inner loop control, a PWM modulation signal is output, so that the inverter adjusts the switching sequence based on the PWM modulation signal, thereby adjusting the voltages of the dc side and the ac side, and achieving the effect of suppressing the overvoltage of the dc bus capacitor.
According to the method for suppressing overvoltage of the direct-current bus of the inverter, when the difference between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than the first threshold voltage, the active circulation adjustment or the reactive circulation adjustment is determined by judging the size of active power and reactive power, the basic control of no-load circulation is realized by an active reactive competition mechanism, the overvoltage voltage suppression of the direct-current bus capacitor is completed, the stability of a power supply system under the working conditions of no-load parallel connection, sudden loading and unloading with load and the like of the inverter can be further improved, and the service life of the power supply system is prolonged.
In some alternative embodiments, further comprising: an overvoltage absorption unit connected in parallel with a direct current side of the inverter; when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than the second threshold voltage, controlling the overvoltage absorbing unit to absorb the energy of the direct-current side no-load circulation of the inverter; the first threshold voltage is less than the second threshold voltage.
For example, referring to fig. 4, the above-mentioned suppression of the overvoltage of the dc bus capacitor by the loop regulation still has a failure risk under certain extreme working conditions, for example, the input end of the two-stage inverter is connected to a photovoltaic panel, when the photovoltaic panel is at high voltage, the voltage of the dc bus capacitor is at a higher value in a steady state, and compared with the voltage of the bus under the low-voltage working condition of the photovoltaic panel and closer to a hardware voltage protection point, the suppression response of the overvoltage of the bus is not timely, resulting in the overvoltage shutdown of the inverter and system breakdown. Therefore, as shown in fig. 4, the method of absorbing the energy of no-load circulation by the overvoltage absorbing unit is used as a method of further improving the system stability, and each inverter judges the real-time voltage U of the dc bus capacitor by the dc bus capacitor voltage hardware sampling and comparator circuit bus And rated voltage U busref The difference being greater than a set threshold U pro2 When the overvoltage absorption unit works, the energy of no-load circulation is absorbed by the energy storage capacitor C in the overvoltage absorption unit s To be absorbed. The active and reactive bus overvoltage suppression scheme can realize circulation control under most conditions, and the overvoltage absorption unit is normally in a non-working state, so that the service life of the energy storage capacitor is indirectly prolonged.
Illustratively, fig. 5 is a flow chart of an active reactive power circulation suppression competition mechanism, and fig. 6 is a waveform of overvoltage suppression of a dc bus voltage of a grid-structured inverter. In fig. 5, when the active power continues to be larger than the reactive power, it is determined that no-load circulation due to the phase angle difference of the inverter, i.e., K is set en1 ＝1、K en2 After=0, loop regulation is started according to step S3 described above based on the active frequency modulation strategy. On the contrary, when the active power is continuously smaller than the reactive power, the no-load circulation caused by the voltage difference of the inverter terminal is judged, namely K is set en1 ＝0、K en2 After=1, the loop current regulation starts according to the above step S5 based on the reactive voltage regulation strategy loop.
The embodiment also provides a device for suppressing overvoltage of the dc bus of the inverter, which is used for implementing the foregoing embodiment and any optional implementation manner, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a device for suppressing overvoltage of dc bus of inverter, as shown in fig. 7, including:
the initial parameter obtaining module 701 is configured to obtain an initial voltage angular frequency and an initial voltage amplitude based on power outer loop control.
And the comparison module 702 is configured to determine whether the active power of the inverter is greater than the reactive power when the real-time voltage of the dc-side bus capacitor of the inverter and the difference between the rated voltage thereof are greater than a first threshold voltage.
And the compensation module 703 is configured to compensate and convert the angular frequency of the initial voltage to obtain a phase angle reference value when the active power lasts for a preset time to be greater than the reactive power, take the initial voltage amplitude as a voltage amplitude reference value, and construct a voltage reference command based on the phase angle reference value and the voltage amplitude reference value.
The switching sequence adjusting module 704 is configured to obtain a switching sequence of the inverter by performing PWM modulation after performing voltage-current inner loop control based on the voltage reference command.
The hardware-based logic mapping device in this embodiment is presented in the form of functional units, where the units refer to ASIC circuits, processors and memories executing one or more software or firmware programs, and/or other devices that can provide the functionality described above.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The embodiment of the invention also provides computer equipment, which is provided with the device for suppressing the overvoltage of the DC bus of the inverter shown in the figure 7.
As shown in fig. 8, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 8.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (11)
1. A method of suppressing overvoltage of a dc bus of an inverter, comprising:
obtaining an initial voltage angular frequency and an initial voltage amplitude based on power outer loop control;
when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than a first threshold voltage, judging whether the active power of the inverter is larger than the reactive power;
when the active power is continuously preset for a time longer than the reactive power, compensating and converting the initial voltage angular frequency to obtain a phase angle reference value, taking the initial voltage amplitude as a voltage amplitude reference value, and constructing a voltage reference instruction based on the phase angle reference value and the voltage amplitude reference value;
and based on the voltage reference instruction, performing PWM modulation after voltage and current inner loop control to obtain a switching sequence of the inverter.
2. The method of suppressing overvoltage of an inverter dc bus according to claim 1, further comprising:
when the duration preset time of the reactive power is longer than the active power, compensating the initial voltage amplitude to obtain a voltage amplitude reference value, and constructing a voltage reference instruction based on the initial voltage angular frequency and the voltage amplitude reference value;
and based on the voltage reference instruction, performing PWM modulation after voltage and current inner loop control to obtain a switching sequence of the inverter.
3. The method of suppressing overvoltage of dc bus of an inverter according to claim 2, wherein the process of obtaining the initial voltage angular frequency comprises:
calculating according to the initial output voltage, the initial output current and the cosine value of the initial output voltage phase angle of the inverter to obtain the initial active power of the inverter;
and calculating a difference value between the active power reference value and the initial active power, and calculating the initial voltage angular frequency by using an active control loop based on the difference value.
4. A method of suppressing overvoltage on a dc bus of an inverter as claimed in claim 3, wherein the process of obtaining the initial voltage magnitude comprises:
calculating to obtain the initial reactive power of the inverter according to the sine values of the initial output voltage, the initial output current and the initial output voltage phase angle of the inverter;
calculating a difference value between a reactive power reference value and the initial reactive power, and calculating a first voltage adjustment quantity by using a reactive power control loop based on the difference value;
and obtaining the initial voltage amplitude based on the first voltage adjustment amount and the reference voltage.
5. The method of suppressing overvoltage of dc bus of an inverter according to claim 1, wherein the process of obtaining the phase angle reference value after compensating and converting the initial voltage angular frequency includes:
according to the difference value between the real-time voltage of the DC side bus capacitor of the inverter and the rated voltage of the DC side bus capacitor, the angular frequency adjustment quantity is obtained by combining voltage sampling low-pass filtering and the adjustment coefficient calculation of the no-load circulation angular frequency adjustment quantity;
and compensating the angular frequency of the initial voltage by using the angular frequency adjustment quantity, and obtaining a phase angle reference value after integrating and trigonometric function transformation of a compensation result.
6. The method for suppressing overvoltage of dc bus of inverter according to claim 2, wherein the process of obtaining the voltage amplitude reference value after compensating the initial voltage amplitude comprises:
according to the difference value between the real-time voltage of the DC side bus capacitor of the inverter and the rated voltage of the DC side bus capacitor, a second voltage regulating quantity is obtained by combining voltage sampling low-pass filtering and the regulating coefficient of the no-load circulating current end voltage regulating quantity;
and compensating the initial voltage amplitude by using the second voltage regulating quantity to obtain a voltage amplitude reference value.
7. The method according to claim 5 or 6, wherein,
the calculation formula of the angular frequency adjustment quantity is as follows:
the calculation formula of the second voltage adjustment amount is as follows:
wherein omega 0 Is the angular frequency adjustment amount; u (U) 0 Is a second voltage adjustment amount; u (U) bus The real-time voltage of the direct-current side bus capacitor; u (U) busref The rated voltage of the direct-current side bus capacitor is used; omega n Cut-off frequency for low-pass filtering of voltage samples; k (K) pω An adjusting coefficient for the no-load circulation angular frequency adjusting quantity; k (K) pU The regulation factor is the regulation quantity of the no-load circulating current end voltage; k (K) en1 K is as follows en2 Are all enabling coefficients.
8. The method of suppressing overvoltage of an inverter dc bus according to claim 1, further comprising:
an overvoltage absorption unit connected in parallel with a direct current side of the inverter;
when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage thereof is larger than a second threshold voltage, controlling the overvoltage absorption unit to absorb the energy of the direct-current side no-load circulation of the inverter;
the first threshold voltage is less than the second threshold voltage.
9. A device for suppressing overvoltage of a dc bus of an inverter, comprising:
the initial parameter acquisition module is used for acquiring initial voltage angular frequency and initial voltage amplitude based on power outer loop control;
the comparison module is used for judging whether the active power of the inverter is larger than the reactive power or not when the difference value between the real-time voltage of the direct-current side bus capacitor of the inverter and the rated voltage of the direct-current side bus capacitor is larger than a first threshold voltage;
the compensation module is used for compensating and converting the initial voltage angular frequency to obtain a phase angle reference value when the active power lasts for a preset time to be larger than the reactive power, taking the initial voltage amplitude as a voltage amplitude reference value, and constructing a voltage reference instruction based on the phase angle reference value and the voltage amplitude reference value;
and the switching sequence adjusting module is used for obtaining the switching sequence of the inverter by PWM modulation after the voltage and current inner loop control based on the voltage reference instruction.
10. A computer device, comprising:
a memory and a processor communicatively coupled to each other, the memory having stored therein computer instructions that, when executed, perform the method of suppressing overvoltage of an inverter dc bus as defined in any one of claims 1 to 7.
11. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of suppressing overvoltage of an inverter dc bus as defined in any one of claims 1 to 7.
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| CN202410164355.8A CN117748627A (en) | 2024-02-05 | 2024-02-05 | Method, device, equipment and medium for inhibiting overvoltage of direct current bus of inverter |
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