CN117747678A - Ultrathin tunneling oxidation passivation contact solar cell and manufacturing method thereof - Google Patents
Ultrathin tunneling oxidation passivation contact solar cell and manufacturing method thereof Download PDFInfo
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Abstract
The application discloses ultra-thin tunneling oxidation passivation contact solar cell and preparation method thereof is provided with ultra-thin tunneling oxide layer and doped polycrystalline silicon layer at the back of semiconductor substrate, can realize the ultra-thin tunneling oxidation passivation contact at back, is provided with bottom electrode contact layer between bottom electrode and doped polycrystalline silicon layer, and bottom electrode contact layer includes: the metal material of the bottom electrode is prevented from burning through the ultrathin tunneling oxide layer, the problem of poor contact effect of ultrathin tunneling oxidation passivation caused by the burning through of the ultrathin tunneling oxide layer can be avoided, the contact effect of ultrathin tunneling oxidation passivation is improved, the metal material of the bottom electrode is prevented from directly contacting with a semiconductor substrate, metal contact recombination is reduced, parasitic absorption is reduced, and photoelectric conversion efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of solar cells, and more particularly, to an ultrathin tunneling oxide passivation contact (Thin Oxide Passivated Contact, abbreviated as TOPCon) solar cell and a method for fabricating the same.
Background
The growing tension of fossil energy has serious influence on the sustainable development of economy and the health of human environment, the ecological environment is destroyed and the traditional energy is exhausted, so that people need a clean, pollution-free and sustainable green energy, and solar energy is particularly important as a clean energy with the most potential for continuous development.
Solar cells are currently one of the main ways people use solar energy. The back of the TOPCon solar cell adopts an ultrathin oxide layer and a polysilicon layer to realize ultrathin tunneling oxidation passivation contact, so that not only can a good back passivation effect be realized, but also quantum tunneling effect can be utilized, multi-tunneling is allowed, minority carriers are blocked from penetrating, selective carrier collection is realized, photoelectric conversion efficiency is improved, and the TOPCon solar cell has better compatibility with the existing emitter back passivation (Passivated Emitterand Rear Cell, PERC for short) cell technology.
In the existing TOPCON solar cell, the problem of poor contact effect of ultra-thin tunneling oxidation passivation exists, and the problem of larger parasitic absorption is solved, so that the photoelectric conversion efficiency is affected.
Disclosure of Invention
In view of the above, the present application provides an ultrathin tunneling oxidation passivation contact solar cell and a method for manufacturing the same, and the method comprises the following steps:
a TOPCon solar cell comprising:
a semiconductor substrate having a front surface and a back surface disposed opposite to each other; the back surface is provided with a metal grid line area and nonmetal grid line areas positioned at two sides of the metal grid line area;
an ultrathin tunneling oxide layer covering the back surface;
a doped polysilicon layer covering the ultra-thin tunneling oxide layer;
the patterned bottom electrode contact layer is positioned on the surface of one side of the doped polysilicon layer, which is away from the ultrathin tunneling oxide layer, and is positioned in the metal gate line region;
the bottom electrode is positioned on one side surface of the bottom electrode contact layer, which is away from the doped polysilicon layer;
wherein the bottom electrode contact layer comprises: the ultra-thin oxide layer is positioned on the surface of the doped polycrystalline silicon layer, and the doped polycrystalline silicon carbide layer is positioned on the surface of the ultra-thin oxide layer, and is used for controlling the metallization depth of the bottom electrode in the sintering process of the bottom electrode, so that ohmic contact is formed between the bottom electrode and the doped polycrystalline silicon layer, and the metallization range is not more than that of the doped polycrystalline silicon layer.
Preferably, in the TOPCon solar cell, the thickness of the doped polysilicon layer is in the range of 10nm to 40nm.
Preferably, in the TOPCon solar cell, the doped polycrystalline silicon carbide layer has a thickness in the range of 40nm to 140nm.
Preferably, in the TOPCon solar cell, the distance between two adjacent bottom electrodes is in the range of 0.85mm to 0.95mm.
Preferably, the TOPCon solar cell further includes:
the silicon nitride passivation layer is positioned on one side surface of the doped polysilicon layer, which is far away from the ultrathin tunneling oxide layer, and the silicon nitride passivation layer is positioned in the nonmetal grid line area and exposes the bottom electrode contact layer.
The application also provides a manufacturing method of the TOPCON solar cell, which comprises the following steps:
providing a semiconductor substrate having a front surface and a back surface disposed opposite to each other; the back surface is provided with a metal grid line area and nonmetal grid line areas positioned at two sides of the metal grid line area;
forming an ultrathin tunneling oxide layer covering the back surface;
forming a doped polysilicon layer and a bottom electrode contact layer, wherein the doped polysilicon layer covers the polysilicon layer of the ultrathin tunneling oxide layer; a patterned bottom electrode contact layer is formed on the surface of one side of the doped polysilicon layer, which is away from the ultrathin tunneling oxide layer, and the bottom electrode contact layer is positioned in the metal gate line region;
forming a bottom electrode on the surface of one side of the bottom electrode contact layer, which is away from the doped polysilicon layer;
wherein the bottom electrode contact layer comprises: the ultra-thin oxide layer is positioned on the surface of the doped polycrystalline silicon layer, and the doped polycrystalline silicon carbide layer is positioned on the surface of the ultra-thin oxide layer, and is used for controlling the metallization depth of the bottom electrode in the sintering process of the bottom electrode, so that ohmic contact is formed between the bottom electrode and the doped polycrystalline silicon layer, and the metallization range is not more than that of the doped polycrystalline silicon layer.
Preferably, in the above manufacturing method, an ultrathin tunneling oxide layer, a doped amorphous silicon layer, an unpatterned bottom electrode contact layer and an unpatterned mask layer are sequentially formed on the back surface by using the same PECVD device;
the doped amorphous silicon layer is used for forming a doped polycrystalline silicon layer based on an annealing process; and after patterning the bottom electrode contact layer based on the mask layer, removing the mask layer.
Preferably, in the above manufacturing method, the thickness of the doped polysilicon layer is in the range of 10nm to 40nm.
Preferably, in the above manufacturing method, the thickness of the doped polycrystalline silicon carbide layer ranges from 40nm to 140nm;
and/or the distance between two adjacent bottom electrodes is in the range of 0.85 mm-0.95 mm.
Preferably, in the above manufacturing method, the method for forming the doped polysilicon layer and the bottom electrode contact layer includes:
forming a doped amorphous silicon layer on the surface of the ultrathin tunneling oxide layer;
sequentially forming an unpatterned ultrathin oxide layer and a doped amorphous silicon carbide layer on the surface of the doped amorphous silicon layer;
forming a mask layer on the surface of one side of the doped amorphous silicon carbide layer, which is far away from the ultrathin oxide layer, and then annealing the mask layer to convert the doped amorphous silicon carbide layer into a doped polysilicon layer and convert the doped amorphous silicon carbide layer into a doped polysilicon layer;
patterning the mask layer, wherein the patterned mask layer covers the doped polycrystalline silicon carbide layer positioned on the metal grid line, and the doped polycrystalline silicon carbide layer positioned in the non-metal grid line area is exposed;
etching to remove the doped polycrystalline silicon carbide layer positioned in the non-metal gate line region based on the patterned mask layer;
synchronously removing the ultrathin oxide layer and the mask layer which are positioned in the nonmetal grid line region; wherein, the material of ultra-thin oxide layer is the same with the material of mask layer.
As can be seen from the above description, in the ultrathin tunneling oxide passivation contact solar cell and the manufacturing method thereof provided in the technical scheme of the present application, an ultrathin tunneling oxide layer and a doped polysilicon layer are disposed on the back surface of a semiconductor substrate, so that the ultrathin tunneling oxide passivation contact on the back surface can be realized, and a bottom electrode contact layer is disposed between a bottom electrode and the doped polysilicon layer, wherein the bottom electrode contact layer includes: the metal material of the bottom electrode is prevented from burning through the ultra-thin tunneling oxide layer, the problem of poor contact effect of ultra-thin tunneling oxidation passivation caused by the burning through of the ultra-thin tunneling oxide layer is avoided, the contact effect of ultra-thin tunneling oxidation passivation is improved, the metal material of the bottom electrode is prevented from directly contacting with a semiconductor substrate, metal contact recombination is reduced, parasitic absorption is reduced, and photoelectric conversion efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the provided drawings without inventive effort to those skilled in the art.
The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and should not be construed as limiting the scope of the invention, since any structural modifications, proportional changes, or dimensional adjustments, which may be made by those skilled in the art, should not be construed as limiting the scope of the invention without affecting the efficacy or the achievement of the objective of the invention.
Fig. 1 is a cut-away view of a TOPCon solar cell according to an embodiment of the present disclosure;
fig. 2 is a cross-sectional view of another TOPCon solar cell according to an embodiment of the present disclosure;
fig. 3 is a cross-sectional view of a TOPCon solar cell according to an embodiment of the present disclosure;
fig. 4 to fig. 13 are schematic structural diagrams of a method for manufacturing a TOPCon solar cell according to an embodiment of the present disclosure in different process steps.
Description of the drawings:
10-a semiconductor substrate; 11-an ultra-thin tunneling oxide layer; a 12-polysilicon doped layer; 13-a bottom electrode contact layer; 14-a bottom electrode; 131-an ultra-thin oxide layer; 132-a doped polycrystalline silicon carbide layer; 15-a silicon nitride passivation layer; 21-a diffusion layer; 22-front passivation structure; 23-top electrode; a 12' -doped amorphous silicon layer; a 132' -doped amorphous silicon carbide layer; 16-mask layer.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which it is shown, and in which it is evident that the embodiments described are exemplary only some, and not all embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, this application is intended to cover such modifications and variations of this application as fall within the scope of the appended claims (the claims) and their equivalents. The embodiments provided in the examples of the present application may be combined with each other without contradiction.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
Referring to fig. 1, fig. 1 is a cut-out view of a TOPCon solar cell according to an embodiment of the present application, where the TOPCon solar cell includes:
a semiconductor substrate 10, the semiconductor substrate 10 having a front surface and a back surface disposed opposite to each other; the back surface is provided with a metal grid line area and nonmetal grid line areas positioned at two sides of the metal grid line area
An ultra-thin tunnel oxide layer 11 covering the back surface;
a doped polysilicon layer 12 covering the ultra-thin tunnel oxide layer 11;
the patterned bottom electrode contact layer 13, the bottom electrode contact layer 13 is positioned on one side surface of the doped polysilicon layer 12, which is away from the ultrathin tunneling oxide layer 11, and is positioned in the metal gate line region;
a bottom electrode 14 located on a side surface of the bottom electrode contact layer 13 facing away from the doped polysilicon layer 12;
wherein the bottom electrode contact layer 13 includes: the ultra-thin oxide layer 131 positioned on the surface 12 of the doped polysilicon layer and the doped polysilicon layer 132 positioned on the surface 131 of the ultra-thin oxide layer are used for controlling the metallization depth of the bottom electrode 14 in the sintering process of the bottom electrode 14, so that the bottom electrode 14 and the doped polysilicon layer 12 form ohmic contact, the metallization range is not more than that of the doped polysilicon layer 12, and the ultra-thin tunneling oxide layer 11 between the doped polysilicon layer 12 and the semiconductor substrate 10 is prevented from being damaged, so that good ultra-thin tunneling oxide passivation contact is ensured.
TOPCon passivation structure can be realized on the back surface of the semiconductor substrate 10 through the ultra-thin tunneling oxide layer 11 and the doped polysilicon layer 12, and the battery passivation effect is improved.
In the TOPCon solar cell provided by the embodiment of the application, the bottom electrode contact layer 13 is provided with the doped polycrystalline silicon carbide layer 132, and the doped polycrystalline silicon carbide layer 132 can control the metallization depth of the bottom electrode 14 in the sintering process of the bottom electrode 14, so that ohmic contact is formed between the bottom electrode 14 and the doped polycrystalline silicon layer 12, and the metallization range does not exceed that of the doped polycrystalline silicon layer 12, thereby avoiding that the metal material of the bottom electrode 14 burns through the ultrathin tunneling oxide layer 11 after sintering, avoiding the poor effect of the ultrathin tunneling oxidation passivation contact caused by the problem, improving the effect of the ultrathin tunneling oxidation passivation contact, avoiding that the metal material of the bottom electrode 14 is directly contacted with the semiconductor substrate 10, reducing metal contact recombination, further reducing parasitic absorption and improving the photoelectric conversion efficiency.
Alternatively, the semiconductor substrate 10 is an N-type doped silicon substrate. The ultra-thin tunnel oxide layer 11 is a silicon oxide layer. The doped polysilicon layer 12 may be phosphorus doped polysilicon. The ultra-thin oxide layer 131 is a silicon oxide layer. Doped polysilicon carbide layer 132 is a phosphorus doped polysilicon carbide layer.
In conventional TOPCO solar cells, the doped polysilicon layer 12 typically has a thickness in the range of about 120nm, a relatively large thickness, and a cell shorting current density gain of about 0.2-0.4 mA/cm 2 The battery short circuit current density gain is small. Although the short-circuit current density gain of the battery can be improved by reducing the thickness of the doped polysilicon layer 12, the lateral transmission performance of carriers in the doped polysilicon layer 12 is weakened, and after electrode sintering, the problem that the metal material in the bottom electrode 14 burns through the ultrathin tunneling oxide layer 11 is more likely to occur due to the reduction of the thickness of the doped polysilicon layer 12And the photoelectric conversion efficiency is improved.
In the TOPCon solar cell provided in the embodiment of the present application, the doped polysilicon layer 12 with a smaller thickness may be used. Although the thickness of the doped polysilicon layer 12 is thinner, the problem that the metal material burns through the ultra-thin tunneling oxide layer 11 due to the reduced thickness of the doped polysilicon layer 12 can be solved by the doped polysilicon layer 132, and the problem that the lateral transport performance of carriers in the doped polysilicon layer 12 is weakened due to the reduced thickness of the doped polysilicon layer 12 can be overcome by reducing the distance between the bottom electrodes 14. Thus, the loss of the filling factor can be reduced to be within 0.3% of the absolute value while the short-circuit current density gain of the battery is improved, and the final photoelectric conversion efficiency of the battery has the absolute gain of more than 0.1%.
Based on the above description, in the embodiment of the present application, the thickness of the doped polysilicon layer 12 can be reduced from 120nm to not more than 40nm, for example, the thickness of the doped polysilicon layer 12 can be set to be in the range of 10nm to 40nm, compared to the conventional TOPCon solar cell. Due to the great reduction of the thickness of the doped polysilicon layer 12, the short-circuit current density gain of the battery can be effectively improved.
Optionally, the doped polysilicon carbide layer 132 is provided in a thickness range of 40nm to 140nm. When the thickness of the doped polysilicon layer 132 is in the range of 40nm to 140nm, the thickness of the doped polysilicon layer 12 can be made not to exceed 40nm, and the problem that the metal material burns through the ultra-thin tunneling oxide layer 11 due to the reduced thickness of the doped polysilicon layer 12 can be effectively solved.
Alternatively, based on the doped polysilicon layer 132 with a certain thickness, the electrode contact portion formed by sintering the bottom electrode 14 may be located on the side of the ultrathin oxide layer 131 away from the back surface of the semiconductor substrate 10, i.e., the bottom electrode 14 does not pass through the ultrathin oxide layer 131. This is because the heterojunction structure formed between the doped polysilicon layer 12 and the doped polysilicon carbide layer 132 can promote the separation and migration of photo-generated carriers, however, good surface passivation is required between different semiconductors to reduce interface defects, and the ultra-thin oxide layer 131 can well passivate the surfaces of the doped polysilicon layer 12 and the doped polysilicon carbide layer 132, and electron tunneling can be caused due to the extremely thin thickness, so that carriers are further separated, and recombination is reduced.
In some implementations of the examples herein, the spacing between adjacent bottom electrodes 14 is provided in the range of 0.85mm to 0.95mm. When the interval between two adjacent bottom electrodes 14 is 0.85 mm-0.95 mm, the thickness of the doped polysilicon layer 12 can be kept not more than 40nm, and the problem that the transverse transmission performance of carriers in the doped polysilicon layer 12 is weakened due to the reduction of the thickness of the doped polysilicon layer 12 can be effectively solved. In the embodiment of the application, the thickness range of the doped polysilicon layer 132 is 40 nm-140 nm, and the interval range between two adjacent bottom electrodes 14 is 0.85 mm-0.95 mm, so that the thickness of the doped polysilicon layer 12 can be greatly reduced, and the thickness of the doped polysilicon layer 12 can be not more than 30nm. The doped polysilicon layer 12 with the thickness ranging from 20nm to 30nm can be adopted, so that the problem that the metal material burns through the ultrathin tunneling oxide layer 11 due to the reduced thickness of the doped polysilicon layer 12 is solved, and meanwhile, the problem that the transverse transmission performance of carriers in the doped polysilicon layer 12 is weakened due to the reduced thickness of the doped polysilicon layer 12 is solved.
Referring to fig. 2, fig. 2 is a cross-sectional view of another TOPCon solar cell provided in the embodiment of the present application, where, based on the foregoing embodiment, the TOPCon solar cell shown in fig. 2 further includes: the silicon nitride passivation layer 15 is positioned on one side surface of the doped polysilicon layer 12, which is away from the ultrathin tunneling oxide layer 11, and the silicon nitride passivation layer 15 is positioned in the nonmetal grid line region and exposes the bottom electrode contact layer 13.
In the mode shown in fig. 5, not only the TOPCon passivation structure formed by the ultrathin tunneling oxide layer 11 and the doped polysilicon layer 12 is provided on the back surface of the battery, but also a silicon nitride passivation layer 15 is provided, so that the passivation effect of the back surface of the battery is improved. The silicon nitride passivation layer 15 has better chemical stability, and can also avoid the damage of the metal material of the bottom electrode 14 to other film layers in the non-metal gate line region in the subsequent electrode sintering process. But the silicon nitride passivation layer 15 can also enhance the anti-reflection effect.
Referring to fig. 3, fig. 3 is a cross-sectional view of a TOPCon solar cell according to an embodiment of the present application, where, in the TOPCon solar cell shown in fig. 3, a diffusion layer 21 is disposed on a front surface of a semiconductor substrate 10, a front passivation structure 22 is covered on a surface of the diffusion layer 21, and a top electrode 23 is disposed on a surface of the front passivation structure 22.
When an N-type doped silicon substrate is used, the diffusion layer 21 may be a P-type doped diffusion layer.
After the top electrode 23 and the bottom electrode 14 are formed by a screen printing process using the conductive paste, good ohmic contact of the top electrode 23 with the diffusion layer 21 and good ohmic contact of the bottom electrode 14 with the doped polysilicon layer 12 are achieved by a sintering process. Through sintering treatment, the metal material in the electrode and the silicon material in the lower film layer can reach the eutectic temperature of the material under the heating effect to form an alloy system, and when the temperature is reduced to a certain range, silicon atoms in the alloy system can be recrystallized to form good ohmic contact.
Based on the TOPCon solar cell provided in the above embodiment, another embodiment of the present application further provides a method for manufacturing the TOPCon solar cell.
Referring to fig. 4 to fig. 12, fig. 4 to fig. 12 are schematic structural diagrams of a method for manufacturing a TOPCon solar cell according to an embodiment of the present application in different process steps, where the manufacturing method includes:
step S11: as shown in fig. 4, a semiconductor substrate 10 is provided.
Wherein a semiconductor substrate 10 is provided having oppositely disposed front and back surfaces; the back surface is provided with a metal grid line area and nonmetal grid line areas positioned at two sides of the metal grid line area.
Step S12: as shown in fig. 5, an ultra-thin tunnel oxide layer 11 is formed covering the back surface.
PECVD process can be adopted, N is utilized 2 O ionizes and forms an ultra-thin tunnel oxide layer 11 on the back side of the semiconductor substrate 10. Alternatively, the thickness of the ultra-thin tunnel oxide layer 11 may range from 0.8nm to 2nm.
Step S13: as shown in fig. 6 to 13, a doped polysilicon layer 12 and a bottom electrode contact layer 13 are formed.
The doped polysilicon layer 12 covers the ultra-thin tunneling oxide layer 11, a patterned bottom electrode contact layer 13 is formed on a surface of one side of the doped polysilicon layer 12 facing away from the ultra-thin tunneling oxide layer 11, and the bottom electrode contact layer 13 is located in the metal gate line region.
In this step, the method of forming the doped polysilicon layer 12 and the bottom electrode contact layer 13 includes: as shown in fig. 6, a doped amorphous silicon layer 12' is formed on the surface of the ultra-thin tunneling oxide layer 11; as shown in fig. 7 and 8, an unpatterned ultra-thin oxide layer 131 and a doped amorphous silicon carbide layer 132 'are sequentially formed on the surface of the doped amorphous silicon layer 12'; after forming the mask layer 16 on the surface of the side of the doped amorphous silicon carbide layer 132' facing away from the ultra-thin oxide layer 131, as shown in fig. 9, annealing is performed to convert the doped amorphous silicon layer 12' into the doped polysilicon layer 12 and convert the doped amorphous silicon carbide layer 132' into the doped polysilicon layer 12, as shown in fig. 10; as shown in fig. 11, the mask layer 16 is patterned, and the patterned mask layer 16 covers the doped polysilicon carbide layer 132 located in the metal gate line, and exposes the doped polysilicon carbide layer 132 located in the non-metal gate line region; as shown in fig. 12, the doped polysilicon carbide layer 132 in the non-metal gate line region is etched away based on the patterned mask layer 16; as shown in fig. 13, the ultra-thin oxide layer 131 and the mask layer 16 in the non-metal gate line region are removed simultaneously; the ultrathin oxide layer 131 is the same as the mask layer 16.
PECVD process can be used to utilize SiH 4 And pH of 3 A layer of phosphorus-containing doped amorphous silicon layer 12' is deposited by ionization to facilitate subsequent annealing to form the doped polysilicon layer 12. Alternatively, the thickness of the doped amorphous silicon layer 12' may range from 10nm to 40nm, and the thickness of the corresponding doped polysilicon layer 12 may range from 10nm to 40nm.
Step S14: a bottom electrode 14 is formed on a surface of the bottom electrode contact layer 13 facing away from the polysilicon layer 12, forming a cell structure as shown in fig. 1.
The manufacturing method shown in fig. 4 to 13 is illustrated by taking the battery structure shown in fig. 1 as an example, and the manufacturing method of the front structure of the conventional TOPCon solar cell can be referred to for the whole structure of the battery, which is not repeated in the embodiments of the present application.
Wherein the bottom electrode contact layer 13 includes: the ultra-thin oxide layer 131 positioned on the surface of the doped polysilicon layer 12 and the doped polysilicon layer 132 positioned on the surface of the ultra-thin oxide layer 131 are used for controlling the metallization depth of the bottom electrode 14 in the sintering process of the bottom electrode 14, so that the bottom electrode 14 and the doped polysilicon layer 12 form ohmic contact, and the metallization range is not more than that of the doped polysilicon layer 12.
In step S13, the method of forming the bottom electrode contact layer 13 includes:
step S141: as shown in fig. 7, an unpatterned ultra-thin oxide layer 131 is formed. PECVD process can be adopted, N is utilized 2 O ionizes, forming an ultra-thin oxide layer 131 on the surface of the doped amorphous silicon layer 12'. Optionally, the thickness of the ultra-thin oxide layer 131 ranges from 0.8nm to 2nm.
Step S142: as shown in fig. 8, an unpatterned doped amorphous silicon carbide layer 132' is formed. PECVD process can be used to utilize SiH 4 、CO 2 And pH (potential of Hydrogen) 3 A layer of amorphous silicon carbide containing phosphorus is formed as the doped amorphous silicon carbide layer 132' on the surface of the ultra-thin oxide layer 131 by ionization. Optionally, the thickness of the doped amorphous silicon carbide layer 132' ranges from 40nm to 140nm.
Step S143: as shown in fig. 9, a mask layer 16 is formed overlying the doped amorphous silicon carbide layer 132'. PECVD process can be used to utilize SiH 4 And N 2 O ionizes, forming a layer of silicon oxide on the surface of the doped amorphous silicon carbide layer 132' as a mask layer 16. Alternatively, the thickness of the mask layer 16 may range from 10nm to 30nm.
As shown in fig. 11, after forming the mask layer 16, an annealing process is performed before patterning the mask layer 16, so that the polysilicon layer 12 and the doped amorphous silicon carbide layer 132' are crystallized and the doping is activated, so that the internal doping ions are uniformly doped. The annealing treatment is performed before the patterning treatment is performed on the mask layer 16, so that the annealing temperature of the doped amorphous silicon layer 12 'and the doped amorphous silicon carbide layer 132' can be uniform based on the whole mask layer 16, the crystallization effect of the doped amorphous silicon layer 12 'and the doped amorphous silicon carbide layer 132' is ensured, and the distribution uniformity of internal doped ions is improved, so that the high-quality doped polysilicon layer 12 and the doped polysilicon carbide layer 132 are formed after annealing.
In addition, compared with the method that after the doped amorphous silicon carbide layer 132 'is etched, the patterned doped amorphous silicon carbide layer 132' is formed, and then the doped polycrystalline silicon carbide layer 132 is formed by annealing. This is because the patterned doped amorphous silicon carbide layer 132' has a smaller lateral dimension, if the patterned doped amorphous silicon carbide layer 132 is annealed after patterning, the uniformity of the doping ions in the peripheral edge region and the central region of the formed doped polycrystalline silicon carbide layer 132 will have a larger difference due to the edge effect, and the patterned doped polycrystalline silicon carbide layer 132 is formed after annealing in the present application, even if the uniformity of the doping ions in the peripheral edge region and the central region of the annealed doped polycrystalline silicon carbide layer 132 has a larger difference, the peripheral edge region can be removed after etching the doped polycrystalline silicon carbide layer 132, thereby the distribution of the doping ions in the doped polycrystalline silicon carbide layer 132 has a better uniformity.
Step S144: as shown in fig. 11, mask layer 16 is etched to form the desired pattern structure to facilitate subsequent etching of doped polysilicon carbide layer 132. In this step, the mask layer 16 in the non-metal gate line region may be removed by laser etching, exposing the doped polysilicon carbide layer 132 in the non-metal gate line region, and retaining the mask layer 16 in the metal gate line region to protect the doped polysilicon carbide layer 132 in the metal gate line region.
Step S145: as shown in fig. 12, the doped polysilicon carbide layer 132 is etched based on the etched mask layer 16 to form a patterned doped polysilicon carbide layer 132. A wet etch may be used to remove the doped polysilicon carbide layer 132 not covered by the mask layer 16, leaving the doped polysilicon carbide layer 132 covered by the mask layer 16, thereby forming a formed doped polysilicon carbide layer 132.
Step S146: as shown in fig. 13, the mask layer 16 on the surface of the ultra-thin oxide layer 131 and the doped polysilicon carbide layer 132 in the non-metal gate line region is removed by simultaneous etching. This step not only etches the ultra-thin oxide layer 131 to form a patterned ultra-thin oxide layer 131, but also simultaneously removes the mask layer 16 on the surface of the doped polysilicon carbide layer 132.
The mask layer 16 and the ultra-thin oxide layer 131 are made of the same material so that they can be simultaneously etched and removed, for example, they can be both silicon oxide layers.
In this embodiment, the thickness of the mask layer 16 is greater than that of the ultra-thin oxide layer 131, so that after the doped polysilicon carbide layer 132 is etched based on the mask layer 16, a part of the thickness of the mask layer 16 is consumed, and the mask layer 16 and the ultra-thin oxide layer 131 have the same or similar thickness, so that the mask layer 16 and the ultra-thin oxide layer 131 can be etched and removed better simultaneously.
An ultra-thin tunneling oxide layer 11, a doped amorphous silicon layer 12', an unpatterned bottom electrode contact layer 13, and an unpatterned mask layer 16 may be sequentially formed on the back surface of the semiconductor substrate 10 using the same PECVD apparatus; as described above, after patterning the bottom electrode contact layer 13 based on the mask layer 16, the mask layer 16 is removed.
In the embodiment of the application, other process machines are not required to be replaced, the ultrathin tunneling oxide layer 11, the doped amorphous silicon layer 12', the unpatterned bottom electrode contact layer 13 and the unpatterned mask layer 16 can be sequentially formed in the same PECVD equipment, the manufacturing process is simple, and the manufacturing cost is reduced.
As described above, the thickness of the doped polysilicon layer 12 ranges from 10nm to 40nm. The thickness of the doped polycrystalline silicon carbide layer 132 ranges from 40nm to 140nm; and/or the spacing between adjacent bottom electrodes 14 is in the range of 0.85mm to 0.95mm. The thickness of the doped polysilicon layer 12 can be greatly reduced, the problem that the metal material burns through the ultrathin tunneling oxide layer 11 due to the reduced thickness of the doped polysilicon layer 12 can be effectively solved, and the problem that the transverse transmission performance of carriers in the doped polysilicon layer 12 is weakened due to the reduced thickness of the doped polysilicon layer 12 can be overcome.
In the embodiment of the application, the thickness of the doped polysilicon layer 12 is uniform, and the doped polysilicon layer 12 is not required to be designed differently in thickness in the metal gate line region and the nonmetal gate line region, so that the metal material in the bottom electrode 14 can be prevented from burning through the doped polysilicon layer 12 through the doped polysilicon carbide layer 132.
In the present specification, each embodiment is described in a progressive manner, or a parallel manner, or a combination of progressive and parallel manners, and each embodiment is mainly described as a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
It is noted that in the description of the present application, it is to be understood that the drawings and descriptions of the embodiments are illustrative and not restrictive. Like reference numerals refer to like structures throughout the embodiments of the specification. In addition, the drawings may exaggerate the thicknesses of some layers, films, panels, regions, etc. for understanding and ease of description. It will also be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In addition, "on …" refers to positioning an element on or under another element, but not essentially on the upper side of the other element according to the direction of gravity.
The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like are used for convenience in describing and simplifying the present application based on the orientation or positional relationship shown in the drawings, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present application. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An ultra-thin tunneling oxide passivation contact solar cell, comprising:
a semiconductor substrate having a front surface and a back surface disposed opposite to each other; the back surface is provided with a metal grid line area and nonmetal grid line areas positioned at two sides of the metal grid line area;
an ultra-thin tunneling oxide layer covering the back surface;
a doped polysilicon layer covering the ultra-thin tunneling oxide layer;
the patterned bottom electrode contact layer is positioned on the surface of one side of the doped polysilicon layer, which is away from the ultrathin tunneling oxide layer, and is positioned in the metal gate line region;
the bottom electrode is positioned on one side surface of the bottom electrode contact layer, which is away from the doped polysilicon layer;
wherein the bottom electrode contact layer comprises: the ultra-thin oxide layer is positioned on the surface of the doped polycrystalline silicon layer, and the doped polycrystalline silicon carbide layer is positioned on the surface of the ultra-thin oxide layer, wherein the doped polycrystalline silicon carbide layer is used for controlling the metallization depth of the bottom electrode in the sintering process of the bottom electrode, so that ohmic contact is formed between the bottom electrode and the doped polycrystalline silicon layer, and the metallization range is not more than that of the doped polycrystalline silicon layer.
2. The ultra-thin tunneling oxide passivation contact solar cell of claim 1, wherein the doped polysilicon layer has a thickness ranging from 10nm to 40nm.
3. The ultra-thin tunneling oxide passivation contact solar cell of claim 2, wherein the doped polycrystalline silicon carbide has a thickness ranging from 40nm to 140nm.
4. The ultra-thin tunneling oxide passivation contact solar cell of claim 2, wherein the spacing between adjacent bottom electrodes is in the range of 0.85mm to 0.95mm.
5. The ultra-thin tunneling oxide passivation contact solar cell of any of claims 1-4, further comprising:
the silicon nitride passivation layer is positioned on one side surface of the doped polysilicon layer, which is away from the ultrathin tunneling oxide layer, and the silicon nitride passivation layer is positioned in the nonmetal grid line area and exposes the bottom electrode contact layer.
6. A method of fabricating an ultra-thin tunneling oxide passivation contact solar cell according to any one of claims 1-5, comprising:
providing a semiconductor substrate having a front surface and a back surface disposed opposite to each other; the back surface is provided with a metal grid line area and nonmetal grid line areas positioned at two sides of the metal grid line area;
forming an ultrathin tunneling oxide layer covering the back surface;
forming a doped polysilicon layer and a bottom electrode contact layer, wherein the doped polysilicon layer covers the ultrathin tunneling oxide layer; a patterned bottom electrode contact layer is formed on the surface of one side of the doped polysilicon layer, which is away from the ultrathin tunneling oxide layer, and the bottom electrode contact layer is positioned in the metal gate line region;
forming a bottom electrode on the surface of one side of the bottom electrode contact layer, which is away from the doped polysilicon layer;
wherein the bottom electrode contact layer comprises: the ultra-thin oxide layer is positioned on the surface of the doped polycrystalline silicon layer, and the doped polycrystalline silicon carbide layer is positioned on the surface of the ultra-thin oxide layer, wherein the doped polycrystalline silicon carbide layer is used for controlling the metallization depth of the bottom electrode in the sintering process of the bottom electrode, so that ohmic contact is formed between the bottom electrode and the doped polycrystalline silicon layer, and the metallization range is not more than that of the doped polycrystalline silicon layer.
7. The method of claim 6, wherein the ultra-thin tunneling oxide layer, the doped amorphous silicon layer, the unpatterned bottom electrode contact layer, and the unpatterned mask layer are sequentially formed on the back surface using the same PECVD apparatus;
the doped amorphous silicon layer is used for forming the doped polycrystalline silicon layer based on an annealing process; and removing the mask layer after patterning the bottom electrode contact layer based on the mask layer.
8. The method of claim 6, wherein the doped polysilicon layer has a thickness in the range of 10nm to 40nm.
9. The method of claim 8, wherein the doped polycrystalline silicon carbide has a thickness in the range of 40nm to 140nm;
and/or the distance between two adjacent bottom electrodes is 0.85 mm-0.95 mm.
10. The method of claim 6, wherein forming the doped polysilicon layer and the bottom electrode contact layer comprises:
forming a doped amorphous silicon layer on the surface of the ultrathin tunneling oxide layer;
sequentially forming an unpatterned ultrathin oxide layer and a doped amorphous silicon carbide layer on the surface of the doped amorphous silicon layer;
forming a mask layer on the surface of one side of the doped amorphous silicon carbide layer, which is away from the ultrathin oxide layer, and then annealing the mask layer to convert the doped amorphous silicon carbide layer into a doped polysilicon layer and convert the doped amorphous silicon carbide layer into a doped polysilicon carbide layer;
patterning the mask layer, wherein the patterned mask layer covers the doped polycrystalline silicon carbide layer positioned on the metal gate line and exposes the doped polycrystalline silicon carbide layer positioned on the non-metal gate line region;
etching to remove the doped polycrystalline silicon carbide layer positioned in the nonmetal grid line region based on the patterned mask layer;
synchronously removing the ultrathin oxide layer positioned in the nonmetal grid line region and the mask layer; wherein, the material of ultra-thin oxide layer is the same with the material of mask layer.
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