CN117747543A - Semiconductor manufacturing method and semiconductor structure - Google Patents
Semiconductor manufacturing method and semiconductor structure Download PDFInfo
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- CN117747543A CN117747543A CN202311836598.3A CN202311836598A CN117747543A CN 117747543 A CN117747543 A CN 117747543A CN 202311836598 A CN202311836598 A CN 202311836598A CN 117747543 A CN117747543 A CN 117747543A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910017052 cobalt Inorganic materials 0.000 claims description 12
- 239000010941 cobalt Substances 0.000 claims description 12
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910052712 strontium Inorganic materials 0.000 claims description 6
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 239000011701 zinc Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000012423 maintenance Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 description 6
- 238000005429 filling process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000001179 sorption measurement Methods 0.000 description 6
- 239000011800 void material Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005281 excited state Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
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- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
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- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor manufacturing method and a semiconductor structure, wherein the semiconductor manufacturing method at least comprises the following steps: providing a semiconductor substrate; forming a trench in the semiconductor substrate, the trench being opened from a surface of the semiconductor substrate to an inside; depositing a lining layer on the surface of the semiconductor substrate with the grooves, wherein the lining layer covers the inner surfaces of the grooves, and the lining layer is made of metal or a combination of metal and metal nitride; filling the trench with a hole filling metal so that the trench is filled. The method can realize filling without or with less gaps, and improves the electrical yield and reliability of the semiconductor device.
Description
Technical Field
The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor manufacturing method and a semiconductor structure.
Background
Since the proposal of "moore's law," microelectronic device densities have evolved almost along the predictions of "moore's law. In order to increase circuit density, microelectronic fabrication has evolved from two dimensions to three dimensions. One of the methods is to stack the chips and then package them, thereby producing a three-dimensional circuit packaging technology (3D IC packaging). In the three-dimensional circuit packaging technology, to realize connection between upper and lower layers of a silicon chip, processes of trench opening and metal hole filling are inevitably required for manufacturing interconnection wires, metal contacts and the like.
However, when filling a trench with a large aspect ratio, a Void (Void) is easily formed in the metal filled in the trench due to the fact that the hole is first closed, so that the problem of short circuit failure or reliability reduction of a subsequent metal wire or metal connecting hole is caused, and how to fill the trench without or with a small Void becomes a problem to be solved in the prior art.
Disclosure of Invention
Aiming at least the defects existing in the related art, the application provides a semiconductor manufacturing method and a semiconductor structure, which can realize filling without or with less gaps and improve the filling quality of the grooves.
A first aspect of the present application provides a semiconductor manufacturing method, including at least the steps of:
providing a semiconductor substrate;
forming a trench in the semiconductor substrate, the trench being opened from a surface of the semiconductor substrate to an inside;
depositing a lining layer on the surface of the semiconductor substrate with the grooves, wherein the lining layer covers the inner surfaces of the grooves, and the lining layer is made of metal or a combination of metal and metal nitride;
filling the trench with a hole filling metal so that the trench is filled.
In some embodiments of the first aspect, the liner layer includes a fill portion overlying the inner surface of the trench and an overflow portion overlying the surface of the semiconductor substrate outside the trench, and further includes, prior to filling the trench with a hole-filling metal: and removing the overflow portion of the lining layer.
In some embodiments of the first aspect, the thickness of the backing layer is
In some embodiments of the first aspect, the liner layer includes an underlying nitride layer and a metal layer overlying the nitride layer, the metal layer being titanium, cobalt, tantalum, tungsten, or ruthenium, the nitride layer being a nitride of titanium, cobalt, tantalum, tungsten, or ruthenium.
In some embodiments of the first aspect, before filling the trench with the hole-filling metal, the method further comprises: and (3) introducing a reducing gas into the groove to reduce the lining layer.
In some embodiments of the first aspect, in the step of filling the trench with the hole filling metal, the filling is performed by a deposition process, and the temperature is raised at the same time as or at intervals of the deposition to reflow the hole filling metal.
In some embodiments of the first aspect, the step of filling the trench with a hole-filling metal specifically includes:
depositing hole filling metal into the groove;
heating while depositing to make the hole filling metal reflux;
maintaining the final temperature until the filling is completed.
In some embodiments of the first aspect, the final temperature is 250 ℃ to 500 ℃, the ramp rate is greater than 50 ℃/min, and the maintenance time of the final temperature is 3 to 30min.
In some embodiments of the first aspect, the hole-filling metal is aluminum, copper, nickel, strontium, cobalt, zinc, or an alloy of at least two of aluminum, copper, nickel, strontium, cobalt, zinc.
A second aspect of the present application provides a semiconductor structure manufactured according to the semiconductor manufacturing method of any one of the first aspects.
Compared with the prior art, the invention has the advantages and positive effects that:
(1) According to the semiconductor manufacturing method provided by at least one embodiment of the application, before the groove is metallized, a lining layer is formed in the groove, and the lining layer can increase the adhesion force to hole filling metal in the subsequent hole filling process, so that the hole filling quality of the groove is improved, and defects such as gaps are reduced;
(2) According to the semiconductor manufacturing method provided by at least one embodiment of the application, the overflow part of the lining layer outside the groove is removed, the adsorption force of the outside of the groove to the subsequent hole filling metal is eliminated, the hole filling metal is pulled into the groove, the hole filling capability is formed more easily, and defects such as gaps and the like in the groove after filling are avoided;
(3) According to the semiconductor manufacturing method provided by at least one embodiment of the application, heating treatment is matched in the hole filling process, so that the hole filling metal is subjected to reflow filling, and the hole filling metal is pulled into the groove under the action of the absorption force of the lining layer in the groove, so that the filling without gaps basically is realized;
(4) The semiconductor structure provided by at least one embodiment of the application is provided with the grooves with few gaps or almost no gaps after metallization, is used for realizing interconnection in device packaging, and can improve the electrical yield and reliability of a semiconductor device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a flow chart of one embodiment of a semiconductor manufacturing method provided herein;
fig. 2a to 2e are cross-sectional views illustrating the processing of a semiconductor structure at various steps of a semiconductor manufacturing method according to an embodiment of the present application.
In the figure:
100. a semiconductor substrate; 200. a groove; 300. a backing layer; 301. a filled portion of the liner layer; 302. an overflow portion of the backing layer; 400. and filling the hole with metal.
Detailed Description
The technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the embodiments described herein can be combined with other embodiments without conflict.
A first aspect of embodiments of the present application provides a semiconductor manufacturing method, which may be specifically used to form an interconnection wire, a metal contact, or a metal via filling in a semiconductor manufacturing process. As shown in fig. 1, the semiconductor manufacturing method at least includes the following steps:
s1: providing a semiconductor substrate;
s2: forming a trench in the semiconductor substrate, the trench being opened from a surface of the semiconductor substrate to an inside;
s3: depositing a lining layer on the surface of the semiconductor substrate with the grooves, wherein the lining layer covers the inner surfaces of the grooves, and the lining layer is made of metal or a combination of metal and metal nitride;
s4: filling the trench with a hole filling metal so that the trench is filled.
According to the semiconductor manufacturing method provided by the embodiment of the application, before the groove is metallized, the lining layer is formed in the groove, the lining layer is attached to the bottom and the inner wall of the groove, a wetting effect on hole filling metal can be formed in the subsequent hole filling process, the adhesive force on the hole filling metal is increased, the hole filling quality of the groove is improved, and defects such as gaps are reduced.
It will be appreciated that in the above method, only the steps relevant to the improvement of the present application are shown, and not all the steps, and therefore, the steps may not be seamlessly joined, and other necessary steps may be interposed between the two steps as required.
Hereinafter, each step will be described in detail with reference to cross-sectional views of a semiconductor structure at each stage in a semiconductor manufacturing process.
First, a semiconductor substrate 100 is provided in step S1 for manufacturing a semiconductor device. The semiconductor substrate 100 may be a bulk silicon substrate (bulk substrate), alternatively, may also be a semiconductor-on-insulator (SOI) substrate 100, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor functional devices (not shown) may be formed in the semiconductor substrate 100, and may include transistors (e.g., MOS), diodes, resistors, capacitors, and/or other active or passive semiconductor devices formed by various integrated circuit fabrication processes. Reference is made to the prior art for a specific method of forming functional devices in the semiconductor substrate 100, which is not described in detail in this application.
Referring to fig. 2a, by performing step S2, a trench 200 opened from the surface of the semiconductor substrate 100 to the inside of the semiconductor substrate 100 is formed in the semiconductor substrate 100. The surface of the semiconductor substrate 100 described in this step specifically refers to a surface that needs to be electrically connected. The trench 200 may be formed in any manner that can be accomplished in the art, for example, by a wet or dry etching process, a plasma etching process, laser drilling, etc., and the depth of the trench 200 is selected as desired, depending on the designer's choice.
Referring to fig. 2a, a liner layer 300 is formed by performing step S3 to deposit the liner layer 300 onto the surface of the semiconductor substrate 100 where the trench 200 is formed such that the liner layer 300 covers at least the inner surface of the trench 200, the liner layer 300 being a metal or a combination of a metal and a metal nitride. Before filling the trench 200, a liner layer 300 attached to the bottom and the sidewall of the trench 200 is formed in the trench 200, and since the liner has a lattice similar to that of the hole filling metal 400, the adsorption force of the inner wall surface of the trench 200 to the subsequent hole filling metal 400 can be increased, thereby improving the filling effect.
In some embodiments, as shown in fig. 2a, the liner layer 300 includes a filling portion 301 covering the inner surface of the trench 200 and an overflow portion 302 located over the surface of the semiconductor substrate 100 outside the trench 200, and further includes step S31 before filling the trench 200 with the hole filling metal 400: the overflow portion 302 outside the trench 200 is removed, and only the filling portion 301 inside the trench 200 is remained, so that the adsorption force of the outside of the trench 200 to the subsequent hole filling metal 400 is eliminated, so that the hole filling metal 400 is pulled into the trench 200 during the subsequent filling process of the trench 200, the hole filling capability is easier to be formed, the defect such as a void is avoided in the filled trench 200, and the cross-sectional view of the liner layer 300 after the overflow portion 302 is removed is shown in fig. 2 b. In some embodiments, the overflow portion 302 of the liner layer 300 may be removed by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process or an etching process.
In some embodiments, the thickness of the backing layer 300 isFor example, it may be specificallyAnd->Etc. and any value within the range, as may be appropriate for the actual situation and designer choice.
In some embodiments, the liner layer 300 includes an underlying nitride layer and a metal layer overlying the nitride layer, the metal layer being titanium, cobalt, tantalum, tungsten, or ruthenium, the nitride layer being a nitride of titanium, cobalt, tantalum, tungsten, or ruthenium. The nitride layer below has good blocking effect, the crystal lattices of the metal layer and the hole filling metal 400 are closer, and in the subsequent hole filling process, good wetting effect can be formed between the hole filling metal 400 and the metal layer serving as a lining, so that the adsorption force to the hole filling metal 400 is improved.
Since the liner layer 300 is easily oxidized when exposed to air after being formed, in some embodiments, after the liner layer 300 is formed and before the hole filling metal 400 is filled into the trench 200, the method further includes step S32: the lining layer 300, and in particular the filled portion 301 of the lining layer 300, is subjected to a step of reduction. Specifically, in step S31, the oxidized liner layer 300 is reduced by introducing a reducing gas into the trench 200, thereby improving the subsequent adsorption force. The reducing gas may be plasma hydrogen (plasma h+), excited state hydrogen (h+), or a mixed gas of plasma hydrogen and excited state hydrogen, which is not limited in this application.
Subsequently, the trench 200 is filled with the hole filling metal 400 by performing step S4 so that the trench 200 is filled. Specifically, in this step, as shown in fig. 2 c-2 e, filling is performed by a deposition process, which may be, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), high-density plasma CVD (High Density Plasma, HDPCVD), metal Organic CVD (MOCVD), or the like, and heating is performed at the same time or at intervals of deposition so that the hole-filling Metal 400 flows back, and the hole-filling Metal 400 is pulled into the trench 200 by the adsorption force of the lining 300 in the trench 200, so that void-free filling is achieved. In some embodiments, the hole filling metal 400 is aluminum, copper, nickel, strontium, cobalt, zinc, or an alloy of at least two of aluminum, copper, nickel, strontium, cobalt, zinc, which may be specifically determined according to the needs and the designer's choice, and is not limited in this application. In addition, the heating treatment can be performed by any existing realizable mode, and the application is not particularly limited; the temperature raising treatment can be performed at the same time as the deposition, or after a period of time, the temperature raising treatment can be performed. The temperature of the heating treatment may be low and then gradually increased, or may be initial, i.e., high, or may be periodically subjected to the heating treatment, etc., and the present application is not particularly limited as long as the hole-filling metal 400 can be in a flowing state or a semi-flowing state.
In some embodiments, the step S4 of filling the trench 200 with the hole-filling metal 400 specifically includes the following steps: s41: as shown in fig. 2c, a hole filling metal 400 is deposited into the trench 200; s42: as shown in fig. 2d, the hole filling metal 400 is reflowed by heating while depositing; s43: the final temperature is maintained until the filling is completed, as shown in fig. 2 e. Firstly, filling a part of hole filling metal 400 in the groove 200, then, heating while depositing to enable the hole filling metal 400 to be in a flowing state or a semi-flowing state, filling possible defects such as gaps in the filling process after the hole filling metal 400 flows back, and keeping the final heating temperature until the hole filling is finished, so that filling almost without gaps can be realized. In some embodiments, the final temperature of the heating treatment is 250 ℃ to 500 ℃, the heating rate is more than 50 ℃/min, the maintaining time of the final temperature is 3 to 30min, and the person skilled in the art can select the temperature within the above range according to the actual situation.
A second aspect of the embodiments of the present application provides a semiconductor structure manufactured according to the semiconductor manufacturing method according to any one of the embodiments of the first aspect, in which the trench 200 after the metallization with little or no void is formed, which may be used in a device package to implement interconnection, and may improve the reliability of a semiconductor device.
As shown in fig. 2e, the semiconductor structure includes:
a semiconductor substrate 100 in which a trench 200 is formed in the semiconductor substrate 100, the trench being opened from the surface to the inside;
a hole filling metal 400 filled in the trench 200;
a liner layer 300 between the trench 200 and the hole filling metal 400, the liner layer 300 being a metal or a combination of metal and metal nitride.
Finally, it should be noted that: in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same; while the invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that: modifications may be made to the specific embodiments of the present invention or equivalents may be substituted for part of the technical features thereof; without departing from the spirit of the invention, it is intended to cover the scope of the invention as claimed.
Claims (10)
1. A method of manufacturing a semiconductor, comprising at least the steps of:
providing a semiconductor substrate;
forming a trench in the semiconductor substrate, the trench being opened to the inside from the surface of the semiconductor substrate;
depositing a lining layer on the surface of the semiconductor substrate with the groove, wherein the lining layer covers the inner surface of the groove, and the lining layer is metal or a combination of metal and metal nitride;
and filling hole filling metal into the groove so as to fill the groove.
2. The semiconductor manufacturing method according to claim 1, wherein the liner layer includes a filling portion covering an inner surface of the trench and an overflow portion located over a surface of the semiconductor substrate outside the trench, and further comprising, before filling the trench with a hole filling metal: the overflow portion of the backing layer is removed.
3. The method of manufacturing a semiconductor according to claim 2, wherein the thickness of the lining layer is
4. The method of claim 2, wherein the liner layer comprises an underlying nitride layer and a metal layer overlying the nitride layer, the metal layer being titanium, cobalt, tantalum, tungsten, or ruthenium, and the nitride layer being a nitride of titanium, cobalt, tantalum, tungsten, or ruthenium.
5. The semiconductor manufacturing method according to claim 2, further comprising, before filling the trench with a hole filling metal: and a step of introducing a reducing gas into the groove to reduce the lining layer.
6. The method of manufacturing a semiconductor according to claim 2, wherein in the step of filling the trench with the hole-filling metal, filling is performed by a deposition process, and heating is performed at the same time as or at a deposition interval to reflow the hole-filling metal.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of filling the trench with a hole filling metal comprises:
depositing the hole filling metal into the groove;
heating while depositing to make the hole filling metal reflow;
maintaining the final temperature until the filling is completed.
8. The method according to claim 7, wherein the final temperature is 250 ℃ to 500 ℃, the temperature rise rate is more than 50 ℃/min, and the maintenance time of the final temperature is 3 to 30min.
9. The method of claim 1, wherein the hole-filling metal is aluminum, copper, nickel, strontium, cobalt, zinc, or an alloy of at least two of aluminum, copper, nickel, strontium, cobalt, zinc.
10. A semiconductor structure manufactured by the semiconductor manufacturing method according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311836598.3A CN117747543A (en) | 2023-12-28 | 2023-12-28 | Semiconductor manufacturing method and semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311836598.3A CN117747543A (en) | 2023-12-28 | 2023-12-28 | Semiconductor manufacturing method and semiconductor structure |
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| Publication Number | Publication Date |
|---|---|
| CN117747543A true CN117747543A (en) | 2024-03-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311836598.3A Pending CN117747543A (en) | 2023-12-28 | 2023-12-28 | Semiconductor manufacturing method and semiconductor structure |
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| Country | Link |
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| CN (1) | CN117747543A (en) |
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