CN117747540A - Preparation method of nanoscale deep hole and nano device - Google Patents
Preparation method of nanoscale deep hole and nano device Download PDFInfo
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- CN117747540A CN117747540A CN202311489575.XA CN202311489575A CN117747540A CN 117747540 A CN117747540 A CN 117747540A CN 202311489575 A CN202311489575 A CN 202311489575A CN 117747540 A CN117747540 A CN 117747540A
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- contact hole
- amorphous silicon
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- 238000002360 preparation method Methods 0.000 title abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 238000000151 deposition Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000000126 substance Substances 0.000 claims abstract description 12
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 8
- 239000011148 porous material Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 239000012670 alkaline solution Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000005137 deposition process Methods 0.000 abstract description 2
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 238000007687 exposure technique Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000276 deep-ultraviolet lithography Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
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Abstract
The application relates to the technical field of deposition processes, and provides a preparation method of a nanoscale deep hole and a nanoscale device, wherein the method comprises the following steps: depositing a first silicon oxide layer with a preset thickness on the surface of the substrate; exposing the first silicon oxide layer to form a contact hole with a preset size; depositing a SIN termination layer on the surfaces of the first silicon oxide layer and the contact hole; depositing a second silicon dioxide layer on the surface of the SIN termination layer until reaching the target aperture; depositing an amorphous silicon film, and filling the target aperture; and removing the amorphous silicon film and the SIN termination layer at the bottom of the contact hole by wet etching. According to the technical scheme, the conventional photoetching technology is combined with the film and the chemical mechanical polishing and etching process, so that the contact holes below 50nm are realized, the production and manufacturing cost is reduced, the productivity pressure of the DUV photoetching machine is reduced, and the application range of different I photoetching machines is widened.
Description
[ field of technology ]
The application relates to the technical field of deposition processes, in particular to a preparation method of a nanoscale deep hole and a nano device.
[ background Art ]
In advanced integrated circuit manufacturing processes, in order to increase the chip integration, the critical dimensions of the device, particularly to photolithography processes, are continuously reduced by reducing the geometric dimensions of a series of pattern structures, such as patterns of lines, holes, etc. The simplest way to use is to obtain the nano-scale pattern by exposure with an EUV lithography machine. However, the extreme ultraviolet lithography machine is extremely costly and has been the productivity bottleneck in the industry.
[ invention ]
The embodiment of the application provides a preparation method of a nano-scale deep hole and a nano device, and aims to solve the technical problems that a nano-scale pattern adopts an extreme ultraviolet lithography machine and the cost is high in the related art.
In a first aspect, an embodiment of the present application provides a method for preparing a nanoscale deep hole, where the method includes:
depositing a first silicon oxide layer with a preset thickness on the surface of the substrate;
exposing the first silicon oxide layer to form a contact hole with a preset size;
depositing a SIN (silicon nitride film) termination layer on the surfaces of the first silicon oxide layer and the contact hole;
depositing a second silicon dioxide layer on the surface of the SIN termination layer until reaching the target aperture;
depositing an amorphous silicon film, and filling the target aperture;
and removing the amorphous silicon film and the SIN termination layer at the bottom of the contact hole by wet etching.
In one embodiment, optionally, before depositing the amorphous silicon thin film, the preparation method further includes:
and reversely etching the second silicon dioxide layer at the opening of the target aperture, and forming a bowl opening structure at the top.
In one embodiment, optionally, after depositing the amorphous silicon thin film and filling the target aperture, the preparation method further includes:
and (3) adopting a chemical mechanical polishing method to grind the top bowl opening structure flat.
In one embodiment, optionally, an alkaline solution is used to remove the amorphous silicon film.
In one embodiment, optionally, the preparation method further comprises:
and depositing a metal layer on the surface of the contact hole after wet etching.
In one embodiment, the thickness of the SIN termination layer is optionally 1-10nm, and the deposition temperature is 400-800 ℃.
In one embodiment, optionally, the target pore size is less than 50nm.
In one embodiment, optionally, after depositing the first silicon oxide layer of a predetermined thickness, the surface is planarized using a chemical mechanical polishing process.
In one embodiment, the predetermined dimension is optionally greater than 250nm.
In a second aspect, embodiments of the present application provide a nanodevice, comprising: the microporous structure is prepared by the preparation method of the nano-scale deep hole.
In the scheme realized by the preparation method of the nano-scale deep hole and the nano device, a first silicon oxide layer with preset thickness is deposited on the surface of the substrate; exposing the first silicon oxide layer to form a contact hole with a preset size; depositing a SIN termination layer on the surfaces of the first silicon oxide layer and the contact hole; depositing a second silicon dioxide layer on the surface of the SIN termination layer until reaching the target aperture; depositing an amorphous silicon film, and filling the target aperture; and removing the amorphous silicon film and the SIN termination layer at the bottom of the contact hole by wet etching. Thus, the conventional photoetching technology is combined with the film and the chemical mechanical polishing and etching process, so that the contact hole with the thickness of less than 50nm is realized, the production and manufacturing cost is reduced, the productivity pressure of the DUV photoetching machine is reduced, and the application range of the I-line photoetching machine is widened.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic flow chart of a method of fabricating a nanoscale deep hole according to one embodiment of the present application.
Fig. 2 to 9 show schematic diagrams of the process of preparing a nano-scale deep hole according to the present application.
[ detailed description ] of the invention
For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, fig. 1 shows a schematic flow chart of a method for fabricating a nanoscale deep hole according to one embodiment of the present application. The preparation method of the nano-scale deep hole is used for solving the technical problems that the cost of the nano-scale image in the related technology is high by adopting an extreme ultraviolet lithography machine.
As shown in fig. 1, a method for preparing a nano-scale deep hole according to an embodiment of the present application includes:
step S101, depositing a first silicon oxide layer with a preset thickness on the surface of a substrate;
as shown in fig. 2, the substrate may be silicon, and a substantial thickness of silicon oxide, an insulating dielectric material, is deposited on the substrate.
In one embodiment, optionally, after depositing the first silicon oxide layer of a predetermined thickness, the surface is planarized using a chemical mechanical polishing process.
Step S102, exposing the first silicon oxide layer to form a contact hole with a preset size;
as shown in fig. 3, contact holes are formed with a size greater than 250nm by exposure using conventional exposure techniques.
Specifically, conventional exposure techniques may employ I-line lithography, DUV is deep ultraviolet (Deep Ultraviolet Lithography), EUV is extreme ultraviolet (Extreme Ultraviolet Lithography). From the process scale, DUV can be essentially only 25nm. Only EUV can satisfy wafer fabrication of 10nm or less, and can continue to extend to 5nm and 3 nm. But EUV is very costly.
Step S103, depositing a SIN termination layer on the surfaces of the first silicon oxide layer and the contact hole;
as shown in FIG. 4, a SIN termination layer is deposited on the surfaces of the first silicon oxide layer and the contact hole, wherein the thickness of the SIN termination layer is 1-10nm, and the deposition temperature is 400-800 ℃. Specifically, the deposition may be performed by an LPCVD (Low pressure chemical vapor deposition) method, which is a CVD reaction in which the operating pressure of the reaction gas in the reactor is reduced to about 133Pa or less.
The LPCVD pressure is reduced below about 133Pa, and accordingly, the free path and gas diffusion coefficient of molecules are increased, so that the mass transfer rate of gaseous reactants and byproducts is accelerated, the reaction rate of forming a film is increased, even if the distance between parallel and vertical arranged chips is reduced to 5-10mm, the mass transfer limit can be ignored compared with the chemical reaction rate of the surfaces of the chips, thereby creating conditions for vertically and densely packing the chips and greatly improving the chip packing capacity of each batch.
The thin film deposited by LPCVD method has better step coverage capability, better composition and structure control, higher deposition rate and output. Furthermore, LPCVD does not require carrier gases, thereby greatly reducing the source of particulate contamination.
Step S104, depositing a second silicon dioxide layer on the surface of the SIN termination layer until the target aperture is reached;
as shown in fig. 4, a second silicon dioxide layer is deposited on the surface of the SIN termination layer until a target pore size is reached, wherein the target pore size may be less than 50nm.
In the embodiment, the conventional photoetching technology is used, and the film side wall growth technology is combined, so that the nanoscale deep hole structure is obtained, the productivity pressure of the DUV photoetching machine is reduced, and the application range of different I-line photoetching machines is widened.
In one embodiment, optionally, the preparation method further comprises:
and reversely etching the second silicon dioxide layer at the opening of the target aperture to form a bowl opening structure at the top.
As shown in fig. 5, to facilitate amorphous silicon filling during subsequent fabrication, a second silicon oxide layer is etched back at the opening of the target aperture to form a bowl opening structure at the top.
Step S105, depositing an amorphous silicon film, and filling the target aperture;
as shown in fig. 6, an amorphous silicon thin film is deposited on the surface of the second silicon oxide layer to fill the holes.
In one embodiment, optionally, after depositing the amorphous silicon thin film and filling the target aperture, the preparation method further includes:
as shown in fig. 7, the top bowl opening structure is flattened by chemical mechanical polishing.
In this step, the pore diameter is filled by the amorphous silicon film, so that the blocking of the pore diameter by the grinding liquid particles can be avoided. And after the aperture is filled, removing the bowl opening structure formed in the back etching process by adopting a chemical mechanical polishing method.
Among them, amorphous silicon (amorphous silicon α -Si) is also called amorphous silicon, and its microstructure is characterized by long-range disorder and short-range disorder. Although the Si atom is also bonded to the other four atoms, the spatial node of the composition is not reproducible in three dimensions, and the four coordinating atoms are not necessarily all present, wherein part of the coordinating Si atoms are also replaced by hydrogen atoms. Therefore, amorphous silicon materials contain a large number of defects, which have more active chemical properties than crystalline silicon with a regular and complete structure, and are less difficult and costly to produce. Compared with crystalline silicon, the amorphous silicon film material has more complicated and changeable electrical properties, and in addition, the amorphous silicon film material has higher light absorption coefficient and stronger photoelectric conversion capability. The preparation method of the amorphous silicon film material mainly comprises a vacuum evaporation method, a sputtering method, a chemical vapor deposition method, a plasma chemical vapor deposition method and the like.
And S106, removing the amorphous silicon film and the SIN termination layer at the bottom of the contact hole by wet etching.
As shown in fig. 8, the amorphous silicon film is removed by alkaline solution, and the bottom SIN is removed by SIN wet etching, because the SIN thickness is very thin, the SIN etching on the top is negligible.
In one embodiment, optionally, the preparation method further comprises:
as shown in fig. 9, a metal layer is deposited on the surface of the contact hole after wet etching.
The metal deposition process is one common surface treating technology, and may form one homogeneous, compact and excellent adhesion metal film on the surface of metal to improve the physical and chemical performance of metal and raise the corrosion resistance, wear resistance, conductivity and other characteristics.
The metal deposition process is mainly divided into electrochemical deposition and physical vapor deposition. Electrochemical deposition is a process of reducing and depositing a metal film on the surface of an electrode by utilizing metal ions in an electrolyte, and the common electrolytes include acidity, alkalinity, hydrochloride and the like. Physical vapor deposition is to evaporate metal into gas at high temperature under high vacuum condition, and then deposit metal film on the surface of the substrate, and common methods include thermal evaporation, electron beam evaporation, magnetron sputtering, etc.
In the scheme realized by the preparation method of the nano-scale deep hole and the nano device, a first silicon oxide layer with preset thickness is deposited on the surface of the substrate; exposing the first silicon oxide layer to form a contact hole with a preset size; depositing a SIN termination layer on the surfaces of the first silicon oxide layer and the contact hole; depositing a second silicon dioxide layer on the surface of the SIN termination layer until reaching the target aperture; depositing an amorphous silicon film, and filling the target aperture; and removing the amorphous silicon film and the SIN termination layer at the bottom of the contact hole by wet etching. Thus, the conventional photoetching technology is combined with the film and the chemical mechanical polishing and etching process, so that the contact hole with the thickness of less than 50nm is realized, the production and manufacturing cost is reduced, the productivity pressure of the DUV photoetching machine is reduced, and the application range of different L-L ine photoetching machines is widened.
For specific limitations of the nano-device, reference may be made to the above limitation of the method for preparing a nano-scale deep hole, and the description thereof will not be repeated here.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be understood that although the terms first, second, etc. may be used in embodiments of the present application to describe the setting units, these setting units should not be limited by these terms. These terms are only used to distinguish the setting units from each other. For example, the first setting unit may also be referred to as a second setting unit, and similarly, the second setting unit may also be referred to as a first setting unit, without departing from the scope of the embodiments of the present application.
Depending on the context, the word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection". Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (10)
1. A method for preparing a nanoscale deep hole, the method comprising:
depositing a first silicon oxide layer with a preset thickness on the surface of the substrate;
exposing the first silicon oxide layer to form a contact hole with a preset size;
depositing a SIN termination layer on the surfaces of the first silicon oxide layer and the contact hole;
depositing a second silicon dioxide layer on the surface of the SIN termination layer until reaching the target aperture;
depositing an amorphous silicon film, and filling the target aperture;
and removing the amorphous silicon film and the SIN termination layer at the bottom of the contact hole by wet etching.
2. The method of manufacturing according to claim 1, wherein before depositing the amorphous silicon thin film, the method of manufacturing further comprises:
and reversely etching the second silicon dioxide layer at the opening of the target aperture, and forming a bowl opening structure at the top.
3. The method of claim 1, wherein after depositing the amorphous silicon thin film to fill the target aperture, the method further comprises:
and (3) adopting a chemical mechanical polishing method to grind the top bowl opening structure flat.
4. The method according to claim 1, wherein the amorphous silicon thin film is removed using an alkaline solution.
5. The method of manufacturing according to claim 1, characterized in that the method of manufacturing further comprises:
and depositing a metal layer on the surface of the contact hole after wet etching.
6. The method of claim 1, wherein the SIN termination layer has a thickness of 1-10nm and a deposition temperature of 400-800 ℃.
7. The method of claim 1, wherein the target pore size is less than 50nm.
8. The method of claim 1, wherein the surface is planarized by chemical mechanical polishing after depositing the first silicon oxide layer to a predetermined thickness.
9. The method of claim 1, wherein the predetermined dimension is greater than 250nm.
10. A nanodevice, comprising: a microporous structure prepared by the method for preparing a nano-scale deep hole according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311489575.XA CN117747540A (en) | 2023-11-09 | 2023-11-09 | Preparation method of nanoscale deep hole and nano device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311489575.XA CN117747540A (en) | 2023-11-09 | 2023-11-09 | Preparation method of nanoscale deep hole and nano device |
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| Publication Number | Publication Date |
|---|---|
| CN117747540A true CN117747540A (en) | 2024-03-22 |
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| CN202311489575.XA Pending CN117747540A (en) | 2023-11-09 | 2023-11-09 | Preparation method of nanoscale deep hole and nano device |
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| Country | Link |
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| CN (1) | CN117747540A (en) |
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- 2023-11-09 CN CN202311489575.XA patent/CN117747540A/en active Pending
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