CN117746946A - RRAM reading circuit and reading method thereof - Google Patents

Abstract

The invention provides an RRAM reading circuit, comprising: a reference resistor; one side is connected with the reference resistor and the variable resistor of the RRAM, and the switch module is used for controlling the on-off between the reference resistor and the variable resistor of the RRAM and the self-bias module; one side of the self-bias module is connected with the other side of the switch module, and the self-bias module is used for clamping the node voltage between the self-bias module and the switch module in the pre-charging step; one side is connected with the other side of the self-bias module, and is used for amplifying the current difference value formed in the pre-charging step through positive feedback so as to be converted into a comparison voltage; the precharge module is connected with the other side of the cross coupling module and used for precharging the RRAM reading circuit; and the output module is connected with the other side of the cross coupling module and is used for comparing the comparison voltage amplified by the cross coupling module and outputting a comparison result.

Description

RRAM reading circuit and reading method thereof

Technical Field

The invention relates to an RRAM reading circuit and a reading method thereof.

Background

Resistive random access memory (RRAM; resistive Random Access Memory) is an emerging non-volatile memory technology based on the reversible switching of the resistance of a non-conductive material between a high resistance state and a low resistance state under the influence of an applied electric field. It has high-speed read-write capability of static random access memory, high integration of dynamic random access memory, and can basically realize infinite data writing. RRAM can exhibit both high and low resistance states after application of different voltage conditions and can permanently retain stored data after power down. RRAM is currently mainly applied to the fields of IoT devices, neural networks, artificial intelligence, and the like. In terms of commercialization, RRAM has two main application directions—storage applications and computing applications. In the aspect of storage application, manufacturers apply RRAM to the MCU field at present; in the aspect of integrated memory and calculation, companies are trying to realize an AI high-power chip through an integrated memory and calculation architecture based on RRAM and apply the AI high-power chip to application scenes of a center side and an edge side.

The RRAM stores information by converting its resistance signal into a current or voltage signal that can be read by peripheral circuits. One prior art RRAM read circuit is shown in fig. 1. The transistors M0 and M1 having the same size serve as switching transistors, and connect the read circuit and the array resistor to each other while the read enable voltage Vread is pulled high. The LDO (Low Dropout Regulaor; low dropout linear voltage regulator) structure consisting of the same size transistor M2, transistor M3 and two identical OTAs (Operational Transconductance Amplifier; operational transconductance amplifiers) clamps A, B two-point voltages, converting the information of the variable resistance of the RRAM and the information of the reference resistance into current information. A. The two currents generated at the two points B are respectively sent to a transistor M4 and a transistor M5 with the same size, and the transistor M4 and the transistor M5 are connected as a PMOS transistor with diodes, which can convert the current information into the voltage information, send the voltage information to the two ends of the comparator CMP for comparison, and then output the read data Dout.

Disclosure of Invention

Although the above-described RRAM reading circuit can realize reading of RRAM resistance value information, this structure has the following drawbacks. Firstly, as process nodes are continuously reduced, windows between high resistance and low resistance of the RRAM are also reduced; in the manner of the RRAM read circuit, only after two paths of comparison currents are generated in the memory cell and the reference cell, the comparison currents are converted into comparison voltages, the read margin is not increased, and the risk of read failure exists along with the reduction of the resistance window. In general, in order to make the resistance of the transistor M0 and the transistor M1 smaller when they are turned on and the adaptation error generated by them smaller, the size requirements of the transistor M0 and the transistor M1 are larger, so that when Vread is pulled high, the level of the jump will raise the potential at the point a, i.e. the read voltage is raised, through the parasitic capacitance of the gate and drain of the transistor M0 and the transistor M1. Vclamp has the function of clamping the read voltage of the RRAM, and if the read voltage is too high, the read voltage can possibly write the RRAM by mistake, so that the resistance state of the RRAM is changed, and the reliability problem is brought to the RRAM. In addition, the memory generally requires higher than 8-bit output, meaning that at least 8 read circuits are required for outputting data in parallel by one RRAM memory, and the structure of the RRAM read circuit occupies at least 16 areas of Operational Transconductance Amplifier (OTA) and its bias circuit, which affects the memory density of the chip.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an RRAM reading circuit including a plurality of transistors, a reference resistor, and a comparator, which sets a read enable voltage, a voltage inverted from the read enable voltage, a precharge voltage, and a voltage inverted from the precharge voltage to be readable by the RRAM reading circuit, through a discharging step, a precharge step, and a comparing step, so as to convert a resistance signal of a variable resistor of the RRAM into a signal that can be read.

Technical proposal for solving the technical problems

In order to solve the above-described problems, an RRAM read circuit according to a first aspect of the present invention includes:

a reference resistor;

the switch module is connected with the reference resistor and the variable resistor of the RRAM at one side and used for controlling the on-off of the reference resistor, the variable resistor of the RRAM and the self-bias module;

the self-bias module is connected with the other side of the switch module and used for clamping the voltage of a node between the self-bias module and the switch module in the pre-charging step;

a cross coupling module having one side connected to the other side of the self-bias module for amplifying the current difference value formed in the precharge step by positive feedback to be converted into a comparison voltage;

The precharge module is connected with the other side of the cross coupling module and is used for precharging the RRAM reading circuit; and

and the output module is connected with the other side of the cross coupling module and is used for comparing the comparison voltage amplified by the cross coupling module and outputting a comparison result.

Further, the RRAM read circuit performs the following steps when performing a read:

a discharging step for discharging a node between the output module and the cross-coupling module and a clamp node in the self-bias module;

a precharge step for charging a node between the output module and the cross-coupling module to a power supply voltage and charging the clamp node in the self-bias module to a clamp voltage; and

and a comparison step of amplifying the current difference value formed in the precharge step by positive feedback to convert it into a comparison voltage, comparing the comparison voltage amplified by the cross-coupling module, and outputting a comparison result.

Further, the switch module comprises a first transistor and a twelfth transistor,

The self-biasing module includes a second transistor, a third transistor, a tenth transistor, and an eleventh transistor,

the cross-coupling module includes a fourth transistor, a fifth transistor, an eighth transistor, and a ninth transistor,

the precharge module includes a sixth transistor and a seventh transistor,

the output module comprises a comparator which is arranged to compare,

the source of the twelfth transistor is connected with the variable resistor of the RRAM, the grid of the twelfth transistor is connected with the grid of the first transistor, the drain of the twelfth transistor is connected with the source of the second transistor,

the source of the first transistor is connected with the reference resistor, the drain of the first transistor is connected with the source of the third transistor,

the grid electrode of the second transistor is connected with the drain electrode of the tenth transistor, the source electrode of the eleventh transistor and the grid electrode of the third transistor, the drain electrode of the second transistor is connected with the source electrode of the fourth transistor,

the grid electrode of the third transistor is connected with the drain electrode of the tenth transistor, the source electrode of the eleventh transistor and the grid electrode of the second transistor, the drain electrode of the third transistor is connected with the drain electrode of the eleventh transistor and the source electrode of the fifth transistor,

The grid electrode of the fourth transistor is connected with one input terminal of the comparator, the drain electrode of the fifth transistor, the drain electrode of the seventh transistor and the drain electrode of the ninth transistor, the drain electrode of the fourth transistor is connected with the drain electrode of the eighth transistor, the drain electrode of the sixth transistor, the other input terminal of the comparator and the grid electrode of the fifth transistor,

the grid electrode of the fifth transistor is connected with the other input terminal of the comparator, the drain electrode of the fourth transistor, the drain electrode of the sixth transistor and the drain electrode of the eighth transistor, the drain electrode of the fifth transistor is connected with the drain electrode of the ninth transistor, the drain electrode of the seventh transistor, one input terminal of the comparator and the grid electrode of the fourth transistor, the source electrode of the fifth transistor is connected with the drain electrode of the third transistor and the drain electrode of the eleventh transistor,

the drain of the sixth transistor is connected to the drain of the eighth transistor, the drain of the fourth transistor, the other input terminal of the comparator, the gate of the fifth transistor, the gate of the sixth transistor is connected to the gate of the seventh transistor, the source of the sixth transistor is applied with a power supply voltage,

The drain of the seventh transistor is connected to the drain of the ninth transistor, the drain of the fifth transistor, one input terminal of the comparator, the gate of the fourth transistor, the source of the seventh transistor is applied with a power supply voltage,

the source electrode of the eighth transistor is grounded, the drain electrode of the eighth transistor is connected with the drain electrode of the fourth transistor, the drain electrode of the sixth transistor, the other input terminal of the comparator and the gate electrode of the fifth transistor,

the source electrode of the ninth transistor is grounded, the drain electrode of the ninth transistor is connected with the drain electrode of the fifth transistor, the drain electrode of the seventh transistor, one input terminal of the comparator and the gate electrode of the fourth transistor,

the source electrode of the tenth transistor is grounded, the drain electrode of the tenth transistor is connected with the grid electrode of the second transistor, the grid electrode of the third transistor and the source electrode of the eleventh transistor,

the drain of the eleventh transistor is connected with the drain of the third transistor and the source of the fifth transistor, the source of the eleventh transistor is connected with the gate of the second transistor, the gate of the third transistor and the drain of the tenth transistor,

A gate of the twelfth transistor and a gate of the first transistor are applied with a read enable voltage, a gate of the eighth transistor, a gate of the ninth transistor and a gate of the tenth transistor are applied with voltages opposite to the read enable voltage,

the gate of the eleventh transistor is applied with a precharge voltage, the gates of the sixth and seventh transistors are applied with voltages opposite to the precharge voltage,

the read enable voltage, the voltage opposite to the read enable voltage, the precharge voltage, and the voltage opposite to the precharge voltage are set so that reading can be performed with the RRAM read circuit to convert a resistance signal of a variable resistor of the RRAM into a signal that can be read.

Further, a node between the drain of the twelfth transistor and the source of the second transistor is L1, a node between the drain of the first transistor and the source of the third transistor is L2, a node between the drain of the fourth transistor and the drain of the sixth transistor is L3, a node between the drain of the fifth transistor and the drain of the seventh transistor is L4, a node between the gate of the second transistor and the gate of the third transistor is L5,

The RRAM reading circuit performs the following steps when reading:

a discharging step of setting the read enable voltage to a low voltage, setting a voltage opposite to the read enable voltage to a high voltage, setting the precharge voltage to a low voltage, and setting a voltage opposite to the precharge voltage to a high voltage, so that the eighth transistor, the ninth transistor, and the tenth transistor are turned on to discharge L3, L4, and L5;

a precharge step of setting the read enable voltage to a high voltage, setting a voltage opposite to the read enable voltage to a low voltage, setting the precharge voltage to a high voltage, setting a voltage opposite to the precharge voltage to a low voltage, and turning on the twelfth transistor, the first transistor, the sixth transistor, the seventh transistor, and the eleventh transistor to charge L3 and L4 to a power supply voltage and to charge L5 to a clamp voltage; and

and a comparison step of maintaining the read enable voltage at a high voltage, maintaining a voltage opposite to the read enable voltage at a low voltage, setting the precharge voltage at a low voltage, and setting a voltage opposite to the precharge voltage at a high voltage, so that the twelfth transistor, the first transistor, and the sixth transistor, the seventh transistor, and the eleventh transistor are turned off to compare a voltage difference formed between L3 and L4 by the comparator.

Further, in the comparing step, when the resistance value of the variable resistor of the RRAM is lower than the resistance value of the reference resistor, the voltage drop rate of L4 is faster than the voltage drop rate of L3; when the resistance of the variable resistor of the RRAM is higher than that of the reference resistor, the voltage of L3 drops faster than that of L4.

Further, the minimum value of the high resistance of the variable resistance of the RRAM is set as R _H The highest value of the variable resistance of the RRAM is R _L Setting the resistance of the reference resistor as R _ref The resistance of the reference resistor is obtained by the following calculation formula:

further, the variable resistance of the RRAM has a high resistance range of 500KΩ to 2MΩ, and the variable resistance of the RRAM has a low resistance range of 10KΩ to 100KΩ.

Further, the resistance value of the reference resistor is 167kΩ.

Further, the twelfth transistor has the same specification as the first transistor,

the second transistor has the same specifications as the third transistor,

the fourth transistor has the same specifications as the fifth transistor,

the specification of the sixth transistor is the same as that of the seventh transistor.

Further, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor are NMOS transistors, and the sixth transistor, the seventh transistor are PMOS transistors.

In a reading method of an RRAM reading circuit according to a second aspect of the present invention, the RRAM reading circuit includes:

a reference resistor;

the switch module is connected with the reference resistor and the variable resistor of the RRAM at one side and used for controlling the on-off of the reference resistor, the variable resistor of the RRAM and the self-bias module;

the self-bias module is connected with the other side of the switch module and used for clamping the voltage of a node between the self-bias module and the switch module in the pre-charging step;

a cross coupling module having one side connected to the other side of the self-bias module for amplifying the current difference value formed in the precharge step by positive feedback to be converted into a comparison voltage;

The precharge module is connected with the other side of the cross coupling module and is used for precharging the RRAM reading circuit; and

the output module is connected with the other side of the cross coupling module and is used for comparing the comparison voltage amplified by the cross coupling module and outputting a comparison result,

the RRAM reading circuit performs the following steps when reading:

a discharging step for discharging a node between the output module and the cross-coupling module and a clamp node in the self-bias module;

a precharge step for charging a node between the output module and the cross-coupling module to a power supply voltage and charging the clamp node in the self-bias module to a clamp voltage; and

and a comparison step of amplifying the current difference value formed in the precharge step by positive feedback to convert it into a comparison voltage, comparing the comparison voltage amplified by the cross-coupling module, and outputting a comparison result.

Effects of the invention

According to the RRAM reading circuit of the invention, the process of reading RRAM resistance is mainly divided into two stages of a precharge stage and an amplifying comparison stage, and the precharge stage can quickly form stable I due to the parasitic capacitance of the MOS transistor _L1 、I _L2 And besides the power consumption of the comparator, the structure of the RRAM reading circuit can generate lower power consumption only in the precharge stage. In addition, in the amplifying and comparing stage, the cross-coupled MOS transistor pair composed of the transistor M4 and the transistor M5 converts the current signal into the voltage signal through positive feedback, so that the read margin can be increased, and the positive feedback conversion of the current voltage in the amplifying and comparing stage accelerates the comparing process, so that the read time can be shortened, and the reliability of the RRAM read data can be increased.

In addition, due to the reference resistance R _ref The present invention can also limit the voltages at the nodes L1 and L2 by setting the sizes of the transistors M1, M3, M5, and M7 to define the voltage at the node L5 in the precharge phase, and can prevent erroneous writing due to excessive voltage applied to the RRAM. In addition, since the voltage of the node L5 is discharged to 0V before the read enable voltage Vread is pulled up, a problem of erroneous writing due to the clamp voltage being raised does not occur.

In addition, in the RRAM reading circuit structure of the invention, the transistors M8, M9, M10 and M11 only need to complete the switching function, so that the minimum size area is adopted, and the occupied area of the RRAM reading circuit structure of the invention is smaller because no operational transconductance amplifier is arranged.

Drawings

Fig. 1 is a circuit schematic diagram showing the structure of an RRAM read circuit in the related art.

Fig. 2 is a schematic diagram showing respective blocks of an RRAM read circuit according to an embodiment of the present invention.

Fig. 3 is a circuit schematic diagram showing a specific configuration of an RRAM read circuit according to an embodiment of the present invention.

Fig. 4 is a waveform diagram showing a process of generating a comparison voltage in the RRAM read circuit according to an embodiment of the present invention.

Description of the reference numerals

101. Switch module

102. Self-biasing module

103. Cross-coupling module

104. Pre-charging module

105. Output module

M ₁ First transistor

M ₂ Second transistor

M ₃ Third transistor

M ₄ Fourth transistor

M ₅ Fifth transistor

M ₆ Sixth transistor

M ₇ Seventh transistor

M ₈ Eighth transistor

M ₉ Ninth transistor

M ₁₀ Tenth transistor

M ₁₁ Eleventh transistor

M ₀ Twelfth transistor

CMP comparator

V _read Read enable voltage

V _readn Voltage opposite to the read enable voltage

V _{sa_pre} Precharge voltage

V _{sa_pren} Voltage opposite to the precharge voltage

V _core Supply voltage

R _cell Variable resistor of RRAM

R _ref Reference resistor

Detailed Description

The invention will be described in detail below with reference to the drawings and the detailed description. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed embodiment and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.

Spatially relative terms, such as "under," "below," "lower," "over," "upper," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features.

Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. The terms are to be understood to have meanings consistent with the context of the relevant art and are not to be construed as idealized or overly formal unless expressly so defined herein.

< Structure of RRAM read Circuit >

Fig. 2 is a schematic diagram showing respective blocks of an RRAM read circuit according to an embodiment of the present invention. Next, each module of the RRAM read circuit according to the embodiment of the present invention will be described in detail with reference to fig. 2.

As shown in fig. 2, the RRAM read circuit according to the embodiment of the present invention includes a reference resistor R _ref A switching module 101, a self-biasing module 102, a cross-coupling module 103, a pre-charge module 104, and an output module 105.

Wherein, one side of the switch module 101 is connected with a reference resistor R _ref Variable resistor R of RRAM _cell Connected with the switch module 101 for providing a reference resistance R _ref Variable resistor R of RRAM _cell And the on-off state between the self-bias module 102 is controlled. One side of the self-biasing module 102 is connected with the other side of the switch module 101, and the self-biasing module102 are used to clamp the voltage of the node between the self-biasing module 102 and the switching module 101 during the precharge step. One side of the cross-coupling module 103 is connected to the other side of the self-biasing module 102, and the cross-coupling module 103 is configured to amplify the current with a smaller difference formed in the precharge step by positive feedback to convert the current into a comparison voltage with a larger difference. The precharge module 104 is connected to the other side of the cross-coupling module 103, and the precharge module 104 is used to precharge the RRAM read circuit. The output module 105 is connected to the other side of the cross-coupling module 103, and the output module 105 is configured to compare the comparison voltages amplified by the cross-coupling module 103 and output a comparison result.

The RRAM read circuit performs the following steps when reading. First, a discharging step is performed for discharging the node between the output module 105 and the cross-coupling module 103 and the clamp node in the self-bias module 102. Then, a precharge step is performed for charging the node between the output module 105 and the cross-coupling module 103 to the power supply voltage, and charging the clamp node in the self-bias module 102 to the clamp voltage. Then, a comparison step of amplifying the current having the smaller difference formed in the precharge step by positive feedback to convert into a comparison voltage having the larger difference is performed, and comparing the comparison voltage amplified by the cross coupling module 103 and outputting the comparison result.

Specifically, in the RRAM read circuit according to the embodiment of the present invention, the switch module 101 includes the first transistor M ₁ Twelfth transistor M ₀ The self-bias module 102 includes a second transistor M ₂ Third transistor M ₃ Tenth transistor M ₁₀ Eleventh transistor M ₁₁ The cross-coupling module 103 includes a fourth transistor M ₄ Fifth transistor M ₅ Eighth transistor M ₈ Ninth transistor M ₉ The precharge module 104 includes a sixth transistor M ₆ Seventh transistor M ₇ The output module 105 includes a comparator CMP.

Fig. 3 is a circuit schematic diagram showing a specific configuration of an RRAM read circuit according to an embodiment of the present invention. Next, a specific configuration of the RRAM read circuit according to an embodiment of the present invention will be described in detail with reference to fig. 3.

As shown in fig. 3, a twelfth transistor M ₀ Variable resistor R of source electrode and RRAM _cell Connected, twelfth transistor M ₀ Gate of (c) and first transistor M ₁ Gate connection of twelfth transistor M ₀ Drain electrode of (d) and second transistor M ₂ Is connected to the source of the (c). First transistor M ₁ Source and reference resistor R _ref Connected to the first transistor M ₁ Drain of (d) and third transistor M ₃ Is connected to the source of the (c).

Second transistor M ₂ Gate of (c) and tenth transistor M ₁₀ Drain of (c) eleventh transistor M ₁₁ Source of (d) and third transistor M ₃ Gate connection of the second transistor M ₂ Drain of (d) and fourth transistor M ₄ Is connected to the source of the (c). Third transistor M ₃ Gate of (c) and tenth transistor M ₁₀ Drain of (c) eleventh transistor M ₁₁ Source of (d) and second transistor M ₂ Gate connection of third transistor M ₃ Drain of (d) and eleventh transistor M ₁₁ And a fifth transistor M ₅ Is connected to the source of the (c).

Fourth transistor M ₄ A fifth transistor M having a gate connected to one input terminal (-) of the comparator CMP ₅ Drain of (d) seventh transistor M ₇ Drain of (d) and ninth transistor M ₉ Drain electrode connection of fourth transistor M ₄ Drain of (c) and eighth transistor M ₈ Drain of (d) sixth transistor M ₆ A drain of the comparator CMP, another input terminal (+) of the comparator CMP, a fifth transistor M ₅ Is connected to the gate of the transistor. Fifth transistor M ₅ A gate of the comparator CMP and the other input terminal (+) of the fourth transistor M ₄ Drain of (d) sixth transistor M ₆ Drain of (c) and eighth transistor M ₈ Drain electrode connection of fifth transistor M ₅ Drain of (d) and ninth transistor M ₉ Drain of (d) seventh transistor M ₇ A drain electrode of the comparator CMP, one input terminal (-), a fourth transistor M ₄ Gate connection of fifth transistor M ₅ Source of (d) and third transistor M ₃ Drain of (c) eleventh transistor M ₁₁ Is connected to the drain of the transistor.

Sixth transistor M ₆ Drain of (c) and eighth transistor M ₈ Drain of the fourth transistor M ₄ A drain of the comparator CMP, another input terminal (+) of the comparator CMP, a fifth transistor M ₅ Gate connection of the sixth transistor M ₆ Gate of (c) and seventh transistor M ₇ Gate connection of the sixth transistor M ₆ Is applied with a power supply voltage V _core . Seventh transistor M ₇ Drain of (d) and ninth transistor M ₉ Drain of fifth transistor M ₅ A drain electrode of the comparator CMP, one input terminal (-), a fourth transistor M ₄ Gate connection of seventh transistor M ₇ Is applied with a power supply voltage V _core 。

Eighth transistor M ₈ The source of (a) is grounded, an eighth transistor M ₈ Drain of (d) and fourth transistor M ₄ Drain of (d) sixth transistor M ₆ A drain of the comparator CMP, another input terminal (+) and a fifth transistor M ₅ Is connected to the gate of the transistor. Ninth transistor M ₉ A source of (a) is grounded, a ninth transistor M ₉ Drain of (d) and fifth transistor M ₅ Drain of (d) seventh transistor M ₇ A drain electrode of the comparator CMP, one input terminal (-) of the comparator CMP and a fourth transistor M ₄ Is connected to the gate of the transistor.

Tenth transistor M ₁₀ A tenth transistor M having its source grounded ₁₀ Drain electrode of (d) and second transistor M ₂ Gate of (d), third transistor M ₃ Gate of (c) and eleventh transistor M ₁₁ Is connected to the source of the (c). Eleventh transistor M ₁₁ Drain of (d) and third transistor M ₃ And a fifth transistor M ₅ Source connection of eleventh transistor M ₁₁ Source electrode of (a) and second transistor M ₂ Gate of (d), third transistor M ₃ Gate of (c) and tenth transistor M ₁₁ Is connected to the drain of the transistor.

Twelfth transistor M ₀ Gate of (c) and first transistor M ₁ Is a gate of (2) Is applied with a read enable voltage V _read Eighth transistor M ₈ Gate of (d) and ninth transistor M ₉ Gate of (c) and tenth transistor M ₁₀ Is applied with a voltage V opposite to the read enable voltage _readn . Eleventh transistor M ₁₁ Is applied with a precharge voltage V _{sa_pre} Sixth transistor M ₆ Gate of (c) and seventh transistor M ₇ Is applied with a voltage V opposite to the pre-charge voltage _{sa_pren} 。

Wherein the read enable voltage V _read Voltage V opposite to the read enable voltage _readn Precharge voltage V _{sa_pre} Voltage V opposite to the precharge voltage _{sa_pren} Is set so that it can be read by the RRAM reading circuit to read the variable resistance of the RRAM _Rcell The resistance signal of (2) is converted into a signal which can be read.

In the present invention, it is preferable that the twelfth transistor M ₀ Specification of (d) and first transistor M ₁ Is the same in specification of the second transistor M ₂ Specification of (d) and third transistor M ₃ Is the same in specification of the fourth transistor M ₄ Specification of (d) and fifth transistor M ₅ Is the same in specification of a sixth transistor M ₆ Specification of (d) and seventh transistor M ₇ But the present invention is not limited thereto. And, preferably, the first transistor M ₁ Second transistor M ₂ Third transistor M ₁ Fourth transistor M ₄ Fifth transistor M ₅ Eighth transistor M ₈ Ninth transistor M ₉ Tenth transistor M ₁₀ Eleventh transistor M ₁₁ Twelfth transistor M ₀ Is an NMOS transistor, a sixth transistor M ₆ Seventh transistor M ₇ Is a PMOS transistor, but the invention is not limited thereto.

Next, a reading operation of the RRAM reading circuit according to an embodiment of the present invention will be described in detail. Fig. 4 is a waveform diagram showing a process of generating a comparison voltage in the RRAM read circuit according to an embodiment of the present invention.

Here, the twelfth transistor M ₀ Is of (2)Electrode and second transistor M ₂ The node between the sources of the first transistor M is set to L1 ₁ Drain of (d) and third transistor M ₃ The node between the sources of the fourth transistor M is set to L2 ₄ Drain of (d) and sixth transistor M ₆ A node between the drains of the fifth transistor M is set to L3 ₅ Drain of (d) and seventh transistor M ₇ A node between the drains of the second transistor M is set to L4 ₂ Gate of (d) and third transistor M ₃ The node between the gates of (c) is set to L5.

Specifically, in the present invention, the RRAM reading circuit performs the following steps when reading.

(1) First, a discharging step (corresponding to 0 to t1 in fig. 3) is performed. I.e. the read enable voltage V _read Set to a low voltage, voltage V to be inverted from the read enable voltage _readn Set to a high voltage, precharge voltage V _{sa_pre} Set to a low voltage, voltage V to be inverted to the precharge voltage _{sa_pren} Set to a high voltage so that the eighth transistor M ₈ Ninth transistor M ₉ Tenth transistor M ₁₀ Turned on to discharge the nodes L3, L4, and L5.

(2) Then, a precharge step (corresponding to t1 to t2 in fig. 3) is performed. I.e. the read enable voltage V _read Set to a high voltage, a voltage V which is to be inverted from the read enable voltage _readn Set to low voltage, precharge voltage V _{sa_pre} Set to a high voltage, a voltage V which is to be inverted from the precharge voltage _{sa_pren} Set to a low voltage so that the twelfth transistor M ₀ First transistor M ₁ Sixth transistor M ₆ Seventh transistor M ₇ Eleventh transistor M ₁₁ Turned on to charge node L3 and node L4 to the supply voltage and to charge node L5 to the clamp voltage.

(3) Then, a comparison step (corresponding to t2 to t3 in fig. 3) is performed. That is, the read enable voltage V _read Hold at high voltage, voltage V inverted to the read enable voltage _readn Hold at low voltage, precharge voltage V _{sa_pre} Set to low voltage to be precharged withVoltage V of voltage inversion _{sa_pren} Set to a high voltage so that the twelfth transistor M ₀ First transistor M ₁ Keep on, sixth transistor M ₆ Seventh transistor M ₇ Eleventh transistor M ₁₁ The disconnection is performed to compare the voltage difference formed between the node L3 and the node L4 by the comparator CMP.

In addition, after the comparison step, the read enable voltage V _read Set to a low voltage, voltage V to be inverted from the read enable voltage _readn Set to a high voltage to make the precharge voltage V _{sa_pre} Is kept at a low voltage, and a voltage V which is inverted from the precharge voltage _{sa_pren} The high voltage is maintained so that the current reading operation is ended and the next reading operation is started.

In particular, when the variable resistance R of RRAM _cell Resistance value of (2) is greater than reference resistance R _ref Has a resistance value of higher (R _cell >R _ref ) At this time, since the current flowing through the nodes L1 and L2 depends on R _cell And R is _ref Resistance size of (2) and thus form I after the precharge step _L1 <I _L2 So that the voltage of the node L4 drops faster than the voltage of the node L3, resulting in the transistor M ₅ Is conducted to a higher degree than the transistor M ₄ Further, the voltage drop rate of the node L3 is further slowed down, and the voltage drop of the final node L4 is insufficient to support the transistor M ₄ Is turned on, the voltage at node L3 remains constant, and node L4 passes through transistor M ₅ The remaining charge continues to be discharged. Thereby, a large pressure difference (L3 >L4) for comparison by the comparator CMP, so that the output signal D of the comparator CMP _out At a high level.

Variable resistance R when RRAM _cell Resistance value of (2) is greater than reference resistance R _ref Has a lower resistance value (R _cell <R _ref ) At this time, since the current flowing through the nodes L1 and L2 depends on R _cell And R is _ref Resistance size of (2) and thus form I after the precharge step _L1 >I _L2 So that the voltage of the node L3 drops at a higher rate than the nodeThe voltage at point L4 drops faster, resulting in transistor M ₄ Is conducted to a higher degree than the transistor M ₅ Further, the voltage drop rate of the node L4 is further slowed down, and the voltage drop of the final node L3 is insufficient to support the transistor M ₅ Is turned on, the voltage at node L4 remains constant, and node L3 passes through transistor M ₄ The remaining charge continues to be discharged. Thereby, a large pressure difference (L4>L3) for comparison by the comparator CMP, so that the output signal D of the comparator CMP _out At a low level.

Thus, the RRAM can be read by the RRAM reading circuit to change the variable resistance of the RRAM _Rcell The resistance signal of (2) is converted into a signal which can be read.

In the present invention, the variable resistor R of RRAM is as follows _cell The minimum value of the high resistance of (2) is R _H Variable resistor R of RRAM _cell The highest value of the low resistance of (2) is set as R _L The resistance of the reference resistor is set as R _ref The resistance of the reference resistor can be obtained by the following calculation formula:

further, as an example, the variable resistance R of the RRAM _cell The high resistance range of (2) is 500KΩ to 2MΩ, and the variable resistance R of RRAM _cell The low resistance range of (2) is 10KΩ to 100KΩ, but the present invention is not limited thereto. Further, the reference resistor preferably has a resistance of 167kΩ, but the present invention is not limited thereto.

Thus, according to the RRAM reading circuit of the invention, the process of reading RRAM resistance is mainly divided into two stages of a precharge stage and an amplifying comparison stage, and the precharge stage can form stable I rapidly due to the parasitic capacitance of the MOS transistor only _L1 、I _L2 And besides the power consumption of the comparator CMP, the structure of the RRAM read circuit of the present invention generates lower power consumption only in the precharge phase. In addition, in the amplifying comparison stage, the transistor M4 and the transistor M5 formThe cross-coupled MOS transistor pair can convert the current signal into the voltage signal through positive feedback, so that the reading margin can be increased, and the positive feedback conversion of the current voltage in the amplifying comparison stage accelerates the comparison process, so that the reading time can be shortened, and the reliability of RRAM reading data can be increased.

In addition, due to the reference resistance R _ref The present invention can also limit the voltages at the nodes L1 and L2 by setting the sizes of the transistors M1, M3, M5, and M7 to define the voltage at the node L5 in the precharge phase, and can prevent erroneous writing due to excessive voltage applied to the RRAM. In addition, since the voltage of the node L5 is discharged to 0V before the read enable voltage Vread is pulled up, a problem of erroneous writing due to the clamp voltage being raised does not occur. In addition, although node L5 is at V _{sa_pre} When pulled down, the floating point becomes floating, and the floating point is influenced by parasitic capacitance at the gate end to reduce the voltage, but the time for forming a sufficiently large voltage difference is very short due to the influence of positive feedback on the nodes L3 and L4, so that the influence caused by floating of the node L5 can be ignored.

In addition, in the RRAM reading circuit structure of the invention, the transistors M8, M9, M10 and M11 only need to complete the switching function, so that the minimum size area is adopted, and the occupied area of the RRAM reading circuit structure of the invention is smaller because no operational transconductance amplifier is arranged.

It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with one another. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the various embodiments of the invention without departing from the scope thereof. While the dimensions and types of materials described herein are intended to define the parameters of the various embodiments of the invention, the various embodiments are not meant to be limiting and are exemplary embodiments. Many other embodiments will be apparent to those of skill in the art upon reading the above description. The scope of the various embodiments of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Industrial applicability

The RRAM reading circuit and the reading method thereof can be applied to the reading of RRAM memories and the like.

Claims (11)

1. An RRAM read circuit, comprising:

a reference resistor;

the switch module is connected with the reference resistor and the variable resistor of the RRAM at one side and used for controlling the on-off of the reference resistor, the variable resistor of the RRAM and the self-bias module;

the self-bias module is connected with the other side of the switch module and used for clamping the voltage of a node between the self-bias module and the switch module in the pre-charging step;

a cross coupling module having one side connected to the other side of the self-bias module for amplifying the current difference value formed in the precharge step by positive feedback to be converted into a comparison voltage;

the precharge module is connected with the other side of the cross coupling module and is used for precharging the RRAM reading circuit; and

and the output module is connected with the other side of the cross coupling module and is used for comparing the comparison voltage amplified by the cross coupling module and outputting a comparison result.

2. The RRAM read circuit of claim 1, wherein,

the RRAM reading circuit performs the following steps when reading:

a discharging step for discharging a node between the output module and the cross-coupling module and a clamp node in the self-bias module;

a precharge step for charging a node between the output module and the cross-coupling module to a power supply voltage and charging the clamp node in the self-bias module to a clamp voltage; and

and a comparison step of amplifying the current difference value formed in the precharge step by positive feedback to convert it into a comparison voltage, comparing the comparison voltage amplified by the cross-coupling module, and outputting a comparison result.

3. The RRAM read circuit of claim 1, wherein,

the switching module includes a first transistor and a twelfth transistor,

the self-biasing module includes a second transistor, a third transistor, a tenth transistor, and an eleventh transistor,

the cross-coupling module includes a fourth transistor, a fifth transistor, an eighth transistor, and a ninth transistor,

The precharge module includes a sixth transistor and a seventh transistor,

the output module comprises a comparator which is arranged to compare,

the source of the twelfth transistor is connected with the variable resistor of the RRAM, the grid of the twelfth transistor is connected with the grid of the first transistor, the drain of the twelfth transistor is connected with the source of the second transistor,

the source of the first transistor is connected with the reference resistor, the drain of the first transistor is connected with the source of the third transistor,

the grid electrode of the second transistor is connected with the drain electrode of the tenth transistor, the source electrode of the eleventh transistor and the grid electrode of the third transistor, the drain electrode of the second transistor is connected with the source electrode of the fourth transistor,

the grid electrode of the third transistor is connected with the drain electrode of the tenth transistor, the source electrode of the eleventh transistor and the grid electrode of the second transistor, the drain electrode of the third transistor is connected with the drain electrode of the eleventh transistor and the source electrode of the fifth transistor,

the grid electrode of the fourth transistor is connected with one input terminal of the comparator, the drain electrode of the fifth transistor, the drain electrode of the seventh transistor and the drain electrode of the ninth transistor, the drain electrode of the fourth transistor is connected with the drain electrode of the eighth transistor, the drain electrode of the sixth transistor, the other input terminal of the comparator and the grid electrode of the fifth transistor,

The grid electrode of the fifth transistor is connected with the other input terminal of the comparator, the drain electrode of the fourth transistor, the drain electrode of the sixth transistor and the drain electrode of the eighth transistor, the drain electrode of the fifth transistor is connected with the drain electrode of the ninth transistor, the drain electrode of the seventh transistor, one input terminal of the comparator and the grid electrode of the fourth transistor, the source electrode of the fifth transistor is connected with the drain electrode of the third transistor and the drain electrode of the eleventh transistor,

the drain of the sixth transistor is connected to the drain of the eighth transistor, the drain of the fourth transistor, the other input terminal of the comparator, the gate of the fifth transistor, the gate of the sixth transistor is connected to the gate of the seventh transistor, the source of the sixth transistor is applied with a power supply voltage,

the drain of the seventh transistor is connected to the drain of the ninth transistor, the drain of the fifth transistor, one input terminal of the comparator, the gate of the fourth transistor, the source of the seventh transistor is applied with a power supply voltage,

the source electrode of the eighth transistor is grounded, the drain electrode of the eighth transistor is connected with the drain electrode of the fourth transistor, the drain electrode of the sixth transistor, the other input terminal of the comparator and the gate electrode of the fifth transistor,

The source electrode of the ninth transistor is grounded, the drain electrode of the ninth transistor is connected with the drain electrode of the fifth transistor, the drain electrode of the seventh transistor, one input terminal of the comparator and the gate electrode of the fourth transistor,

the source electrode of the tenth transistor is grounded, the drain electrode of the tenth transistor is connected with the grid electrode of the second transistor, the grid electrode of the third transistor and the source electrode of the eleventh transistor,

the drain of the eleventh transistor is connected with the drain of the third transistor and the source of the fifth transistor, the source of the eleventh transistor is connected with the gate of the second transistor, the gate of the third transistor and the drain of the tenth transistor,

a gate of the twelfth transistor and a gate of the first transistor are applied with a read enable voltage, a gate of the eighth transistor, a gate of the ninth transistor and a gate of the tenth transistor are applied with voltages opposite to the read enable voltage,

the gate of the eleventh transistor is applied with a precharge voltage, the gates of the sixth and seventh transistors are applied with voltages opposite to the precharge voltage,

The read enable voltage, the voltage opposite to the read enable voltage, the precharge voltage, and the voltage opposite to the precharge voltage are set so that reading can be performed with the RRAM read circuit to convert a resistance signal of a variable resistor of the RRAM into a signal that can be read.

4. The RRAM read circuit of claim 3,

a node between the drain of the twelfth transistor and the source of the second transistor is L1, a node between the drain of the first transistor and the source of the third transistor is L2, a node between the drain of the fourth transistor and the drain of the sixth transistor is L3, a node between the drain of the fifth transistor and the drain of the seventh transistor is L4, a node between the gate of the second transistor and the gate of the third transistor is L5,

the RRAM reading circuit performs the following steps when reading:

a discharging step of setting the read enable voltage to a low voltage, setting a voltage opposite to the read enable voltage to a high voltage, setting the precharge voltage to a low voltage, and setting a voltage opposite to the precharge voltage to a high voltage, so that the eighth transistor, the ninth transistor, and the tenth transistor are turned on to discharge L3, L4, and L5;

A precharge step of setting the read enable voltage to a high voltage, setting a voltage opposite to the read enable voltage to a low voltage, setting the precharge voltage to a high voltage, setting a voltage opposite to the precharge voltage to a low voltage, and turning on the twelfth transistor, the first transistor, the sixth transistor, the seventh transistor, and the eleventh transistor to charge L3 and L4 to a power supply voltage and to charge L5 to a clamp voltage; and

and a comparison step of maintaining the read enable voltage at a high voltage, maintaining a voltage opposite to the read enable voltage at a low voltage, setting the precharge voltage at a low voltage, and setting a voltage opposite to the precharge voltage at a high voltage, so that the twelfth transistor, the first transistor, and the sixth transistor, the seventh transistor, and the eleventh transistor are turned off to compare a voltage difference formed between L3 and L4 by the comparator.

5. The RRAM read circuit of claim 4, wherein,

in the comparing step, when the resistance of the variable resistor of the RRAM is lower than the resistance of the reference resistor, the voltage drop rate of L4 is faster than the voltage drop rate of L3; when the resistance of the variable resistor of the RRAM is higher than that of the reference resistor, the voltage of L3 drops faster than that of L4.

6. The RRAM read circuit of any one of claims 1-5, wherein,

to the RRAMThe minimum value of the high resistance of the variable resistor is R _H The highest value of the variable resistance of the RRAM is R _L Setting the resistance of the reference resistor as R _ref ，

The resistance of the reference resistor is obtained by the following calculation formula:

。

7. the RRAM read circuit of claim 6, wherein,

the variable resistance of the RRAM has a high resistance interval of 500KΩ to 2MΩ, and the variable resistance of the RRAM has a low resistance interval of 10KΩ to 100KΩ.

8. The RRAM read circuit of claim 7, wherein,

the resistance value of the reference resistor is 167KΩ.

9. The RRAM read circuit of any one of claim 3-5,

the twelfth transistor has the same specifications as the first transistor,

the second transistor has the same specifications as the third transistor,

the fourth transistor has the same specifications as the fifth transistor,

the specification of the sixth transistor is the same as that of the seventh transistor.

10. The RRAM read circuit of any one of claim 3-5,

The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor are NMOS transistors, and the sixth transistor, the seventh transistor are PMOS transistors.

11. A method of reading an RRAM read circuit, the RRAM read circuit comprising:

a reference resistor;

the switch module is connected with the reference resistor and the variable resistor of the RRAM at one side and used for controlling the on-off of the reference resistor, the variable resistor of the RRAM and the self-bias module;

the self-bias module is connected with the other side of the switch module and used for clamping the voltage of a node between the self-bias module and the switch module in the pre-charging step;

a cross coupling module having one side connected to the other side of the self-bias module for amplifying the current difference value formed in the precharge step by positive feedback to be converted into a comparison voltage;

the precharge module is connected with the other side of the cross coupling module and is used for precharging the RRAM reading circuit; and

The output module is connected with the other side of the cross coupling module and is used for comparing the comparison voltage amplified by the cross coupling module and outputting a comparison result,

the RRAM reading circuit performs the following steps when reading:

a discharging step for discharging a node between the output module and the cross-coupling module and a clamp node in the self-bias module;

a precharge step for charging a node between the output module and the cross-coupling module to a power supply voltage and charging the clamp node in the self-bias module to a clamp voltage; and

and a comparison step of amplifying the current difference value formed in the precharge step by positive feedback to convert it into a comparison voltage, comparing the comparison voltage amplified by the cross-coupling module, and outputting a comparison result.