CN117744546A

CN117744546A - Digital circuit evaluation method, system, equipment and storage medium

Info

Publication number: CN117744546A
Application number: CN202410192969.7A
Authority: CN
Inventors: 李明
Original assignee: Shenzhen Shanhai Semiconductor Technology Co ltd
Current assignee: Shenzhen Shanhai Semiconductor Technology Co ltd
Priority date: 2024-02-21
Filing date: 2024-02-21
Publication date: 2024-03-22
Anticipated expiration: 2044-02-21
Also published as: CN117744546B

Abstract

The application relates to a digital circuit evaluation method, a digital circuit evaluation system, digital circuit evaluation equipment and a digital circuit storage medium, and belongs to the technical field of data processing. The method comprises the following steps: acquiring a digital circuit description file; analyzing the digital circuit description file to obtain resource analysis information; calculating load capacity data of the resource based on the load information; analyzing a file in a standard unit based on the load capacity data and/or attribute information of each resource to match the corresponding standard unit and the number thereof for each resource; acquiring area parameter data of the matched standard unit from the standard unit analysis file, and calculating to obtain the estimated area of the digital circuit based on the area parameter data and the matched number; when the standard process library is not determined, the analysis information and the load capacity data of each resource are recorded to generate a resource statistical file. The method and the device can estimate the area of the target digital circuit in the initial design stage, are high in processing speed, accurate in estimated result and free from being influenced by artificial experience.

Description

Digital circuit evaluation method, system, equipment and storage medium

Technical Field

The present disclosure relates to the field of data processing technologies, and in particular, to a method, a system, an apparatus, and a storage medium for evaluating a digital circuit in the field of integrated circuits.

Background

An integrated circuit (Integrated Circuit, abbreviated as IC) is also called a chip, and the circuits in the chip are divided into an analog circuit and a digital circuit according to the types of signals handled by the circuits in the chip, and are counted at the time of design. In the initial stage of chip design, not only the architecture performance needs to be evaluated at the system level, but also the area of the chip needs to be estimated, so that the area of the wafer required in manufacturing is estimated, and the preparation cost of the chip is estimated. As the specific gravity of digital circuits in chip circuits increases with the development of large-scale integrated circuits, the area of digital circuits has an increasing impact on the manufacturing cost of chips.

Currently, the estimation of the digital circuit area is usually performed by a professional EDA (Electronics Design Automation, electronic design automation) synthesis tool, and configuration parameters such as a process library, constraints, etc. used in design (for example, some parameters such as clock frequency, driving capability, etc. when mapping the circuit description to a standard cell) are input to the EDA synthesis tool, and the digital circuit area is calculated by the EDA synthesis tool. However, the prediction method needs to obtain better effects when the design is completed or the constraint file is already available, the process library and other conditions are determined, however, in the initial stage of the design, under the condition that the process is not yet determined and the constraint file is not available, extra time is required to determine relevant information such as configuration parameters and constraint files required by the EDA comprehensive tool, so that extra workload is increased, the consistency of the information content provided currently and the information content after the final design is difficult to ensure, the accuracy of the prediction cannot be ensured, the time cost is increased, and the design period is prolonged. Another approach relies on the experience of engineers who themselves roughly estimate the resources to be used, e.g. standard cells, IP libraries etc. applied, from their design logic, by querying the areas provided in these resources to estimate the digital circuit area they are designing. However, the method depends on the familiarity of engineers with mapping hardware description languages into circuits to a great extent, and the results tend to vary from person to person, so that the reliability is not high.

Disclosure of Invention

Aiming at the technical problems in the prior art, the application provides a digital circuit evaluation method, a system, equipment and a storage medium, which can evaluate the area of a digital circuit in the initial stage of integrated circuit design, and has high processing speed and high reliability.

To solve the above technical problem, according to one aspect of the present application, there is provided a digital circuit evaluation method, including the steps of:

acquiring a digital circuit description file generated by adopting a digital circuit description language;

analyzing the digital circuit description file to at least obtain the resources and attribute information of the resources applied in the digital circuit;

when the attribute information comprises resource load information, calculating to obtain load capacity data of the resource based on the resource load information;

when a standard process library is determined and a standard unit analysis file of the standard process library is provided, matching corresponding standard units and the number thereof for each resource in the standard unit analysis file based on the load capacity data and/or attribute information of each resource in the digital circuit;

the method comprises the steps of obtaining area parameter data of a matched standard unit from a standard unit analysis file, and calculating an area value corresponding to each resource based on the area parameter data and the number of the matched standard units;

Calculating area values of all resources to obtain the estimated area of the digital circuit; and

and when the standard process library is not determined, recording the analyzed resources, the attribute information and the load capacity data of the resources applied in the digital circuit to generate a resource statistical file.

Optionally, the step of parsing the digital circuit description file includes:

traversing the digital circuit description file, and identifying the resources applied in the digital circuit from the circuit description code according to preset resource keywords;

determining corresponding preset attribute keywords based on the identified resources; and

traversing the digital circuit description file, and identifying the attribute information of the resource from the circuit description code based on preset attribute keywords.

Optionally, the resource keywords are preset keywords according to the characteristics of the digital circuit description language and the description rules of the resources, and a plurality of preset resource keywords are combined together to meet the specific condition of determining the preset resources; the attribute keywords are one or more, and a plurality of preset attribute keywords are combined together to meet the specific condition for determining the related attribute of the preset resource.

Optionally, when the preset attribute key includes a resource output key, the step of identifying attribute information of the resource from the circuit description code based on the preset attribute key includes:

Identifying the load and the type of the resource in the digital circuit description code based on the resource output keyword;

correspondingly, the step of calculating based on the resource load information to obtain the load capacity data of the resource comprises the following steps: and counting the load, the type and the number of the resources.

Optionally, the resources include one or more of a plurality of types of memory cells, a plurality of types of logic gates, and a plurality of types of selectors.

Optionally, the step of parsing the digital circuit description file further includes:

traversing the digital circuit description code based on a preset constraint mark;

when the digital circuit description code is matched with the corresponding constraint mark, acquiring a module name corresponding to the constraint mark and taking the module name as the identified resource;

setting the attribute information of the identified resources as an IP module; and

the statistical attribute information is the number of resources of the same module name of the IP module.

Optionally, when the standard process library is determined and the standard unit parsing file of the standard process library is not provided, further comprising:

acquiring a parameter file in the standard process library;

analyzing the parameter file to obtain a standard unit and attribute parameter data thereof and generating a standard unit analysis file, wherein the attribute parameters at least comprise an area parameter and a load capacity parameter.

To solve the above technical problem, according to another aspect of the present application, there is provided a digital circuit evaluation system, including:

a file acquisition module configured to acquire a digital circuit description file generated using a digital circuit description language;

the analysis processing module is configured to analyze the digital circuit description file to at least obtain resources and attribute information of the resources applied in the digital circuit; when the attribute information comprises resource load information, calculating to obtain load capacity data of the resource based on the load information;

the matching processing module is configured to match corresponding standard units and the quantity thereof for each resource in the standard unit analysis file based on the load capacity data and/or attribute information of each resource in the digital circuit when the standard process library is determined and the standard unit analysis file of the standard process library is provided; and

the result processing module is configured to record the resources and attribute information thereof applied in the digital circuit obtained by analysis and the load capacity data to generate a resource statistical file when the standard process library is not determined; when a standard process library is determined, area parameter data of the matched standard units are obtained, and area values corresponding to each resource are calculated based on the area parameter data and the number of the matched standard units; and calculating the area values of all the resources to obtain the estimated area of the digital circuit.

Optionally, the digital circuit evaluation system further comprises an interaction module configured to provide a user interaction interface, determine the digital circuit description file from the specified location based on a file import operation by the user.

To solve the above technical problem, according to one aspect of the present application, there is provided an electronic device, including a processor and a memory, where a set of computer readable program instructions is stored, the processor implementing the aforementioned digital circuit evaluation method when executing the set of computer readable program instructions.

To solve the above technical problem, according to one aspect of the present application, there is provided a computer-readable storage medium in which a set of computer-readable program instructions is stored, which when executed by a processor, implements the aforementioned digital circuit evaluation method.

To solve the above technical problem, according to one aspect of the present application, there is provided a computer program product comprising a set of computer program instructions which, when executed by a processor, implement the digital circuit evaluation method described above.

In the initial design stage of the digital circuit, the digital circuit can be evaluated after the digital circuit description code is finished, in the evaluation process, the area of the target digital circuit can be estimated when the standard unit process is determined, and the design work is not required to be completed completely, so that the area of the target digital circuit can be estimated in the initial design stage, and reference data is provided for the estimation of the manufacturing cost; because the evaluation method in the application mainly processes the text file, the processing speed is high compared with an EDA comprehensive tool; in the method, the digital circuit description file is analyzed for evaluation, the mapping between the circuit and the standard unit is realized, and the personal experience of an engineer is not relied on, so that the estimated area is not interfered by artificial experience, the estimated result is accurate, and the reliability is high.

Drawings

Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:

FIG. 1 is a flow chart of a digital circuit evaluation method according to one embodiment of the present application;

FIG. 2 is a partial schematic diagram of a method flow of parsing a digital circuit description file according to one embodiment of the present application;

FIG. 3 is another partial schematic diagram of a method flow of parsing a digital circuit description file according to one embodiment of the present application; and

fig. 4 is a schematic diagram of a digital circuit evaluation system according to one embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. For the purpose of illustration only, the connection between elements in the figures is meant to indicate that at least the elements at both ends of the connection are in communication with each other and is not intended to limit the inability to communicate between elements that are not connected. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the output terminals provided, and is not intended to limit the communication between the two units to only signals as shown in the figures.

The application provides a digital circuit evaluation method, a digital circuit evaluation system, an electronic device and a storage medium, wherein the electronic device is any device with a processor and a memory, and the digital circuit evaluation system is installed in the electronic device, and the digital circuit evaluation method is realized through the digital circuit evaluation system. The electronic equipment is provided with an interaction device, such as a display and an input keyboard, so that a user can interact with the digital circuit evaluation system, and the digital circuit evaluation system can display corresponding data, such as an interaction interface, result data and the like, through the interaction device based on the instruction sent by the interaction device and corresponding data, files and the like.

FIG. 1 is a flow chart of a digital circuit evaluation method according to one embodiment of the present application, the method comprising the steps of:

step S11, a digital circuit description file generated by using a digital circuit description language is acquired.

And step S12, analyzing the digital circuit description file to obtain resource analysis information, wherein the resource analysis information at least comprises resources applied in the digital circuit description and attribute information of the resources.

Step S13, calculating the load capacity data of the resource based on the resource load information in the attribute information.

Step S14, judging whether the standard process library is determined, if the standard process library is determined, executing step S15, and if the standard process library is not determined, executing step S21.

Step S15, judging whether a standard unit analysis file of the standard process library exists, if so, executing step S16, and if not, executing step S19.

Step S16, analyzing the file in the standard units based on the load capacity data and/or attribute information of each resource to match the corresponding standard units and the quantity thereof for each resource.

And S17, acquiring area parameter data of the matched standard units, and calculating an area value corresponding to each resource based on the area parameter data and the matched quantity.

And S18, calculating area values of all resources to obtain the estimated area of the digital circuit, and ending the evaluation flow.

And S19, acquiring a parameter file in the standard process library.

Step S20, analyzing the parameter file to obtain the standard unit and the attribute parameter information thereof and generating a standard unit analysis file, and returning to step 16.

And S21, recording the analysis information and the load capacity data of each type of resource to generate a resource statistical file, and ending the evaluation flow.

In step S11, the digital circuit description file is a text file generated by a digital circuit designer using a digital circuit description language, where the digital circuit is described by using a code in text form according to the grammar and rules of the digital circuit description language, so that the circuit description code includes the device name of the digital circuit application and various operators, logic symbols, relational symbols, and the like for indicating the connection relation and logic relation of the devices. In one embodiment, a digital circuit designer writes digital circuit description codes according to design targets (such as circuits with certain functions for processing digital signals, hereinafter referred to as target digital circuits), and stores the digital circuit description codes in corresponding positions in the form of files, and one or more digital circuit description files can be generated according to design requirements. When the digital circuit description file is acquired, a plurality of corresponding digital circuit description files can be sequentially read according to the storage address. In another embodiment, when a plurality of digital circuit description files are generated for a corresponding target digital circuit, the storage addresses of all digital circuit description files are stored in a single file list, in which all digital circuit description file names and their storage addresses are recorded. Thus, when the digital circuit description files are acquired, the names and the storage addresses of the digital circuit description files are obtained from the file list, and all the digital circuit description files are read at one time.

Since the digital circuit description file is a text file, and the digital circuit description language, such as Verilog or VHDL, is a language with standard grammar specifications, in order to determine the applied resources from the digital circuit description file, keywords for determining different kinds of resources are preset according to the characteristics of the digital circuit description language and the description rules of various resources. The resources described in this application are, for example, registers or latches as storage units, or various logic gates, or various IP blocks of application, or selectors, etc., and these resources are combined together according to a certain logic relationship to form the target digital circuit. According to the description language characteristics of the digital circuit and the description rules of the preset resources, one or more keywords are preset, the keywords used for determining specific resources are called resource keywords, and a plurality of resource keywords are combined together to meet the specific condition for determining the resource. In addition, because different resources have different roles and uses in the digital circuit, even though the resources of the same type have different corresponding areas in different application scenes, and therefore, attribute keywords corresponding to various resources and meeting the corresponding attributes of the various resources are preset in the application. The attributes of the resource are, for example, the bit width of the register, the input and number of selectors, the input number of AND gates or adders, the load used for the connection and its type, etc.

When the digital circuit description file is parsed in step S12, the digital circuit description file is traversed first, and when a resource corresponding to a preset resource keyword is identified from the digital circuit description code according to the preset resource keyword, the digital circuit description code is queried based on a preset attribute keyword corresponding to the preset resource to obtain attribute information of the resource. In one embodiment, a plurality of resource keywords for determining a preset resource form a resource keyword group, and a plurality of attribute keywords for determining attributes corresponding to each preset resource form an attribute keyword group, wherein the attribute keyword group corresponds to the resource keyword group.

FIG. 2 is a partial schematic diagram of a method flow for parsing a digital circuit description file to obtain resources according to one embodiment of the present application. The method comprises the following steps:

in step S121, the target vocabulary number is set to 1. In order to traverse the circuit description codes (e.g., english words) in the digital circuit description file, each word has a corresponding sequence number, and the sequence number of the first word is 1. By setting the target vocabulary number to 1, the traversal process starts with the first vocabulary of the circuit description code.

Step S122, reading the description words with the corresponding serial numbers from the text of the digital circuit description file according to the serial numbers to serve as target words.

Step S123, comparing the target vocabulary with the resource keywords in the preset resource keyword list one by one.

Step S124, it is determined whether a resource keyword is matched, if a resource keyword (referred to herein as a first resource keyword for convenience of description) is matched, step S125 is executed, if not, step S1281 adds 1 to the target vocabulary number, and step S1282 determines whether there is a vocabulary corresponding to the number in the digital circuit description file, if yes, step S122 is returned, if not, the description is completed, and if not, the analysis is ended.

Step S125, recording the resource keywords and the corresponding target vocabulary.

Step S126, judging whether the same group of resource keywords are not compared. In order to determine a specific resource, a plurality of resource keywords are generally provided, and these resource keywords are combined to form a condition that one resource is determined. Thus when a resource keyword is matched, it is necessary to determine whether there is the same set of resource keywords. If so, then in step S1261, one is determined from the same set of resource keywords as a second resource keyword, and then step S1262 is performed. If there is no same set of resource keywords, in step S127, a specific resource is determined based on the recorded resource keywords and the corresponding target vocabulary based on the satisfied conditions, and step S128 is performed.

Step S128, judging whether the corresponding attribute key words are present. Typically, a resource is accompanied by corresponding attribute information, so that when a keyword is preset, each resource is further configured with an attribute keyword to analyze specific attribute information. Thus, when a resource is determined, whether there is an attribute keyword is determined by querying the keyword configuration table, if yes, step S1291 is performed, and if not, it is indicated that the currently matched resource has already been parsed into all the required information, and then the parsing of the digital circuit description file is continued, i.e., step S1281 is performed.

Step S1262, add 1 to the target vocabulary sequence number.

Step S1263, determining whether the digital circuit description file has a vocabulary corresponding to the serial number, and if so, executing step S1264. If not, the current circuit description is incomplete, and the corresponding resource cannot be judged, then in step S1268, the analysis failure of the current vocabulary is confirmed, and an error prompt message is generated.

Step S1264, reading the descriptors with the corresponding serial numbers from the digital circuit description file according to the serial numbers to serve as target words.

Step S1265, comparing the target vocabulary with the second resource keyword.

Step S1266, determine whether the two match, and if not, return to step S1262. If so, in step S1267, the target vocabulary corresponding to the second resource keyword is recorded, and step S126 is returned to determine whether there are any uncompared same-group resource keywords.

Referring to fig. 3, fig. 3 is another partial schematic diagram of a method flow of parsing a digital circuit description file according to one embodiment of the present application. In step S1291, one is determined as the target attribute keyword from among the attribute keywords.

In step S1292, the target vocabulary number is set to 1. I.e. matching attribute keywords from scratch, parsing its attribute information for the currently determined resource.

And step S1293, acquiring the target vocabulary according to the sequence number and comparing the target vocabulary with the target attribute keywords.

Step S1294, judging whether the two are matched, if so, executing step S1295. If not, step S1297 is performed.

And step S1295, recording the target attribute keywords and the target vocabulary.

Step S1296, judging whether there is not any matching attribute keyword, if yes, returning to step S1291. If not, returning to the step S1281, and continuing to determine the next vocabulary for resource analysis.

In step S1297, the target vocabulary number is incremented by 1.

Step S1298, judging whether the vocabulary of the sequence number exists. I.e. whether all digital circuit description files have been matched. If the vocabulary of the sequence number is available, the description is not matched, and the process returns to step S1293. If not, it is indicated that all the matched digital circuit description files are still not matched with the corresponding attribute information for the preset attribute keywords, in one embodiment, if not, the matching failure of the attribute is determined in step S1299, error prompt information is generated, and then step S1281 is returned to continuously determine the next vocabulary for resource analysis. In addition, when one attribute of the resource needs to be determined by a plurality of information meeting a certain condition, and a plurality of target words corresponding to a plurality of attribute keywords are analyzed, specific attribute information is determined according to the condition that the target words are combined together.

In addition, the resource keywords or the attribute keywords applied in the parsing process can be preset keywords, or the recognized vocabulary can be used as keywords required for matching resources or obtaining attributes according to the requirements in the parsing process. For example, in step S125, when one of the circuit description codes corresponds to a vocabulary of the resource, such as a register name, in order to determine a specific type of the register, it is further necessary to continue matching according to other keywords corresponding to the register type, and at this time, the parsed register name (the previously parsed code vocabulary) is used as an auxiliary keyword. The same processing method is also used for analyzing the attribute of the resource.

And traversing the digital circuit description file by using the resource keywords and the attribute keywords so as to analyze and obtain the resource and the attribute information thereof.

In the attribute of the resource, the load capacity is an important factor affecting the area of the device, so that the attribute keywords include resource output keywords for determining the load capacity, and when traversing the digital circuit description file based on the resource output keywords, the obtained attribute information is the load information of the resource, such as the load and the type, that is, the attribute information recorded in step S1295 is the resource load information. At this time, in step S13, the load capacity data of the resource may be obtained by counting the load of the resource, the type and the number of the resource.

The parsing process in step S12 is described below taking the register circuit description code written in the standard verilog language shown in table 1 as an example:

TABLE 1

For verilog language, when the register set based on the characteristics of the language description storage unit is a resource, the corresponding resource keyword comprises 'reg', and according to a grammar rule, the register name is the later, so when the content of line 1 is analyzed, the analysis to the storage unit is determined based on the keyword 'reg', and 'dout' is used as the name of the storage unit, and in order to analyze the attribute, such as bit width, the 'dout' is used as an auxiliary keyword used when analyzing the bit width attribute, and the bit width definition word or symbol is used as an attribute keyword. Since memory cells in digital circuits can be divided into registers and latches, registers are in turn divided into two types, reset set type and asynchronous reset set type. Thus when resolving the resulting resource as a memory location, it is first necessary to determine whether it is a register or a latch. The application is also provided with the following resource keywords, such as: "always" followed by a list of signal sensitivities in brackets; keywords representing signal names, such as "clk", "rst_n", and keywords representing signal edges, such as "posedge" and "negedge"; an "if-else" structure and an "if" structure representing a condition. In the present application, when the "if-else" structure is resolved from the circuit description code, the storage unit is determined to be a register, and when the "if" structure is resolved from the circuit description code, the storage unit is determined to be a latch. In this embodiment, since the "if-else" structure is obtained from the above in parsing from line 2, the memory cells in this embodiment are registers. Then, in order to determine which type of register the register is, the present application determines the register type based on the conditions under which the corresponding attribute key is combined. For example, the condition for asynchronously resetting the set register is satisfied when two signals "rst_n" and "set" are included in the circuit description code and assigned to "1" and "0", respectively. The resource of the asynchronous reset set register is thus determined for this embodiment by parsing the contents of table 1.

In another embodiment, see the circuit description code written in the standard verilog language shown in table 2.

TABLE 2

The circuit description code is a section of the following code in table 1, and a register named dout_load and a circuit network of dout_load2 are obtained based on the parsing method. For registers, its resource output key includes, for example, an assignment symbol and a register name. For example, in table 2, when traversing the code, the assignment symbol and the register names "dout" and "dout_load" are obtained in the content of line 7, and the load of the register "dout_load" is determined as the load of the register "dout" according to the meaning of the assignment symbol. In the same way, in line 9, the register "dout" and the register "din" and the and operation are obtained based on the keywords "dout" and "din" and the and gate symbol "&", and thus it can be determined that the register "dout" is applied in the and gate so that the two-input and gate acts as the load of the register "dout". Combining table 2 and table 1 results in the resolved register "dout" in table 1 having a register load named "dout_load" and a two-input and gate load, respectively.

Table 3 is a piece of logic gate description code, and the analysis process is described as follows:

TABLE 3 Table 3

The resource keywords used for determining the resource of the logic gate comprise ' assignment ' and ' always@and when the two words are included in the circuit description code, the logic gate is determined and obtained, and the bit width information of the current logic gate is obtained based on the bit definition keywords. To determine which logic gate is specific, a corresponding vocabulary expressing the logic relationships is derived from the current circuit description code based on preset arithmetic operators, relational operators, and logical operators, and the specific logic gate is determined based on the logic conditions that these vocabularies meet. From the sign "+" in the first row and the parsed register "dout" and its 1 bit width, it can be determined that there is a 1 bit adder, the adder result being represented by "data"; according to the AND operator "&" and/or the operator "|" in the third row, it is determined that there is a two-input AND gate and a two-input OR gate, respectively. Through the above analysis, the circuit description code in table 3 includes a 1-bit adder, a two-input and gate, and a two-input or gate.

For an adder, in one embodiment, the result is used as a resource output keyword, and when the adder result data is identified in the two-input or gate input in the third row while traversing the codes in table 3, the two-input or gate is determined to be the load of the adder. Similarly, by analyzing the subsequent code, when the "valid" in the third row is applied in the subsequent code, it can be determined that the load is the load of the two-input AND gate analyzed here, and the load type can be determined according to the specific code analyzed to use the "valid".

Table 4 is a section of selector circuit description code, and the parsing process is described as follows:

TABLE 4 Table 4

When analyzing the content of line 1 of table 4, the present resource is a selector of two alternatives based on the terms "assign", "result" and "sel. The attribute of the selector is, for example, bit width, and the bit width information of "a" and "b" in this embodiment can be obtained by traversing the circuit description code using the bit width keyword, and is used as the attribute information of the alternative selector.

For the content of line 2, the current content is determined to be an always block according to a preset resource keyword 'always', and when the content in brackets is analyzed, whether the current circuit is a time sequence circuit or a combination circuit can be determined. When the content in brackets includes the keyword "pore" or "negedge", it is determined that the current circuit is a sequential circuit. When the contents in parentheses include the symbol "×" or a specific variable name, then it is combinational logic.

For the content of line 3, determining that the current content is a content conforming to the case grammar according to a preset resource keyword "case", further analyzing to obtain a selector based on keywords such as bracket content, branch expression, execution statement and the like set by the content required by the case statement, and determining that the current content is a selector of n-choice 1 based on the bit width (n) of the analyzed "sel 2".

When the subsequent step S16 matches the standard selector for the selector, the number of selectors is determined according to the bit width information. For example, when the standard selector has only one of two selectors, the number N of one of two selectors corresponding to the parsed selector bit width N is calculated by the following formula:

N=2^0+2^1+…+2^(n-1)。

similarly, the parsing method of other resources in the digital circuit description file is the same, and will not be described here again.

In integrated circuit designs, in addition to describing specific circuits using hardware circuit description language, certain circuit modules in an IP library are often used in the form of IP module calls. Since the circuit modules of the IP library are already encapsulated circuit modules, in which the area parameters are provided, for this case only the IP module used need to be determined during the parsing.

In one embodiment, the parsing of the digital circuit description file further comprises:

traversing codes in the digital circuit description file based on preset constraint marks;

In the process of writing digital circuit description codes, when calling the IP module, a user sets constraint marks in the codes, for example, constraint marks of the IP module are obtained by/balck box. Thus, when the constraint mark/balck box is matched, the module name corresponding to the constraint mark/balck box is used as the identified resource and used as the IP module when the code in the digital circuit description file is traversed when the digital circuit description file is analyzed.

In one embodiment, after parsing of the digital circuit description code is completed, the parsed content is stored as a file, which includes the parsed resource and its attribute information.

In step S13, the resource output information of each resource is extracted from the attribute information, and based on the characteristics of the resource, the resource output information is calculated by adopting a corresponding calculation method to obtain the load capacity data.

For example, for a register, its load and corresponding load type are determined based on the scenario in which the register is applied, such as the register load and the two-input or gate load obtained in table 1 above. In one embodiment, the number of times a register is used may be used as the load capability data, so that the load capability of the register is obtained by counting the number of times a register is called. For a selector, its number of other resources to output connections is taken as its load capacity.

When the user does not determine the preparation process for the currently designed digital circuit, that is, does not determine the standard process library, the analysis information obtained in the step S12 and the load capacity data obtained in the step S13 are combined together to generate a resource statistical file, and the resource statistical file is stored or provided for the user.

When a user determines a preparation process for a currently designed digital circuit, i.e., a standard process library, the area of the currently designed digital circuit is estimated based on the standard process library.

The standard process library has many files, such as a circuit netlist, a parameter file and the like, wherein the parameter file is a text file, library information such as version, date and various data units are recorded, and information such as name, area, input/output drive or load size of each standard unit is recorded. In view of the present application, it is only necessary to estimate the area, and thus the relevant library information described in the parameter file, as well as the area parameters of the standard cells and the relevant parameters affecting the determined area, such as load data. When the method is applied to area estimation for the first time, the parameter file is analyzed according to the determined standard process library to obtain a standard unit analysis file, and standard units, area parameter data thereof, load and other area-related parameter data are recorded in the standard unit analysis file.

For example, library information extracted from one parameter file includes date (date), version (version), default input capacity value (default input pin cap), default output capacity value (default inout pin cap), and (default output load capacity) default fanout Load. The first two are used to record information of the library for the user, and the last three default parameters are used when some units do not give specific parameters.

The standard cells in the parameter file start with cells, and the relevant parameters of the standard cells are recorded, for example, the relevant parameter data of one of the following standard inverters:

cell (INVX20AS6){

cell footprint : "INV";

area : 48.921600;

……

pg_pin (VCCK) {

pg_type : primary_power;

voltage name: "VCCK";

}

pin (O) {

direction :"output"

……

max capacitance : 2.934958;

timing () {

related pin :"I":

……

}

pin (I) {

direction :"input";

……

capacitance : 0.0427213;

……

}

in extracting the above-described parameter data, similarly to the analysis of the digital circuit description file, a keyword such as the aforementioned inverter is preselected for the analysis of necessary parameters from the parameter file of the standard cell library, and the preset keyword is, for example, "capacity" in "max capacity" in "cell", "area", "pin (O)", and "capacity" in "pin (I)". When these keywords are matched from the parameter file, the latter contents are read, such AS "INVX20AS6" after "cell", "48.921600" after "area", "2.934958" after "max capability", and so on. The "48.921600" after "area" is area data, the unit is micron, "max capacitance" is driving capability of the output pin, and the unit is picofarad after "2.934958" is capacitance value.

In one embodiment, a front-to-back strategy is adopted in the parsing process, basic information of a library is matched, then information such as name, area, load and the like of each standard cell (cell) is matched, the information is recorded in an internal cvs file, and each standard cell occupies one row, so that a standard cell parsing file is obtained. The same analysis method can be adopted to analyze the corresponding standard unit analysis files for different standard process libraries, so that the analysis files are convenient to use in evaluation.

In step S16, the content in the reference standard cell analysis file is the standard cell and number corresponding to the analyzed resource, based on the content analyzed by the digital circuit description file and the calculated load data. For example, when the digital circuit description file is parsed into the inverter (hereinafter referred to as a target inverter), the input pin data and the output pin data in the attribute information are compared with the inverter (hereinafter referred to as a standard inverter) parameter data in the standard cell, and when a condition that the input data of the standard inverter is greater than the input data of the target inverter and the output data of the standard inverter is greater than the output data of the target inverter is satisfied, the current standard inverter is determined as an optional cell, and if the standard cell parse file has a plurality of inverters of different attributes, the target inverter is compared with the standard inverter one by one according to the condition. When a plurality of inverters meeting the condition are obtained, a standard inverter with the smallest comparison time difference value can be determined to realize the device of the target inverter.

In another embodiment, when the digital circuit description file is parsed into a selector with a bit width N, and only one selector is selected from the standard cell process library, the number of the required one selectors is calculated according to the formula n=2ζ0+2ζ1+ … +2ζ1.

After the corresponding standard units and the quantity thereof are matched for the analyzed resources, the area parameter data of the standard units are read, and the estimated area of the current digital circuit can be calculated.

Through the digital circuit evaluation method, the area of the target digital circuit can be estimated when the standard unit process is determined, the whole design is not required to be completed, the area of the target digital circuit can be estimated only in the initial design stage, and reference data is provided for the estimation of the manufacturing cost; because the evaluation method in the application mainly processes the text file, the processing speed is high compared with an EDA comprehensive tool; the evaluation method in the application realizes the mapping of the circuit and the standard unit through the analysis of the digital circuit description file, and does not depend on personal experience of engineers any more, so that the estimated area is not interfered by artificial experience any more, and the estimated result is accurate.

In another aspect, the present application also provides a digital circuit evaluation system, see fig. 4, which is a schematic diagram of the digital circuit evaluation system according to one embodiment of the present application. In this embodiment, the digital circuit evaluation system includes a file acquisition module 11, an analysis processing module 12, a matching processing module 13, and a result processing module 14, where the file acquisition module 11 is configured to acquire a digital circuit description file generated using a digital circuit description language. The parsing module 12 is configured to parse the digital circuit description file to obtain resource parsing information, where the resource parsing information includes at least resources identified from the digital circuit description file and attribute information of the resources; when the resource load information is included in the attribute information, load capacity data of the resource is calculated based on the load information. The matching processing module 13 is configured to, when a standard process library is determined and a standard unit analysis file of the standard process library is provided, match, for each resource, a corresponding standard unit and the number thereof in the standard unit analysis file based on the load capability data and/or attribute information of each resource. The result processing module 14 is configured to connect with the parsing processing module 12 when the standard process library is not determined, record parsing information and load capacity data of each resource, and generate a resource statistics file; when the standard process library is determined, the area parameter data of the matched standard units are acquired, and the area value corresponding to each resource is calculated based on the area parameter data and the matched quantity; and calculating the area values of all the resources to obtain the estimated area of the digital circuit.

Further, the digital circuit evaluation system includes an interaction module 15 configured to provide a user interaction interface. The user interaction interface comprises, for example, a graphical interface in which operation keys or labels, such as file import and export keys, are provided. The user can import the digital circuit description file, the standard process library or the standard unit analysis file from a preset position through the file import operation, and can export the generated resource statistical file to other storage addresses through the export key.

In addition, the interactive module 15 of the present application is further provided with a code writing interface, so that a user can write a digital circuit description code and generate a digital circuit description file through the code writing interface.

The interactive module 15 of the present application provides a commanded input interface in addition to a graphical interface. When the digital circuit description file is imported from a predetermined position, the digital circuit description file may be imported in such a manner that a read command and an address are input in the command input interface.

Of course, the interaction module 15 may also include other interfaces, such as a display interface, for displaying information and data, such as generating error notification information during parsing, and finally generating the area of the digital circuit.

The digital circuit evaluation system may be operated in a variety of ways, such as a stand-alone manner, i.e. the digital circuit evaluation system is installed in an electronic device comprising a processor and a memory. The electronic device is, for example, a desktop or laptop computer, etc. The system can also work in a mode of matching the service end and the user end, for example, only the user end of the system is installed in the electronic equipment.

In one embodiment, the digital circuit evaluation system further comprises a user management module, configured to manage information such as an account and a password of the user, and perform login verification of the user, so as to ensure that the system is used by a legal user or a user with authority.

In an application embodiment, a user logs into the digital circuit evaluation system, imports digital circuit description files through an interactive interface, and when a target digital circuit includes a plurality of digital circuit description files, imports the digital circuit description files respectively or imports the digital circuit description files in a file list manner. Then, the user determines whether to prepare a standard process library and what process standard process library is needed according to the needs. If the user has determined the process to be used, the standard process library can be determined according to the process to be used, and if the corresponding standard unit analysis file is not in the system at this time, the parameter file in the standard process library is imported. In addition, when the user writes the digital circuit description file, if the IP module is used, the corresponding IP library parameter file is imported. And then the user sends out an evaluation instruction through the interactive interface, such as clicking an evaluation instruction button in the interactive interface to send out an instruction. If the user does not determine what process is adopted, clicking an evaluation instruction button in the interactive interface to send an instruction after importing the digital circuit description file

After receiving the evaluation instruction, the digital circuit evaluation system processes each module according to the method flow, obtains the estimated area of the digital circuit when the standard process library is specified, and generates the resource statistical file when the standard process library is not determined. And after the processing is finished, displaying results, such as estimated area values, or storage addresses of resource statistical information or resource statistical files, and the like, on the interactive interface.

When a problem occurs in the processing process, if one resource cannot be analyzed or the attribute corresponding to the one resource cannot be determined, error prompt information of failure in analysis of the current vocabulary is generated and displayed in the interactive interface.

The digital circuit evaluation system provided by the application is flexible in implementation mode, high in processing speed, simple to operate and high in estimated area accuracy, and a user can obtain an evaluation result only by importing a digital circuit description file.

In another aspect, the application also provides an electronic device comprising a processor and a memory, the memory having stored therein a set of computer readable program instructions, the processor implementing the aforementioned digital circuit evaluation method when executing the set of computer readable program instructions. The electronic device is, for example, a desktop computer, a laptop computer, a tablet computer, a server, etc. The electronic device includes one or more processors, a communication interface, and a memory.

The processor can include one or more Central Processing Units (CPUs), graphics Processing Units (GPUs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), or combinations thereof. The processor is capable of executing software or computer readable instructions stored in the memory to perform the methods or operations described herein. The processor can be implemented in a number of different ways. For example, the processor can include one or more embedded processors, processor cores, microprocessors, logic circuits, hardware Finite State Machines (FSMs), digital Signal Processors (DSPs), or combinations thereof.

The communication interface can include one or more wired or wireless communication interfaces. Such as a network interface card, a wireless modem, or a wired modem. In one application, the communication interface can be a WiFi modem. In other applications, the communication interface can be a 3G modem, a 4G modem, an LTE modem, a bluetooth component, a radio frequency receiver, an antenna, or a combination thereof.

The memory can store software, data, logs, or a combination thereof. The memory can be an internal memory or an external memory. For example, the memory can be volatile memory or nonvolatile memory, such as nonvolatile random access memory (NVRAM), flash memory, disk memory, or volatile memory such as Static Random Access Memory (SRAM).

According to another aspect of the present application, there is also provided a computer readable storage medium having stored therein a set of computer readable program instructions, which when executed by a processor, implement the foregoing digital circuit evaluation method. The computer readable storage medium may be a memory in the electronic device, or may be any other memory.

The present application also provides a computer program product comprising a set of computer program instructions which, when executed by a processor, implement the digital circuit evaluation method of the foregoing embodiments. The computer program product includes, but is not limited to, forms that may be published on websites, application installation packages in application stores, application plugins, applets that may be run in certain applications, and the like.

It should be clear that the present application is not limited to the particular arrangements and processes described above and illustrated in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions, or change the order between steps, after appreciating the spirit of the present application.

The above embodiments are provided for illustrating the present application and are not intended to limit the present application, and various changes and modifications can be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.

Claims

1. A digital circuit evaluation method, comprising:

when the attribute information comprises resource load information, calculating based on the resource load information to obtain load capacity data of the resource;

2. The digital circuit evaluation method according to claim 1, wherein the step of parsing the digital circuit description file includes:

3. The digital circuit evaluation method according to claim 2, wherein the resource keywords are preset keywords according to the characteristics of the digital circuit description language and the description rules of the resources, and a plurality of preset resource keywords are combined together to satisfy a specific condition for determining preset resources; the attribute keywords are one or more, and a plurality of preset attribute keywords are combined together to meet the specific condition for determining the related attribute of the preset resource.

4. The digital circuit evaluation method according to claim 2, wherein when a resource output keyword is included in the preset attribute keyword, the step of identifying attribute information of the resource from the circuit description code based on the preset attribute keyword includes:

5. The digital circuit evaluation method of claim 4, wherein the resources comprise one or more of a plurality of types of memory cells, a plurality of types of logic gates, and a plurality of types of selectors.

6. The digital circuit evaluation method of claim 2, wherein parsing the digital circuit description file further comprises:

7. The digital circuit evaluation method according to claim 1, further comprising, when a standard process library is determined and a standard cell resolution file of the standard process library is not provided:

acquiring a parameter file in the standard process library; and

8. A digital circuit evaluation system, comprising:

9. The digital circuit evaluation system of claim 8, further comprising an interaction module configured to provide a user interaction interface, the digital circuit description file being determined from the specified location based on a file import operation by a user.

10. An electronic device comprising a processor and a memory, the memory having stored therein a set of computer readable program instructions, characterized in that the processor, when executing the set of computer readable program instructions, implements the digital circuit evaluation method of any of the preceding claims 1-7.

11. A computer readable storage medium, in which a set of computer readable program instructions is stored, characterized in that the digital circuit evaluation method of any one of the preceding claims 1-7 is implemented when said set of computer readable program instructions is executed by a processor.

12. A computer program product comprising a set of computer program instructions which, when executed by a processor, implements the digital circuit assessment method of any one of claims 1-7.