CN117743242A - Even number last level compensation system and compensation method between low-speed CPU cores - Google Patents
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Abstract
The invention provides a low-speed CPU inter-core even number last level compensation system and a compensation method, wherein the system comprises: the device comprises a last bit even number judging device, a last bit flag register, a cache module and an even number decomposing module; the last bit even number judging device comprises a last bit judging device and an even number judging device; the last bit judging device is used for judging whether the serial data line data acquired when the time sequence circuit is stopped is last bit or not; the even number judging device is used for judging whether decimal numbers corresponding to the binary numbers of the preset number of the last digits are even numbers or not; the even decomposition module is used for decomposing the even number into the sum of a preset number of odd prime numbers according to an even decomposition table when the decimal number is judged to be even; converting the preset number of odd prime numbers into corresponding preset number of binary numbers; the caching module is used for caching binary numbers; the last bit flag register is used for storing a last bit judgment result, an even number judgment result and the even number disassembly bit number. The invention can solve the problem of end bit level shift during transmission between CPU cores.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to a low-speed CPU inter-core even number last level compensation system and a compensation method.
Background
In the field of computing science, due to possible defects in the aspects of a core arithmetic unit, a scheduler, an operating system, a core algorithm or chip design, when designing a large-scale integrated circuit, a large-scale numerical control logic gate circuit and a low-speed special embedded processor, the last time sequence transmitted between CPU cores generates a level shift phenomenon due to even number last bits.
One method for dealing with the problem of "last level shift" is to extend the timing wave widely, and still ensure the occurrence of the timing wave when the serial data is no longer transmitted, but the above method greatly increases the errors of the statistics elements that depend on the timing in the CPU, such as: PMU (Performance Monitoring Unit) performance records the overhead and errors of the original and also becomes difficult to control over the time of the extension of the timing wave.
Disclosure of Invention
The invention provides a low-speed CPU inter-core even number end level compensation system and a compensation method, which are used for solving the problem that the transmission end time sequence between CPU cores encounters even number end level shift in the prior art.
In a first aspect, an embodiment of the present invention provides a low-speed CPU inter-core even last bit level compensation system, the system comprising: the device comprises a last bit even number judging device, a last bit flag register, a cache module and an even number decomposing module;
the last bit even number judging device comprises a last bit judging device and an even number judging device; the last bit judging device is used for judging whether the serial data line data acquired when the time sequence circuit is stopped is last bit or not; the even number judgment unit is used for judging whether decimal numbers corresponding to the binary numbers of the preset number of last digits are even numbers or not;
the even decomposition module is used for decomposing the even number into the sum of a preset number of odd prime numbers according to an even decomposition table when the decimal number is judged to be even; converting the preset number of odd prime numbers into corresponding preset number of binary numbers;
the caching module is used for caching the binary numbers output by the even number decomposition module and the original binary numbers;
the last bit flag register is used for storing a last bit judgment result output by the last bit judgment device, an even number judgment result output by the even number judgment device and the even number decomposition module to decompose the even number decomposition bit number.
Optionally, the low-speed CPU inter-core even last bit level compensation system provided by the present invention further includes:
and the CPU inter-core serial bus hub is used for connecting the last bit even number judgment device, the last bit flag register, the cache module, the even number decomposition module and the CPU core.
In a second aspect, an embodiment of the present invention provides a low-speed CPU inter-core even last bit level compensation method for a low-speed CPU inter-core even last bit level compensation system, including:
acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device;
when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not;
when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length;
storing the original binary number and the converted binary number in a cache module;
and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
Optionally, according to the method for compensating the even last level between low-speed CPU cores provided by the present invention, the last determination result is represented by 0,1, where 0 represents that the determined serial data is a non-transmission end bit, and 1 represents that the determined serial data is a transmission end bit.
Optionally, according to the low-speed CPU inter-core even last level compensation method provided by the present invention, the even number judgment result is represented by 0,1, where 0 represents that the judged decimal number is an uneven number, and 1 represents that the judged decimal number is an even number.
Optionally, according to the low-speed CPU inter-core even last bit level compensation method provided by the present invention, the number of disassembled bits is represented by 0,1, where 01 represents the sum of two prime numbers, 10 represents the sum of one prime number and two products, 11 represents the odd addition of two non-prime numbers, and 00 represents the last bit number of 0.
In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the processor and the memory complete communication with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions capable of performing the method of: acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device; when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not; when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length; storing the original binary number and the converted binary number in a cache module; and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
In a fourth aspect, embodiments of the present invention provide a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the following method: acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device; when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not; when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length; storing the original binary number and the converted binary number in a cache module; and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
In a fifth aspect, embodiments of the present invention provide a computer program product comprising a computer program which, when executed by a processor, performs the method of: acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device; when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not; when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length; storing the original binary number and the converted binary number in a cache module; and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
According to the low-speed CPU inter-core even number end bit level compensation system and the low-speed CPU inter-core even number end bit level compensation method, the end bit flag register is added in the CPU, when the end bit of transmission is determined to be even, the even number is expanded to be the sum of a preset number of odd prime numbers, the decomposed end bit of transmission exists in an odd number mode, whether transmission is ended or not can be judged, and the problem of even number end bit level drift of the CPU inter-core transmission is effectively solved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a low-speed CPU inter-core even last level compensation system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing a logic relationship between a CPU data line and a sequential circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a CPU serial bus design according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the last level shift principle according to an embodiment of the present invention;
FIG. 5 is a waveform diagram of a timing waveform at a last bit value 190 according to an embodiment of the present invention;
FIG. 6 is a waveform diagram of a decomposition of 190 into 179 and 11 timing waves according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a method for compensating even last level between low-speed CPU cores according to an embodiment of the present invention;
fig. 8 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The last level shift is to prevent the transmission of the timing by mainly powering down the last timing or turning off the power switch when the timing circuit is in an off state or when the CPU core is switched. In general, the turn-off time of the timing circuit is later than the last bit data transmission of the CPU, but due to the defects of the nano technology and the brush quality process of the high-speed circuit board, the situation that the last bit timing wave is advanced to the serial port data line often occurs in a part of special embedded processors. When the serial port last bit data is odd, i.e. the last bit ends with a high level, the serial port data can be reversely deduced by the collected data bits, but when the serial port last bit data is even, i.e. the last bit ends with a low level, whether the last bit even is normally transmitted or not cannot be judged, which is the so-called "last bit level shift" problem in the field of large scale integrated circuit design.
Aiming at the last bit drift problem, if a method of widely extending the time sequence wave is adopted, the error of a statistics element which depends on the time sequence in the CPU is greatly increased, and the time sequence wave is difficult to control in the extending time.
The invention provides a low-speed CPU inter-core even number last bit level compensation system and a compensation method.
The following describes a low-speed CPU inter-core even last bit level compensation system and compensation method according to an embodiment of the present invention with reference to fig. 1 to 5.
Fig. 1 is a schematic diagram of a low-speed CPU inter-core even last bit level compensation system according to an embodiment of the present invention. As shown in fig. 1, the system includes: a last bit even number judging device 11, a last bit flag register 12, a buffer memory module 13 and an even number decomposing module 14.
The last even number judging device 11 comprises a last judging device 111 and an even number judging device 112; the last bit judging device 111 is configured to judge whether the serial data line data acquired when the sequential circuit is suspended is last bit; the even number judging unit 112 is configured to judge whether the decimal number corresponding to the last 8-bit binary number is an even number; the even decomposition module 14 is configured to decompose the even number into a sum of a predetermined number of odd prime numbers according to an even decomposition table when the decimal number is determined to be an even number; and converting the predetermined number of odd prime numbers into corresponding 8-bit binary numbers; the buffer module 13 is configured to buffer the 8-bit binary number output by the even number decomposition module 14 and the original 8-bit binary number; the last bit flag register 12 is used for storing a last bit judgment result output by the last bit judgment unit 111, an even number judgment result output by the even number judgment unit 112, and the even number decomposition module 14 decomposes the even number decomposition bit number.
It will be appreciated that from a number theory perspective, the last even number may be represented by Goldbach Chen Dingli as the sum of a prime number and a product of no more than two prime numbers. Since the decomposed last bit number exists in the form of an odd number (prime number), the odd number is terminated in a high level in binary, and thus it can be judged whether the last bit ends transmission by detecting whether the terminated level is a high level.
Specifically, fig. 2 is a schematic diagram of a logic relationship between a CPU data line and a sequential circuit provided in an embodiment of the present invention, as shown in fig. 2, when a last sequential wave is advanced to a serial port data line, and when last data is even, if the sequential circuit is finished in advance and a "last level shift" condition occurs, it is not known whether more even numbers exist after even numbers or 0 level exists; however, if the even number is converted into the sum of a prime number and a product of no more than two prime numbers, the end bit will be an odd number, so that the end flag bit can be reversely deduced.
Based on the above analysis, in the proposed low-speed CPU inter-core even last-bit level compensation system, the embodiment of the present invention sets the even-number decomposition module 14, for example, taking the last bit as 8 as a binary number, and when the last 8 bit is even, represents the last 8 bit even as the sum of the products of one prime number and one not more than two prime numbers according to Chen Dingli. The 8 bits are expanded to 24 bits, and 2-3 odd numbers represent large even numbers, so that the problem that whether the last bit data ends or not can not be judged due to 'last bit level shift' of CPU serial port data is solved.
Two common serial bus design modes exist in the multi-core CPU, and FIG. 3 is a schematic diagram of the CPU serial bus design mode provided by the embodiment of the invention, as shown in FIG. 3, the common serial bus design mode in the multi-core CPU comprises a common serial communication bus and a serial-parallel interactive data bus.
Due to the defects of the high-speed circuit board brush quality process and the production quality of the nano-scale switch-gate circuit, the problem of sporadic tail level shift of the two serial data lines in fig. 3 occurs.
Specifically, fig. 4 is a schematic diagram of the last level shift principle provided by the embodiment of the present invention, as shown in fig. 3, when the last 8 bits of data of the serial port are odd, the last bit ends with a high level, and the serial port data can be reversely deduced through the collected data bits. Illustratively, if the last 16 bits are collected in binary: 1001 1101 and 00001111, 157 and 15, by looking up the even decomposition table and the last flag register, it is inversely deduced that it is transformed by the even 172.
However, when the last 8 bits of the serial port are even numbers, that is, the last bit ends with a low level, it cannot be determined whether the last bit obtained is a true transmission end bit, and it cannot be determined whether the last bit even numbers are normally transmitted, which causes a last bit level shift problem when designing a large-scale integrated circuit.
Specifically, in the proposed low-speed CPU inter-core even last level compensation system according to the embodiment of the present invention, the last bit determiner 111 is configured to determine whether the acquired binary number is the last bit. The specific judging process can be as follows:
judging whether a last bit flag bit in a last bit flag register is 1;
if the flag bit is 1, it indicates that the 8-bit data transmitted subsequently is the last 8 bits.
That is, when the serial port is transmitting the last 8 bits of data, the last bit arbiter 111 is set to 1, and when the serial port is not transmitting the last 8 bits of data, the last bit arbiter 111 does not take the value.
Further, after determining that the serial port transmits the last 8-bit data, the compensation system determines, by the set even number determiner 112, whether or not the decimal number corresponding to the predetermined number of binary numbers consecutive before the last bit is even.
Illustratively, a binary number with an end digit of 8 bits is selected for analysis.
Specifically, since the last digit is 8 bits, it ranges from 0 to 255: where the prime number set is { 23 57 11 13 17 19 23 29 31 37 41 43 47 53 59 61 67 71 73 79 83 8997 101 103 107 109 113 127 131 137 139 149 151 157 163 167 173 179181 191 193 197 199 211 223 227 229 233 239 241 251}.
The even set is { 246 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 3840 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224226 228 230 232 234 236 238 240 242 244 246 248 250 252 254}.
When the last bit is judged to be even, decomposing the even by an even decomposition module to obtain the sum of a preset number of odd prime numbers, wherein the even decomposition module comprises an even decomposition table, as shown in table 1, and table 1 is the even decomposition table with the value range of 2-255 provided by the embodiment of the invention.
TABLE 1
| Decimal system | Decomposition results | Decimal system | Decomposition results | Decimal system | Decomposition results |
| 2 | 1+1 | 18 | 13+5 | 182 | 163+19 |
| 4 | 1+3 | 20 | 17+3 | 180 | 173+7 |
| 6 | 3+3 | 22 | 11+11 | 178 | 173+5 |
| 8 | 5+3 | … | … | 176 | 173+3 |
| 10 | 7+3 | 190 | 179+11 | 174 | 163+11 |
| 12 | 7+5 | 188 | 181+7 | 172 | 157+15 |
| 14 | 11+3 | 186 | 179+7 | … | … |
| 16 | 13+3 | 184 | 179+5 | 254 | 251+3 |
Optionally, the even number judgment result is represented by 0,1, where 0 represents that the judged decimal number is an uneven number, and 1 represents that the judged decimal number is an even number.
Alternatively, the number of disassembled bits is represented by 0,1, where 01 represents the addition of two prime numbers, 10 represents the sum of one prime number and two products, 11 represents the addition of two non-prime numbers and odd number, and 00 represents the number of final bits as 0.
In the embodiment of the present invention, the last bit flag register 12 is set in the CPU, by setting the 4 bit flag in the last bit flag register, where the first bit indicates whether it is the transmission end bit, the second bit indicates whether it is the even flag, the extended bit flag indicates that the even is represented as several prime numbers according to Chen Dingli, for example, as in table 2, table 2 is a case of disassembling the last bit as an even into two non-prime odd additions, where 01 represents two prime additions, 10 represents a sum of one prime number and two products, and for solving the cases of even 4 and 2, 11 is identified as two non-prime odd additions, and 00 represents the last bit number as 0.
TABLE 2
| Whether or not to last position | Whether or not to even number | Extended number of bits |
| 1 | 1 | 11 |
For example, taking the last 8-bit binary number as an example, in the case where the last 8 bits are even numbers, the even numbers can be represented by 2 odd numbers or odd prime numbers, and when the serial port is even numbers, the serial port is represented as two odd combinations.
Illustratively, as shown in table 3, table 3 is a flag bit of the last flag register at the time of the value 190, and when the last digit is 190, 190 may be expressed as: 179+11, the original number 190 is indicated as 179 and 11, and at the same time the "last register" last flag bit is identified as "1", whether even is identified as "1", and the number of extension bits is identified as "10".
TABLE 3 Table 3
| Whether or not to last position | Whether or not to even number | Extended number of bits |
| 1 | 1 | 10 |
FIG. 5 is a waveform diagram of a timing waveform at a last bit value 190 according to an embodiment of the present invention; FIG. 6 is a waveform diagram of a decomposition of 190 into 179 and 11 timing waves according to an embodiment of the present invention; as shown in fig. 5 and 6, when the last bit is an even number, a last level shift occurs, and since the even number is expressed as addition of two odd numbers (prime numbers), the binary last bit of the odd number is expressed as a high level, and thus can be terminated with a high level flag.
Optionally, the low-speed CPU inter-core even last-bit level compensation system provided by the embodiment of the present invention may further include a CPU inter-core serial bus hub, configured to connect the last-bit even-number arbiter, the last-bit flag register, the buffer module, the even-number decomposition module, and the CPU core.
The embodiment of the invention also provides a low-speed CPU inter-core even number end bit level compensation method for the low-speed CPU inter-core even number end bit level compensation system, as shown in FIG. 7, FIG. 7 is a flow diagram of the low-speed CPU inter-core even number end bit level compensation method provided by the embodiment of the invention, the method comprises the following steps:
s710, acquiring a last bit binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device;
s720, when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not;
s730, when the decimal number is judged to be even, the even is disassembled into the sum of the preset number of odd numbers through an even decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length;
s740, storing the original binary number and the converted binary number in a cache module;
s750, storing the last bit judgment result, the even judgment result and the even disassembly bit number of the even disassembly module, which are output by the even judgment device, in the last bit flag register.
The low-speed CPU inter-core even number last level compensation system and the compensation method provided by the embodiment of the invention solve the problem of 'last level shift' caused by the fact that whether the last even number is ended cannot be judged due to the fact that the time sequence wave is ended in advance in serial port communication between CPU cores. Since the even number ends with a low level and thus the last bit is difficult to judge, according to the embodiment of the invention, when the last bit even number is identified as the addition of a predetermined number of odd prime numbers, according to Goldbach Chen Dingli, the addition of the even number decomposed into two prime numbers has a strong correlation, and the prime numbers cannot be split into other prime numbers in a logic gate circuit, so that the correlation can be determined, and the data transmission uniqueness and determinability when the problem of 'level shift' occurs can be determined according to the correlation of the prime numbers.
Fig. 8 is a block diagram of an electronic device according to an embodiment of the present invention. As shown in fig. 8, the electronic device includes: a memory 802 and a processor 801, the processor 801 and the memory 802 completing communication with each other through a bus 803; the memory 802 stores program instructions executable by the processor, and the processor 801 invokes the program instructions to perform methods including, for example: acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device; when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not; when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length; storing the original binary number and the converted binary number in a cache module; and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
Embodiments of the present invention also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, are capable of performing the methods provided by the above-described method embodiments, for example comprising: acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device; when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not; when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length; storing the original binary number and the converted binary number in a cache module; and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
Embodiments of the present invention also provide a computer readable storage medium storing computer instructions that cause a computer to perform the methods provided by the above-described method embodiments, for example, including: acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device; when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not; when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length; storing the original binary number and the converted binary number in a cache module; and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A low-speed CPU inter-core even last bit level compensation system, comprising: the device comprises a last bit even number judging device, a last bit flag register, a cache module and an even number decomposing module;
the last bit even number judging device comprises a last bit judging device and an even number judging device; the last bit judging device is used for judging whether the serial data line data acquired when the time sequence circuit is stopped is last bit or not; the even number judgment unit is used for judging whether decimal numbers corresponding to the binary numbers of the preset number of last digits are even numbers or not;
the even decomposition module is used for decomposing the even number into the sum of a preset number of odd prime numbers according to an even decomposition table when the decimal number is judged to be even; converting the preset number of odd prime numbers into corresponding preset number of binary numbers;
the caching module is used for caching the binary numbers output by the even number decomposition module and the original binary numbers;
the last bit flag register is used for storing a last bit judgment result output by the last bit judgment device, an even number judgment result output by the even number judgment device and the even number decomposition module to decompose the even number decomposition bit number.
2. The low-speed CPU inter-core even last bit level compensation system of claim 1, further comprising:
and the CPU inter-core serial bus hub is used for connecting the last bit even number judgment device, the last bit flag register, the cache module, the even number decomposition module and the CPU core.
3. A low-speed CPU inter-core even last bit level compensation method using the low-speed CPU inter-core even last bit level compensation system according to any one of claims 1 to 2, comprising:
acquiring the last binary number transmitted by a CPU through a serial port when the time sequence circuit is stopped, and judging the last bit of the binary number through an even number judging device;
when judging that the binary number is the last bit, the even number judging device judges whether the decimal number corresponding to the binary number with the preset length before the last bit is an even number or not;
when judging that the decimal number is even, disassembling the even number into the sum of a preset number of odd numbers through an even number decomposition module; converting the preset number of odd prime numbers into corresponding binary numbers with preset length;
storing the original binary number and the converted binary number in a cache module;
and storing a last bit judgment result, an even judgment result and a disassembly bit number of the even output by the even judgment device, wherein the disassembly bit number of the even is disassembled by the even decomposition module, in the last bit flag register.
4. The method of claim 3, wherein the last bit determination result is represented by 0,1, wherein 0 represents that the determined serial data is a non-transmission end bit and 1 represents that the determined serial data is a transmission end bit.
5. The method of claim 3, wherein the even number judgment result is represented by 0,1, wherein 0 represents that the judged decimal number is an uneven number, and 1 represents that the judged decimal number is an even number.
6. The method of claim 3, wherein the number of disassembled bits is represented by 0,1, wherein 01 represents the sum of two prime numbers, 10 represents the sum of one prime number and two products, 11 represents the odd addition of two non-prime numbers, and 00 represents the number of the disassembled bits as 0.
7. An electronic device, comprising:
the device comprises a memory and a processor, wherein the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the steps of the low speed CPU inter-core even last level compensation method of any of claims 3 to 6.
8. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the steps of the low speed CPU inter-core even last level compensation method according to any one of claims 3 to 6.
9. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor performs the steps of the low-speed CPU inter-core even last level compensation method according to any one of claims 3 to 6.
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