CN117742572A - Memory, controller, memory system and operation method of memory system - Google Patents

Abstract

The present invention relates to a controller. The controller includes: a data splitter configured to split host write data into high-order data and low-order data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing high-order data into a first storage area in the memory selected based on the first address, and one or more second commands for writing low-order data into a second storage area in the memory selected based on the second address; and a control block configured to control the address generator and the command generator to make power consumption different between the first storage area and the second storage area.

Description

Memory, controller, memory system and operation method of memory system

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2022-0111936 filed on month 21 of 2022 and korean patent application No. 10-2023-0026607 filed on month 28 of 2023, both of which are incorporated herein by reference in their entireties.

Technical Field

Various embodiments of the present invention relate to a memory system.

Background

In the field of machine learning, which is one of the fields of artificial intelligence, it is indispensable to collect and analyze big data. As the size of data used in machine learning increases exponentially, the amount of memory required for Personal Computers (PCs), servers, and data centers that process the data also increases exponentially.

As the amount of storage used increases, so does the power consumption and greenhouse gas emissions of data systems, such as those using large amounts of storage. This requires development of a technology capable of reducing power consumption used by the memory.

Disclosure of Invention

Embodiments of the present invention relate to a technique for reducing memory power consumption.

According to an embodiment of the present invention, a controller includes: a data splitter configured to split host write data into high-order data and low-order data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing high-order data to a first storage area in the memory selected based on the first address, and one or more second commands for writing low-order data to a second storage area in the memory selected based on the second address; and a control block configured to control the address generator and the command generator to make power consumption different between the first storage area and the second storage area.

According to another embodiment of the present invention, a memory includes: a first storage area configured to store therein high-order data; and a second storage area configured to store therein low-order data, wherein a refresh rate of the first storage area and a refresh rate of the second storage area are different from each other.

In the memory, the high-order data may include more integers than the low-order data, and the low-order data may include more decimal numbers than the high-order data. The refresh rate of the first memory region may be higher than the refresh rate of the second memory region. The memory may further include a refresh control circuit configured to control refresh operations on the first and second memory regions in response to the refresh command such that the respective first and second memory regions are refreshed at different refresh rates from each other. The memory may further include a refresh control circuit configured to control the performance of a refresh operation on both the first memory region and the second memory region in response to the first refresh command, and to control the performance of the refresh operation on the first memory region in response to the second refresh command. The first storage region may have different storage characteristics than the second storage region. The first memory region may have a flip-flop memory characteristic. The second memory region may have a nonvolatile memory characteristic of performing a refresh operation to retain stored data.

According to another embodiment of the present invention, a memory system includes: a memory; and a memory controller, wherein the memory controller comprises: a data splitter configured to split host write data into high-order data and low-order data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing high-order data to a first storage area in the memory selected based on the first address, and to generate one or more second commands for writing low-order data to a second storage area in the memory selected based on the second address; and a control block configured to control the address generator and the command generator to make power consumption different between the first storage area and the second storage area.

In the memory system, the high-order data may include more integers than the low-order data, and the low-order data may include more decimal numbers than the high-order data. The host write data may include a plurality of numbers, each of the plurality of numbers being 2N bits, and the data splitter may split upper N bits of each of the plurality of numbers from the host write data as upper data, and lower N bits of each of the plurality of numbers as lower data, where N is an integer greater than 0.

According to another embodiment of the present invention, a method for operating a memory system includes: receiving, by a memory controller, a write request from a host including host write data and a host write address; separating, by the memory controller, the host write data into high-order data and low-order data; generating, by the memory controller, a first write address and a second write address based on the host write address; instructing, by the memory controller, the memory to perform an operation of writing high-order data into a first storage area selected based on the first write address; storing, by the memory, the high-order data into the first storage area; instructing, by the memory controller, the memory to perform an operation of writing low-order data into the second storage area selected based on the second write address; and storing, by the memory, the low-order data into the second storage area.

The method may further include refreshing, by the memory, the first memory region at a first refresh rate and the second memory region at a second refresh rate, the first refresh rate being greater than the second refresh rate. The high order data may include more integers than the low order data, and the low order data may include more decimal numbers than the high order data. The host write data may include a plurality of numbers, each of the plurality of numbers being 2N bits, and the separating may include separating, from the host write data, the upper N bits of each of the plurality of numbers as the upper data, and separating the lower N bits of each of the plurality of numbers as the lower data, wherein N is an integer greater than 0. The method may further comprise: receiving, by a memory controller, a read request from a host including a host read address; generating, by the memory controller, a first read address and a second read address based on the host read address; instructing, by the memory controller, the memory to perform a read operation on the first storage area selected based on the first read address; reading, by the memory, high-order data from the first storage area; instructing, by the memory controller, the memory to perform a read operation on the second storage area selected based on the second read address; reading, by the memory, low-order data from the second storage area; generating, by the memory controller, host read data by combining the read high-order data and low-order data; and providing, by the memory controller, the host read data to the host.

According to another embodiment of the present invention, a memory system includes: a memory including a first memory region and a second memory region and configured to refresh the first memory region at a first rate and to refresh the second memory region at a second rate; and a controller configured to: in response to a write request provided with the data fragment, the first portion and the second portion are separated from the data fragment, and the memory is controlled to store the first portion and the second portion into respective first storage areas and second storage areas.

The first ratio may be greater than the second ratio. The data fragment may represent a rational number, the first portion may represent an integer portion of the rational number, and the second portion may represent a fractional portion of the rational number. The first portion may be a predetermined number of high order bits within the data segment and the second portion may be the remaining low order bits within the data segment. The controller may be further configured to: in response to a read request for a data segment, the first and second portions are read from the respective first and second storage areas, and the read first and second portions are combined into a data segment provided as a response to the read request. The controller may be further configured to control the memory to refresh the first storage area and the second storage area.

Drawings

FIG. 1 is a block diagram illustrating a memory system according to an embodiment of the invention.

Fig. 2 is a diagram for describing the operation of the data separator and the data adder shown in fig. 1 according to an embodiment of the present invention.

Fig. 3 is a diagram for describing an operation of the address generator shown in fig. 1 according to an embodiment of the present invention.

Fig. 4 is a diagram for describing an operation of the address generator shown in fig. 1 according to an embodiment of the present invention.

Fig. 5A to 5C are detailed block diagrams illustrating the memory shown in fig. 1 according to an embodiment of the present invention.

FIG. 6 is a flow chart for describing a write operation of the memory system shown in FIG. 1 according to an embodiment of the present invention.

Fig. 7 is a flowchart for describing a read operation of the memory system shown in fig. 1 according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. The invention may, however, be embodied in different forms and variations and should not be construed as being limited to the embodiments set forth herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout the disclosure in the various figures and embodiments of the present invention.

In terms of the nature of machine learning, numbers (e.g., rational numbers: hereinafter representatively referred to as rational numbers) composed of integer parts and fractional parts are mainly processed in the calculation process, instead of integers. Since the rational numbers including the integer part and the fractional part are stored in the same area of the memory, the error rate may be the same. However, in machine learning and other fields, the accuracy of the integer part is sometimes considered more important than the accuracy of the fractional part. Accordingly, the following embodiments of the present invention provide a technique for reducing power consumption of a memory by dividing a rational number into an integer part and a fractional part, storing the integer part and the fractional part in different areas of the memory, and maintaining the accuracy of the stored integer part greater than the accuracy of the stored fractional part.

Fig. 1 is a block diagram illustrating a memory system 100 according to an embodiment of the invention.

Referring to fig. 1, a memory system 100 may include a memory controller 110 and a memory 150.

Memory controller 110 may control the operation of memory 150 upon request of HOST. HOST may include a CPU (central processing unit), GPU (graphics processing unit), AP (application processor), etc. Memory controller 110 may include a host interface 111, a control block 113, a command generator 115, a memory interface 117, a data splitter 119, a data adder 121, and an address generator 123. The memory controller 110 may be embedded in CPU, GPU, AP or the like. In this case, the HOST may refer to a configuration other than the memory controller 110 in CPU, GPU, AP or the like. For example, when the memory controller 110 is embedded in a CPU, the HOST in fig. 1 may represent constituent elements in the CPU other than the memory controller 110.

HOST interface 111 may be an interface for communication between HOST and memory controller 110. Write requests, read requests, etc. may be communicated from HOST to memory controller 110 through HOST interface 111. In addition, the processing results of the operations indicated by HOST may be transferred from memory controller 110 to HOST through HOST interface 111.

The control block 113 may control the overall operation of the memory controller 110 and schedule operations to be directed to the memory 150. Control block 113 may change the order of requests received from HOST and the order in which operations of memory 150 are to be directed in order to improve the performance of memory 150. For example, even if the HOST requests the memory 150 to perform a read operation first and then a write operation, the order may be adjusted in such a way that the write operation is performed first and then the read operation is performed. Control block 113 may control the operation of host interface 111, command generator 115, memory interface 117, data splitter 119, data adder 121, and address generator 123.

The command generator 115 may generate commands to be applied to the memory 150 according to an operation order determined by the control block 113. For example, the commands may include an activate command, a precharge command, a refresh set command, a read command, a write command, a mode register command, and the like.

The memory interface 117 may be provided as an interface between the memory controller 110 and the memory 150. The command/address signal CA may be transferred from the memory controller 110 to the memory 150 through the memory interface 117, and the DATA may be transmitted and received through the memory interface 117. The memory interface 117 may also be referred to as a Physical (PHY) interface.

The data splitter 119 may split HOST write data transferred from the HOST into upper data (upper data) and lower data (lower data). The high order data may include more integer parts than the low order data, and the low order data may include more fractional parts than the high order data. The high order data may be data of which accuracy is very important, and the low order data may be data of which accuracy is relatively low order data. The high order data and the low order data may be written into different areas in the memory 150. The data separator 119 will be described in detail below with reference to fig. 2.

The data adder 121 may generate read data requested by the HOST by adding the high-order data and the low-order data read from the memory 150. The data splitter 119 may split HOST write data transferred from the HOST during a write operation into high-order data and low-order data, and the data adder 121 generates HOST read data by adding the high-order data and the low-order data transferred from the memory 150 during a read operation. The data adder 121 will be described in detail below with reference to fig. 2.

The address generator 123 may generate the first address and the second address based on the HOST address transferred from the HOST. The first address may be an address for selecting a first storage area of the memory 150 storing high-order data, and the second address may be an address for selecting a second storage area of the memory 150 storing low-order data. The address generator 123 may generate the first address and the second address based on the HOST address included in the write request of the HOST during the write operation, and the address generator 123 may generate the first address and the second address based on the HOST address included in the read request of the HOST during the read operation. The address generator 123 will be described in detail later with reference to fig. 3 to 4.

On the other hand, the control block 113 according to an embodiment of the present invention may control the above-described components (particularly the command generator 115 and the address generator 123) so that the power consumption is different between the first memory area and the second memory area. For example, the control block 113 may control the command generator 115 and the address generator 123 such that the number of accesses between the first storage area and the second storage area is different. For example, the command generator 115 and the address generator 123 may be controlled such that the refresh rates of the first and second memory regions are different from each other.

For example, under control of control block 113, command generator 115 may issue refresh commands to memory 150 that refresh memory cells in a first memory region and refresh commands to memory cells in a second memory region at different rates. In this case, the command generator 115 may generate the refresh command for refreshing the memory cells in the first memory region more frequently. For example, under the control of the control block 113, the command generator 115 may generate and supply refresh setting commands setting different refresh rates of the first and second memory regions to the memory 150.

The memory 150 may perform operations indicated by the memory controller 110. The memory 150 may include memory regions having different memory characteristics. For example, the memory 150 may include a volatile memory area having volatile memory characteristics and a nonvolatile memory area having nonvolatile memory characteristics. The volatile memory characteristic may have a characteristic of losing stored data at power-off, and the nonvolatile memory characteristic may have a characteristic of retaining stored data even at power-off. Recently, even in the case of a memory having a nonvolatile memory characteristic, a refresh operation is performed to restore the characteristic of the memory cell due to occurrence of a drift phenomenon of a threshold shift of the memory cell. The memory 150 will be described in detail with reference to fig. 5A to 5C.

On the other hand, the memory controller 110 may further include an internal memory 125. The internal memory 125 may be used as an operation memory of the memory system 100 and the memory controller 110, and store data for driving the memory system 100 and the memory controller 110. Depending on the configuration, the internal memory 125 may be implemented as a volatile memory such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM), or as a non-volatile memory such as a flash memory, a resistive RAM (ReRAM), a Phase Change RAM (PCRAM), a ferroelectric RAM (FeRAM), or a Magnetic RAM (MRAM), or other type of RAM. According to an embodiment, the internal memory 125 may be implemented using registers, flip-flops (flip-flop), static Random Access Memory (SRAM), or a combination thereof. Further, the internal memory 125 stores data required to perform operations such as data writing and reading between the host and the memory 150, and may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and the like.

In particular, the internal memory 125 may include a first storage area according to an embodiment of the invention. In this case, under the control of the control block 113, the address generator 123 may generate a first address for accessing the internal memory 125 and a second address for accessing the memory 150 located outside the memory controller 110. According to an embodiment, the internal memory 125 may include both a volatile memory area having volatile memory characteristics and a nonvolatile memory area having nonvolatile memory characteristics. As described above, since the first storage area is provided in the internal memory 125, the amount of power consumption for transmitting data to the external memory 150 can be reduced.

According to an embodiment of the present invention, the first storage area and the second storage area may be allocated to storage areas of the memory 150 having different storage characteristics. In this case, under the control of the control block 113, the address generator 123 may generate a first address and a second address for accessing the memory areas of the memory 150 having different memory characteristics, respectively. For example, the address generator 123 may designate the second storage area as a volatile storage area or a nonvolatile storage area by generating a second address of a storage area having storage characteristics that must perform a refresh operation to retain stored data, which accesses the memory 150. For example, the address generator 123 may designate the second storage area as the nonvolatile storage area by generating a second address to access the nonvolatile storage area. According to another embodiment, the first storage area and the second storage area may be respectively allocated to storage areas of the internal memory 125 having different storage characteristics. In this case, under the control of the control block 113, the address generator 123 may designate the first storage area as the trigger memory by generating a first address of the storage area having the trigger-type storage characteristic for accessing the internal memory 125.

In the following embodiment, a case where both the first storage area and the second storage area are provided in the memory 150 will be described as an example, in which the memory 150 is interfaced with the memory controller 110 through the memory interface 117.

Fig. 2 is a diagram for describing the operation of the data separator 119 and the data adder 121 shown in fig. 1 according to an embodiment of the present invention.

Referring to fig. 2, (a) shows HOST WRITE DATA host_write_data transferred from HOST. The HOST WRITE DATA host_write_data may have a size of 512 bits, and may include 16 rational numbers N0 to N15, each of which is 32 bits. Each of the rational numbers N0 to N15 may include integer parts int_0 to int_15 and fractional parts dec_0 to dec_15. In each of the 32-bit rational numbers N0 to N15, the size of the integer parts int_0 to int_15 and the size of the fractional parts dec_0 to dec_15 are not fixed (floating point decimal point) in general. In the case of rational numbers used in the machine learning field, the size of the fractional part (i.e., the number of bits representing the fractional part) is generally larger than the size of the integer part (i.e., the number of bits representing the integer part). For example, the integer part int_0 of the rational number N0 may be 10 bits, while the fractional part dec_0 of the rational number N0 may be 22 bits, the integer part int_7 of the rational number N7 may be 14 bits, and the fractional part dec_7 of the rational number N7 may be 18 bits.

Referring to fig. 2, (b) shows the high-order DATA mem_data_0 separated from the HOST WRITE DATA by the DATA separator 119, and (c) shows the low-order DATA mem_data_1 separated from the HOST WRITE DATA by the DATA separator 118.

In (b) of fig. 2, the upper DATA mem_data_0 may be obtained by classifying the upper 16 bits msb_0 to msb_15 of each of the rational numbers. In other words, msb_0 may be the upper 16 bits of the 32-bit rational number N0, and msb_15 may be the upper 16 bits of the 32-bit rational number N15.

In (c) of fig. 2, the low-order DATA mem_data_1 may be obtained by classifying the low-order 16 bits lsb_0 to lsb_15 of each of the rational numbers. That is, lsb_1 may be the lower 16 bits of the 32-bit rational number N1, and lsb_3 may be the lower 16 bits of the 32-bit rational number N3.

The DATA separator 119 may separate the upper 16 bits msb_0 to msb_15 of the 32-bit rational numbers N0 to N15 included in the HOST WRITE DATA host_write_data into the upper DATA mem_data_0, and may separate the lower 16 bits lsb_0 to lsb_15 of the rational numbers N0 to N15 into the lower DATA mem_data_1.

Since the size of the fractional part is generally larger than the size of the integer part for each of the rational numbers N0 to N15, most of the fractional parts dec_0 to dec_15 of the rational numbers N0 to N15 may be included in the low bit DATA mem_data_1, and some of the fractional parts dec_0 to dec_15 of the rational numbers N0 to N15 and the integer parts int_0 to int_15 may be included in the high bit DATA mem_data_0. For example, when the integer part int_0 of the rational number N0 is 10 bits and the fractional part dec_0 of the rational number N0 is 22 bits, the msb_0 of the high-order DATA mem_data_0 may include a 10-bit integer and 6-bit fractional number, and the lsb_0 of the low-order DATA mem_data_1 may include 16-bit fractional number.

That is, the low-order DATA mem_data_1 obtained by the DATA separator 119 may include a part of the fractional parts dec_0 to dec_15 among the rational numbers N0 to N15 included in the HOST WRITE DATA host_write_data, and the high-order DATA mem_data_0 may include the integer parts int_0 to int_15 of the rational numbers N0 to N15 and the rest of the fractional parts dec_0 to dec_15 included in the HOST WRITE DATA host_write_data. Since the high-order DATA mem_data_0 includes integer parts int_0 to int_15 of the rational numbers N0 to N15 and the low-order DATA mem_data_1 includes only the fractional parts dec_0 to dec_15 of the rational numbers N0 to N15, the high-order DATA mem_data_0 may require higher accuracy than the low-order DATA mem_data_1.

The data adder 121 may perform an operation opposite to that of the data separator 119. The DATA splitter 119 may perform an operation of dividing the HOST WRITE DATA host_write_data into the high-order DATA mem_data_0 and the low-order DATA mem_data_1 during the WRITE operation, and the DATA adder 121 may generate the HOST read DATA having the same format as the HOST WRITE DATA host_write_data by adding the high-order DATA mem_data_0 and the low-order DATA mem_data_1 read during the read operation.

Fig. 3 is a diagram for describing an operation of the address generator 123 shown in fig. 1 according to an embodiment of the present invention.

Referring to fig. 3, it is shown how the address generator 123 generates a table of a first address mem_add_0 and a second address mem_add_1 from the value of the HOST address host_add.

HOST address host_add may be an address included in a write request and a read request transmitted from HOST to memory controller 110. The HOST address host_add may include a bank address (bank address), a row address, and a column address. Here, for convenience of description, the value of the bank address of the HOST address host_add may be in the range of 0 to 7, the value of the row address may be in the range of 0 to 7, and the value of the column address may be in the range of 0 to 7.

The first address mem_add_0 may be an address generated by the address generator 123 based on the HOST address host_add, and the first address mem_add_0 may be an address for selecting the first storage area to store the high bit DATA mem_data_0 in the memory 150. As with the HOST address host_add, the first address mem_add_0 may also include a bank address, a row address, and a column address. Here, the value of the bank address of the first address mem_add_0 may be in the range of 0 to 3, the value of the row address may be in the range of 0 to 7 and the value of the column address may be in the range of 0 to 15.

The second address mem_add_1 may be an address generated by the address generator 123 based on the HOST address host_add, and the second address mem_add_1 may be an address for selecting the second storage area to store the low-order DATA mem_data_1 in the memory 150. As with the HOST address host_add, the second address mem_add_1 may also include a bank address, a row address, and a column address. Here, the value of the bank address of the second address mem_add_1 may be in the range of 4 to 7, the value of the row address may be in the range of 0 to 7, and the value of the column address may be in the range of 0 to 15.

Referring to fig. 3, it can be seen that when the value of the bank address of the HOST address host_add is one of 0 to 3, the bank address of the first address mem_add_0 is generated to have a value of one of 0 to 3. In addition, it can be seen that the bank address of the second address mem_add_1 is generated to have a value obtained by adding 4 to the bank address of the HOST address host_add.

In addition, it can be seen that when the value of the bank address of the HOST address host_add is one of 4 to 7, the bank address of the first address mem_add_0 is generated to have a value obtained by subtracting 4 from the bank address of the HOST address host_add. Further, it can be seen that the bank address of the second address mem_add_1 is generated to be the same as the bank address of the HOST address host_add.

Referring to fig. 3, it can be seen that the row address of the HOST address host_add and the row address of the first address mem_add_0 are generated to have the same value, and the row address of the second address mem_add_1 is also generated to have the same value as the row address of the HOST address host_add and the first address mem_add_0. It can be seen that the values of the row addresses of the HOST address host_add, the first address mem_add_0, and the second address mem_add_1 are all the same.

Referring to fig. 3, it can be seen that when the bank address of the HOST address host_add is in the range of 0 to 3 and the value of the column address of the HOST address host_add is one of 0 to 7, the column address of the first address mem_add_0 and the column address of the second address mem_add_1 are generated to have the same value as the column address of the HOST address host_add. In addition, it can be seen that when the bank address of the HOST address host_add is in the range of 4 to 7 and the value of the column address of the HOST address host_add is one of 0 to 7, the column address of the first address mem_add_0 and the column address of the second address mem_add_1 are generated as values obtained by adding 8 to the column address of the HOST address host_add.

When the conversion operation is performed according to the table shown in fig. 3, and when the HOST address host_add is (2,6,3) in the order of (bank address, row address, column address), the first address mem_add_0 may be generated as (2,6,3), and the second address mem_add_1 may be generated as (6, 3). Further, when the HOST address host_add is (6, 5, 6), the first address mem_add_0 may be generated as (2, 5, 14), and the second address mem_add_1 may be generated as (6, 5, 14).

Since the high-order DATA mem_data_0 and the low-order DATA mem_data_1 must be stored in regions of the memory 150 having different refresh rates, i.e., different regions in which a refresh operation can be independently performed, the first address mem_add_0 and the second address mem_add_1 may be generated in such a manner that the low-order DATA mem_data_1 and the high-order DATA mem_data_0 may be stored in different banks. Since the value of the bank address of the first address mem_add_0 is in the range of 0 to 3, the high-order DATA mem_data_0 may be stored in the banks 0 to 3 in the memory 150, and since the value of the bank address of the second address mem_add_1 is in the range of 4 to 7, the second DATA mem_data_1 may be stored in the banks 4 to 7 of the memory 150.

Fig. 4 is a diagram for describing an operation of the address generator 123 shown in fig. 1 according to an embodiment of the present invention. In fig. 3, a case where the address value is within a specific range is shown, but in fig. 4, the range of the address value is not limited.

In fig. 4, a case is shown in which the value of the bank address of the HOST address host_add is in the range of 0 to 2k+1, the value of the row address is in the range of 0 to L, and the value of the column address is in the range of 0 to M. K. Each of L and M may be any integer of 2 or more.

Referring to fig. 4, when the value of the bank address of the HOST address host_add is one of 0 to K, the value of the bank address of the first address mem_add_0 may also be generated to have a value of one of 0 to K. In addition, the value of the bank address of the second address mem_add_1 may be generated to have a value obtained by adding k+1 to the bank address of the HOST address host_add.

When the value of the bank address of the HOST address host_add is one of k+1 to 2k+1, the value of the bank address of the first address mem_add_0 may be generated to have a value obtained by subtracting K-1 from the bank address of the HOST address host_add. In addition, the value of the bank address of the second address mem_add_1 may be generated to have the same value as the value of the bank address of the HOST address host_add.

Referring to fig. 4, it can be seen that the values of the row addresses of the HOST address host_add, the first address mem_add_0, and the second address mem_add_1 are all the same.

Referring to fig. 4, it can be seen that when the bank address of the HOST address host_add is in the range of 0 to K and the value of the column address of the HOST address host_add is one of 0 to M, the column address of the first address mem_add_0 and the column address of the second address mem_add_1 are generated to have the same value as the value of the column address of the HOST address host_add. In addition, it can be seen that when the bank address of the HOST address host_add is in the range of k+1 to 2k+1 and the column address of the HOST address host_add is one of 0 to M, the column address of the first address mem_add_0 and the column address of the second address mem_add_1 are generated to have values obtained by adding m+1 to the column address of the HOST address host_add.

Fig. 5A to 5C are detailed block diagrams illustrating the memory 150 shown in fig. 1 according to an embodiment of the present invention.

Referring to fig. 5A, the memory 150 may perform an operation indicated by a command/address signal CA transmitted from the memory controller 110 and exchange DATA with the memory controller 110. The memory 150 may include a first memory region 510, a second memory region 520, and a refresh control circuit 530.

The first storage area 510 may be an area that is accessed and stores the high-order DATA mem_data_0 (see fig. 2) obtained by the DATA separator 119 based on the first address mem_add_0 (see fig. 3 and 4) generated by the address generator 123. The first memory area 510 may include BANKs 0 to 3BANK0 to BANK3. Each of the BANKs BANK0 to BANK3 may include a plurality of memory cells for storing data.

The second storage area 520 may be an area that is accessed and stores the low-order DATA mem_data_1 (see fig. 2) obtained by the DATA separator 119 based on the second address mem_add_1 (see fig. 3 and 4) generated by the address generator 123. The second memory area 520 may include BANKs 4 to 7BANK4 to BANK7. Each of the BANKs BANK4 to BANK7 may include a plurality of memory cells for storing data.

The refresh control circuit 530 may control the refresh rates of the first and second memory regions 510 and 520 to be different from each other. In particular, the refresh control circuit 530 may control the refresh rate of the first memory region 510 to be relatively high and the refresh rate of the second memory region 520 to be relatively low. The refresh control circuit 530 may control the first memory region 510 to be refreshed more frequently than the second memory region 520. Since the first memory region 510 is refreshed more frequently than the second memory region 520, the accuracy of the high-order DATA mem_data_0 (see fig. 2) stored in the first memory region 520 may be maintained high. Since the refresh frequency of the second memory region 520 is lower than that of the first memory region 510, the accuracy of the low-order DATA mem_data_1 (see fig. 2) stored in the second memory region 520 may be maintained lower than that of the high-order DATA mem_data_0. That is, errors may rarely occur in the high-order DATA mem_data_0, while more errors may occur in the low-order DATA mem_data_1 than in the high-order DATA mem_data_0. Since the refresh rate of the second memory region 520 is controlled to be lower than that of the first memory region 510, power consumption for refreshing the second memory region 520 can be reduced.

The refresh control circuit 530 differently controls the refresh rates of the first memory region 510 and the second memory region 520, which may be driven by the memory controller 110 or the memory 150. This will be described below.

Refresh rate controlled by memory controller 110

There are two types of refresh commands that may be applied from the memory controller 110 to the memory 150, and the refresh rates of the first and second memory regions 510 and 520 may be controlled to be different based on the two types of refresh commands. The first refresh command transmitted from the memory controller 110 may be a command for refreshing both the first memory region 510 and the second memory region 520. When the first refresh command is applied from the memory controller 110, the refresh control circuit 530 may control both the first memory region 510 and the second memory region 520 to be refreshed. The second refresh command transmitted from the memory controller 110 may be a command for refreshing the first memory region 510. When the second refresh command is applied from the memory controller 110, the refresh control circuit 530 may control to perform a refresh operation only in the first memory region 510. The memory controller 110 may control the refresh rates of the first and second memory regions 510 and 520 by adjusting the number of times each of the first and second refresh commands is applied to the memory 150. For example, when the memory controller 110 applies the first refresh command and the second refresh command to the memory 150 at a ratio of 1:1, the refresh frequency of the first memory region 510 may be 2 times the refresh frequency of the second memory region 520. In addition, when the memory controller 110 applies the first refresh command and the second refresh command to the memory 150 at a ratio of 2:1, the refresh frequency of the first memory region 510 may be 1.5 times the refresh frequency of the second memory region 520.

Refresh rate controlled by memory 150

There is only one type of refresh command that is applied from memory controller 110 to memory 150. The refresh control circuit 530 may control a refresh operation to be performed in the first memory region 510 every time a refresh command is applied from the memory controller 110, but the refresh control circuit 530 can control a refresh operation not to be performed at a predetermined refresh rate in the second memory region 520. For example, the refresh control circuit 530 may perform a refresh operation in the first memory area 510 regardless of whether the refresh command is applied an odd number of times or an even number of times, but the refresh control circuit 530 can control the refresh operation to be performed in the second memory area 520 only when the refresh command is applied an even number of times. The refresh control circuit 530 may be set to control a refresh rate at which a refresh operation is not performed in the second memory area based on a set command transmitted from the memory controller 110.

On the other hand, in an embodiment of the present invention, the first storage region 510 and the second storage region 520 may have different storage characteristics. Referring to fig. 5B, the first storage area 510 may be a volatile storage area having a volatile storage characteristic, and the second storage area 520 may be designated as a nonvolatile storage area having a nonvolatile storage characteristic. As described above, in recent years, even in the case of a memory having nonvolatile memory characteristics, a refresh operation is performed to restore the nonvolatile memory characteristics. Accordingly, the second storage area 520 may be a nonvolatile storage area having a storage characteristic that requires a refresh operation to retain stored data.

According to an embodiment, the first storage area 510 may be designated as a storage area having a flip-flop type storage characteristic.

In another embodiment of the present invention, the memory 150 may be divided into two or more memories 150A and 150B having different memory characteristics. Referring to fig. 5C, the memory 150 may include a first memory 150A and a second memory 150B, which include a first memory area 510 and a second memory area 520, respectively. The first storage area 510 and the second storage area 520 of the first memory 150A may be designated as volatile storage areas having volatile storage characteristics, and the first storage area 510 and the second storage area 520 of the second memory 150B may be designated as nonvolatile storage areas having nonvolatile storage characteristics. In this case, the first and second memory areas 510 and 520 of the first memory 150A may be accessed by the first and second addresses mem_add_0 and mem_add_1, respectively, and may be designated as areas for storing the high-order DATA mem_data_0 and the low-order DATA mem_data_1. According to an embodiment, one of the first and second memory areas 510 and 520 of the first memory 150A may be accessed by the first address mem_add_0 to store the high-order DATA mem_data_0, and one of the first and second memory areas 510 and 520 of the second memory 150B may be accessed by the second address mem_add_1 to store the low-order DATA mem_data_1.

Fig. 6 is a flowchart for describing a write operation of the memory system 100 shown in fig. 1 according to an embodiment of the present invention.

Referring to fig. 6, when the HOST transmits a write request to the memory controller 110 in operation S601, a write operation of the memory system 100 may begin. The WRITE request may include HOST WRITE DATA and a HOST address HOST ADD.

In operation S603, the DATA separator 119 of the memory controller 110 may separate the HOST WRITE DATA host_write_data into the high-order DATA mem_data_0 and the low-order DATA mem_data_1, as described in fig. 2.

In operation S605, the address generator 123 of the memory controller 110 may generate the first address mem_add_0 and the second address mem_add_1 based on the HOST address host_add, as described in fig. 3 and 4.

In operation S607, the memory controller 110 may instruct the memory 150 to write the high bit DATA mem_data_0 into the memory cells of the first memory region 510 selected based on the first address mem_add_0. Specifically, the activate command and the bank address and row address of the first address mem_add_0 may be transferred from the memory controller 110 to the memory 150 (direction of the activate operation). In addition, a write command, a bank address and a column address of the first address mem_add_0, and high-order DATA mem_data_0 may be transferred from the memory controller 110 to the memory 150 (direction of write operation).

In response to the instruction of operation S607, the high-order DATA mem_data_0 may be written into the memory cells of the first memory region 510 selected based on the first address mem_add_0 in the memory 150 in operation S609. The process can be divided into an activate operation and a write operation. First, an activation operation of activating a row selected based on a row address in a BANK selected based on a BANK address of the first address mem_add_0 among BANKs BANK0 to BANK3 of the first memory area 510 of the memory 150 may be performed. Then, a write operation in which the high-order DATA mem_data_0 is written into a memory cell selected based on the column address of the first address mem_add_0 among the memory cells of the activated row may be performed.

In operation S611, the memory controller 110 may instruct the memory 150 to write the low-order DATA mem_data_1 into the memory cells of the second memory region 520 selected based on the second address mem_add_0. Specifically, the activate command and the bank address and row address of the second address mem_add_1 may be transferred from the memory controller 110 to the memory 150 (direction of the activate operation). In addition, a write command, a bank address and a column address of the second address mem_add_1, and low-order DATA mem_data_1 may be transferred from the memory controller 110 to the memory 150 (direction of write operation).

In response to the instruction of operation S611, the low DATA mem_data_1 may be written into the memory cells of the second storage area 520 selected based on the second address mem_add_1 in the memory 150 in operation S613. The process can be divided into an activate operation and a write operation. First, an activation operation of activating a row selected based on a row address in a BANK selected based on a BANK address of the second address mem_add_1 among the BANKs BANK4 to BANK7 of the second memory area 520 of the memory 150 may be performed. Then, a write operation in which the low-order DATA mem_data_1 is written into a memory cell selected based on the column address of the second address mem_add_1 among the memory cells of the activated row may be performed.

Through the above-described operation, in the HOST WRITE DATA host_write_data, the high-order DATA mem_data_0 including a large number of integer parts may be stored in the first storage area 510 of the memory 150, and the low-order DATA mem_data_1 including a large number of fractional parts may be stored in the second storage area 520 of the memory 150. Since the first memory region 510 in the memory 150 is refreshed more frequently than the second memory region 520, few errors occur in the high-order DATA mem_data_0. In addition, since the refresh frequency of the second memory region 520 of the memory 150 is lower than that of the first memory region 510, more errors may occur in the lower DATA mem_data_1 than in the higher DATA mem_data_0. However, an error occurring in the lower DATA mem_data_1 may not cause a large problem in terms of characteristics of DATA, and since the refresh frequency of the second memory region 520 is lower, power consumption of the memory 150 may be reduced.

On the other hand, as described above, even in the case of a memory having a nonvolatile memory characteristic, a refresh operation can be performed to restore the memory cell due to a drift phenomenon. Accordingly, even in the case of a memory having a nonvolatile memory characteristic, power consumption can be reduced by refreshing the first memory region 510 more frequently than the second memory region 520 and refreshing the second memory region 520 less frequently than the first memory region 520.

Fig. 7 is a flowchart for describing a read operation of the memory system 100 shown in fig. 1 according to an embodiment of the present invention.

Referring to fig. 7, when the HOST transmits a read request to the memory controller 110 in operation S701, a read operation of the memory system 100 may be started. The read request may include a HOST address host_add.

In operation S703, the address generator 123 of the memory controller 110 may generate the first address mem_add_0 and the second address mem_add_1 based on the HOST address host_add, as described in fig. 3 and 4.

In operation S705, the memory controller 110 may instruct the memory 150 to perform a read operation on the memory cells of the first memory region 510 selected based on the first address mem_add_0. Specifically, the activate command and the bank address and row address of the first address mem_add_0 may be transferred from the memory controller 110 to the memory 150 (direction of the activate operation). Then, the read command and the bank address and column address of the first address mem_add_0 may be transferred from the memory controller 110 to the memory 150 (direction of the read operation).

In response to the instruction of operation S705, in operation S707, the high-order DATA mem_data_0 may be read from the memory cells of the first memory region 510 selected based on the first address mem_add_0 in the memory 150. The process can be divided into an activate operation and a read operation. First, an activation operation of activating a row selected based on a row address in a BANK selected based on a BANK address of the first address mem_add_0 among BANKs BANK0 to BANK3 of the first memory area 510 of the memory 150 may be performed. Then, a read operation of reading the high-order DATA mem_data_0 from a memory cell selected based on the column address of the first address mem_add_0 among the memory cells of the activated row may be performed. The high-order DATA mem_data_0 may be transferred from the memory 150 to the memory controller 110.

In operation S709, the memory controller 110 may instruct the memory 150 to perform a read operation on the memory cells of the second memory region 520 selected based on the second address mem_add_1. Specifically, the activate command and the bank address and row address of the second address mem_add_1 may be transferred from the memory controller 110 to the memory 150 (direction of the activate operation). Then, the read command and the bank address and column address of the second address mem_add_1 may be transferred from the memory controller 110 to the memory 150 (direction of the read operation).

In response to the instruction of operation S709, the lower DATA mem_data_1 may be read from the memory cells of the second memory region 520 selected based on the second address mem_add_1 in the memory 150 in operation S711. The process can be divided into an activate operation and a read operation. First, an activation operation of activating a row selected based on a row address in a BANK selected based on a BANK address of the second address mem_add_1 among the BANKs BANK4 to BANK7 of the second memory area 520 of the memory 150 may be performed. Then, a read operation of reading the low-order DATA mem_data_1 from a memory cell selected based on the column address of the second address mem_add_1 among the memory cells of the activated row may be performed. The low bit DATA mem_data_1 may be transferred from the memory 150 to the memory controller 110.

In operation S713, the DATA adder 121 of the memory controller 110 may generate host read DATA by adding the high-order DATA mem_data_0 and the low-order DATA mem_data_1 transferred from the memory 150. In other words, the DATA adder 121 can generate host read DATA of the format shown in fig. 2 (a) by adding the high-order DATA mem_data_0 and the low-order DATA mem_data_1 of the format shown in fig. 2 (b) and (c).

In operation S715, HOST read data generated by the data adder 121 may be provided to the HOST. The read operation of memory system 100 may be terminated.

According to the embodiment of the invention, the power consumption of the memory can be reduced.

While the invention has been shown and described with respect to a certain embodiment, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the following claims. Furthermore, the embodiments may be combined to form further embodiments.

Claims (20)

1. A controller, comprising:

a data separator for separating the host write data into high-order data and low-order data;

an address generator that generates a first address and a second address based on a host address;

a command generator that generates one or more first commands for writing the high-order data into a first storage area in a memory selected based on the first address, and one or more second commands for writing the low-order data into a second storage area in the memory selected based on the second address; and

and a control block controlling the address generator and the command generator to make power consumption different between the first storage area and the second storage area.

2. The controller of claim 1, wherein the control block controls the address generator and the command generator to make the number of accesses between the first storage area and the second storage area different.

3. The controller of claim 1, wherein the control block controls the address generator and the command generator to control refresh rates of the first and second memory regions to be different from each other.

4. The controller of claim 3, wherein the command generator issues refresh commands to refresh memory cells in the first memory region and refresh commands to refresh memory cells in the second memory region at different rates.

5. The controller of claim 4, wherein the frequency at which the command generator issues the refresh command for the first memory region is higher than the frequency at which the command generator issues the refresh command for the second memory region.

6. The controller of claim 3, wherein the command generator issues refresh setting commands for setting different refresh rates for the respective first and second memory regions.

7. The controller according to claim 1, further comprising:

and the internal memory comprises the first storage area.

8. The controller of claim 7, wherein the control block controls the address generator to generate a first address for accessing the internal memory and to generate a second address for accessing the memory located outside the controller.

9. The controller of claim 1, wherein the control block controls the address generator to generate the first address and the second address for accessing the first storage area and the second storage area of the memory located outside the controller.

10. The controller of claim 1, wherein the control block controls the address generator to generate the first address and the second address that access the first storage area and the second storage area having different storage characteristics, respectively.

11. The controller of claim 10, wherein the address generator generates the second address to access the second memory region having memory characteristics that perform a refresh operation to preserve stored data.

12. The controller of claim 10, wherein the address generator generates the second address to access the second storage area having non-volatile storage characteristics.

13. The controller of claim 10, wherein the address generator generates the second address to access the second storage region having a trigger storage characteristic.

14. The controller of claim 1, further comprising a data adder that generates host read data by adding the high order data read from the first storage area and the low order data read from the second storage area during a read operation.

15. The controller according to claim 1, wherein,

the high-order data includes more integers than the low-order data, and

the low bit data includes more decimal than the high bit data.

16. The controller according to claim 1, wherein,

the host write data includes a plurality of numbers, each of the plurality of numbers being 2N bits, and

the data separator separates, from the host write data, upper N bits of each of the plurality of numbers as the upper data, and separates lower N bits of each of the plurality of numbers as the lower data, where N is an integer greater than 0.

17. A memory system, comprising:

a memory; and

the memory controller may be configured to control the memory controller,

wherein the memory controller includes:

a data separator for separating the host write data into high-order data and low-order data;

an address generator that generates a first address and a second address based on a host address;

a command generator that generates one or more first commands for writing the high-order data to a first storage area in the memory selected based on the first address, and that generates one or more second commands for writing the low-order data to a second storage area in the memory selected based on the second address; and

and a control block controlling the address generator and the command generator to make power consumption different between the first storage area and the second storage area.

18. The memory system of claim 17, wherein the control block controls the address generator and the command generator to control refresh rates of the first and second memory regions to be different from each other.

19. The memory system of claim 18 wherein the command generator issues refresh commands to refresh memory cells in the first memory region and refresh commands to refresh memory cells in the second memory region at different rates.

20. The memory system of claim 18, wherein the command generator issues refresh setting commands for setting different refresh rates for the respective first and second memory regions.