CN117742430A - Linear voltage stabilizing circuit, chip and electronic equipment - Google Patents

Abstract

The application provides a linear voltage stabilizing circuit, a chip and electronic equipment. The linear voltage stabilizing circuit can change the on current of the fourth transistor when the output voltage changes through the second impedance attenuation circuit. In this way, the source of the fourth transistor introduces negative feedback, and the impedance at the source of the fourth transistor decreases, balancing the impedance at the source of the fourth transistor with the impedance at the source of the third transistor. The first impedance attenuation circuit changes the on current of the third transistor when the output voltage changes. In this way, negative feedback is introduced into the source of the third transistor, so that the impedance at the source of the third transistor is reduced, and the magnitude of the pole at the source of the third transistor is increased. Further, the pole on the source of the third transistor is designed outside the UGB of the inner small loop of the LDO. Therefore, the pole of the source electrode of the third transistor is eliminated, the pole quantity of the inner small loop of the LDO is reduced, and the stability of the inner small loop and the stability of the LDO are improved.

Description

Linear voltage stabilizing circuit, chip and electronic equipment

Technical Field

The application relates to the technical field of voltage regulators, in particular to a linear voltage stabilizing circuit, a chip and electronic equipment.

Background

A low drop-out regulator (LDO) is a commonly used linear voltage regulator circuit, and can provide a low-error and stable output voltage to an output terminal of the LDO through a feedback loop. In general, the phase delay caused by a feedback loop is counteracted by using a miller compensation method by the LDO, so that the stability of the output voltage is ensured.

At present, one conventional miller compensation method is a cascode miller compensation method. In the method, the pole in the LDO can be pushed away by connecting the cascode miller compensation circuit between the source of the cascode transistor in the LDO and the output end of the LDO, so that the output voltage of the LDO can be stabilized.

However, since the cascode miller compensation circuit spans a larger gain, a new small inner loop (SL) is introduced into the LDO. Thus, the new inner small loop has one zero and three poles, resulting in a decrease in the stability of the new inner small loop, which in turn destroys the stability of the LDO.

Disclosure of Invention

The utility model provides a linear voltage stabilizing circuit, chip and electronic equipment can reduce the pole of inside little loop, improves the stability of inside little loop and the stability of LDO.

In a first aspect, the present application provides a linear voltage stabilizing circuit, comprising: the device comprises a cascode differential operational amplifier, a first impedance attenuation circuit, a second impedance attenuation circuit, a compensation circuit and a voltage constant output circuit;

the cascode differential operational amplifier comprises a first transistor, a second transistor, a third transistor, a fourth transistor, at least one fifth transistor and at least one sixth transistor;

the first end of the fifth transistor, the first end of the sixth transistor and the first end of the voltage constant output circuit are all used for being connected with power supply voltage, the second end of the fifth transistor is electrically connected with the first end of the first impedance attenuation circuit, the second end of the voltage constant output circuit is electrically connected with the second end of the first impedance attenuation circuit, the first end of the first impedance attenuation circuit is electrically connected with the second end of the first impedance attenuation circuit, the third end of the first impedance attenuation circuit is electrically connected with the second end of the third transistor, the first end of the third transistor is electrically connected with the second end of the first transistor, the fourth end of the first impedance attenuation circuit is electrically connected between the first end of the third transistor and the second end of the first transistor, the second end of the sixth transistor is electrically connected with the first end of the second impedance attenuation circuit, the second end of the second impedance attenuation circuit is electrically connected with the control end of the sixth transistor, the first end of the second impedance attenuation circuit is electrically connected with the second end of the second impedance attenuation circuit, the third end of the second impedance attenuation circuit is electrically connected with the second end of the fourth transistor, the first end of the fourth transistor is electrically connected with the second end of the second transistor, the fourth end of the second impedance attenuation circuit is electrically connected between the first end of the fourth transistor and the second end of the second transistor, the first end of the first transistor and the first end of the second transistor are both electrically connected with the first end of the common-source common-gate differential operational amplifier, and the second end of the common-source common-gate differential operational amplifier is grounded;

The first end of the compensation circuit is electrically connected with the fourth end of the first impedance attenuation circuit, and the second end of the compensation circuit is electrically connected with the third end of the voltage constant output circuit;

the control end of the fifth transistor is electrically connected with the control end of the sixth transistor, the control end of the third transistor is electrically connected with the control end of the fourth transistor, the control end of the first transistor is used for being connected with a reference voltage, the control end of the second transistor is electrically connected with the fourth end of the voltage constant output circuit, the fifth end of the voltage constant output circuit is used for outputting the output voltage of the linear voltage stabilizing circuit, and the sixth end of the voltage constant output circuit is grounded;

a second impedance attenuation circuit for changing the on-current of the fourth transistor when the output voltage is changed, so as to reduce the impedance on the source electrode of the fourth transistor;

and the first impedance attenuation circuit is used for changing the on current of the third transistor when the output voltage is changed, so that the impedance on the source electrode of the third transistor is reduced, and the pole of the source electrode of the third transistor is eliminated.

With the linear voltage stabilizing circuit provided in the first aspect, the on-current of the fourth transistor can be changed when the output voltage is changed by the second impedance attenuation circuit. In this way, the source of the fourth transistor introduces negative feedback, reducing the impedance at the source of the fourth transistor, enabling the impedance at the source of the fourth transistor to be balanced with the impedance at the source of the third transistor. The first impedance attenuation circuit can change the on current of the third transistor when the output voltage changes. In this way, negative feedback is introduced into the source of the third transistor, so that the impedance at the source of the third transistor is reduced, and the magnitude of the pole at the source of the third transistor is increased. Further, it is easy to design the pole on the source of the third transistor outside the UGB of the inner small loop of the LDO. Therefore, the pole of the source electrode of the third transistor is eliminated, the pole number of the inner small loop of the LDO is reduced, and the stability of the inner small loop and the stability of the LDO are improved.

In one possible design, the second impedance attenuation circuit is configured to increase the on-current of the fourth transistor when the output voltage increases, so that the impedance on the source of the fourth transistor decreases;

a first impedance attenuation circuit for increasing the on-current of the third transistor when the output voltage is increased, so that the impedance on the source electrode of the third transistor is reduced to eliminate the pole of the source electrode of the third transistor;

or,

a second impedance attenuation circuit for reducing the on-current of the fourth transistor when the output voltage becomes smaller, so that the impedance on the source electrode of the fourth transistor is reduced;

and the first impedance attenuation circuit is used for reducing the on current of the third transistor when the output voltage is reduced so as to reduce the impedance on the source electrode of the third transistor and eliminate the pole of the source electrode of the third transistor.

In one possible design, the first impedance attenuation circuit includes: the first operational amplifier component and the first resistor;

the first end of the first resistor is electrically connected with the second end of the fifth transistor, the second end of the first resistor is electrically connected with the second end of the third transistor, the positive phase input end of the first operational amplifier component is electrically connected with the second end of the voltage constant output circuit, the negative phase input end of the first operational amplifier component is electrically connected with the second end of the third transistor, and the output end of the first operational amplifier component is electrically connected between the first end of the third transistor and the second end of the first transistor;

The first operational amplifier component is used for carrying out operational amplification on the voltages at two ends of the first resistor under the action of changing the voltages at two ends of the first resistor, outputting the changed first voltage, and the first voltage is used for changing the on current of the third transistor.

In one possible design, the second impedance attenuation circuit includes: the second operational amplifier component and the second resistor;

the first end of the second resistor is electrically connected with the second end of the sixth transistor, the second end of the second resistor is electrically connected with the second end of the fourth transistor, the positive phase input end of the second operational amplifier component is electrically connected with the control end of the sixth transistor, the negative phase input end of the second operational amplifier component is electrically connected with the second end of the fourth transistor, and the output end of the second operational amplifier component is electrically connected between the first end of the fourth transistor and the second end of the second transistor;

and the second operational amplifier component is used for carrying out operational amplification on the voltages at two ends of the second resistor under the action of changing the voltages at two ends and outputting a changed second voltage, and the second voltage is used for changing the on current of the fourth transistor.

In one possible design, the op-amp assembly includes: a seventh transistor;

the first end of the seventh transistor is electrically connected to the second end of the voltage constant output circuit or to the control end of the sixth transistor, the control end of the seventh transistor is electrically connected to the second end of the third transistor or to the second end of the fourth transistor, and the second end of the seventh transistor is electrically connected to the second end of the third transistor or to the second end of the fourth transistor.

In one possible design, the op-amp assembly includes: an eighth transistor, a ninth transistor, and a bias current device;

the first end of the eighth transistor is electrically connected with the second end of the third transistor or with the second end of the fourth transistor, the first end of the ninth transistor and the first end of the bias current device are electrically connected with the second end of the voltage constant output circuit or with the control end of the sixth transistor, the second end of the eighth transistor is electrically connected with the second end of the bias current device, the control end of the eighth transistor and the second end of the eighth transistor are electrically connected with the control end of the ninth transistor, and the second end of the ninth transistor and the third end of the bias current device are electrically connected with the second end of the third transistor or with the second end of the fourth transistor.

In one possible design, the voltage constant output circuit includes: a power tube and a feedback sub-circuit;

the first end of the power tube is used for being connected with a power supply voltage, the control end of the power tube is electrically connected with the second end of the first impedance attenuation circuit, the second end of the power tube is electrically connected with the first end of the feedback sub-circuit, the second end of the compensation circuit is electrically connected between the second end of the power tube and the first end of the feedback sub-circuit, the second end of the feedback sub-circuit is electrically connected with the control end of the second transistor, and the third end of the feedback sub-circuit is grounded.

In one possible design, the feedback sub-circuit includes a third resistor and a fourth resistor;

the first end of the third resistor is electrically connected with the second end of the power tube, the second end of the compensation circuit is electrically connected between the first end of the third resistor and the second end of the power tube, the second end of the third resistor is electrically connected with the first end of the fourth resistor, the control end of the second transistor is electrically connected between the second end of the third resistor and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.

In a second aspect, the present application provides a chip comprising: the linear voltage stabilizing circuit of the first aspect and any one of the possible designs of the first aspect.

The advantages of the chip provided in the second aspect and the possible designs of the second aspect may be referred to the advantages brought by the possible embodiments of the first aspect and the possible embodiments of the first aspect, which are not described herein.

In a third aspect, the present application provides an electronic device, comprising: the second aspect above and the chips in each of the possible designs of the second aspect above.

Drawings

FIG. 1 is a schematic diagram of a conventional Miller compensation method for providing a linear voltage regulator;

FIG. 2 is a schematic diagram of a linear voltage regulator according to another conventional Miller compensation method;

FIG. 3 is a schematic diagram showing the amplitude and phase frequency characteristics of a new inner loop in a cascode Miller compensation method;

FIG. 4 is a schematic diagram of a linear voltage stabilizing circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a linear voltage stabilizing circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a linear voltage stabilizing circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a linear voltage stabilizing circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a linear voltage stabilizing circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a load transient response of a linear voltage stabilizing circuit according to an embodiment of the present application.

Detailed Description

In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c alone may represent: a alone, b alone, c alone, a combination of a and b, a combination of a and c, b and c, or a combination of a, b and c, wherein a, b, c may be single or plural. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

The terms "center," "longitudinal," "transverse," "upper," "lower," "left," "right," "front," "rear," and the like refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present application.

The terms "connected," "connected," and "connected" are to be construed broadly, and may refer to, for example, electrical or signal connections in addition to physical connections, e.g., direct connections, i.e., physical connections, or indirect connections via at least one element therebetween, such as long as electrical circuit communication is achieved, and communications within two elements; signal connection may refer to signal connection through a medium such as radio waves, in addition to signal connection through a circuit. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

One conventional miller compensation method is miller compensation. Referring to fig. 1, fig. 1 is a schematic diagram of a linear voltage regulator provided by a conventional miller compensation method. As shown in fig. 1, a capacitor CC is connected between a gate of a P-channel metal-oxide-semiconductor (PMOS) and a drain of the P-type power transistor, so that an equivalent capacitance formed by the P-type power transistor and the capacitor CC increases, resulting in a pole of an output terminal of the error amplifier becoming a dominant pole and a pole of an output terminal of the LDO becoming a subordinate pole, i.e., gmp/CL. Wherein gmp is the transconductance of the P-type power tube, and CL is the load capacitance. At this time, the unity gain bandwidth (unity gain bandwidth, UGB) of the LDO loop is gm1/CC. Gm1 is the transconductance of transistor Q1 and the transconductance of transistor Q2. Therefore, the stability of the LDO loop can be realized only by the fact that the secondary pole point gmp/CL is larger than UGB. That is, gm1/CC < gmp/CL.

However, due to the introduction of the capacitor CC, there is a feed-forward path in the LDO loop from the output of the error amplifier to the capacitor CC and then to the output of the LDO. Thus, a right half-plane zero is introduced. Thus, the stability of the LDO loop is reduced.

Meanwhile, due to the stability requirement of the LDO, the secondary pole point gmp/CL needs to be larger than UGB. Therefore, the load capacitance CL cannot exceed (gmp×cc)/gm 1, resulting in a smaller range of load capacitances CL that can be driven by the miller compensation method.

In addition, since the power supply voltage VDD is routed from the transistor Q5 to the capacitor CC and then to the output of the LDO, and the transistor Q6 is routed from the transistors Q4, Q2, Q1 and Q3 to the capacitor CC and then to the output of the LDO, the output voltage VOUT of the LDO is susceptible to noise from the power supply. Thus, the miller-compensated power supply rejection is poor.

The above-described miller compensation method has drawbacks. Therefore, the cascode miller compensation method is more commonly used.

Referring to fig. 2, fig. 2 is a schematic diagram of a linear voltage regulator provided by another conventional miller compensation method. As shown in fig. 2, one end of the CC capacitor is connected to the output end of the LDO, and the other end of the CC capacitor is connected to the source end of the cascode transistor Q3. Thus, the two ends of the CC capacitor are connected across a larger gain, so that the secondary point (gmp×cc)/(C1×cl) of the LDO loop is farther than the secondary point gmp/CL in the miller compensation method. Wherein C1 is the parasitic capacitance of the output terminal of the error amplifier a.

Since there is no feed-forward path between the output of the error amplifier a to the output of the LDO in this cascode miller compensation method. Therefore, the problem that the Miller compensation method introduces a right half plane zero point is solved.

Meanwhile, since the capacitor CC is connected across the source of the transistor Q3 and the output terminal of the LDO, that is, the capacitor CC is connected across two nodes far from the power supply voltage VDD. Therefore, the power supply rejection ratio of the cascode miller compensation method is better than that of the miller compensation method.

In addition, under the cascode miller compensation method, the loop stability condition of the LDO is: gm1/CC < (gmp×cc)/(C1×cl). At this time, the stable condition makes the range of the load capacitance CL that can be driven by the cascode miller compensation method large.

However, the capacitor CC bridges the larger gain in the cascode miller compensation method, which introduces a new small internal loop (SL) inside the LDO. The new inner loop SL is coupled to the source of the transistor Q3 through the capacitor CC from the output of the LDO, and then from the source of the transistor Q3 to the output of the error amplifier a, and finally back to the output of the LDO through the P-type power transistor.

Referring to fig. 3, fig. 3 is a schematic diagram showing the amplitude frequency and the phase frequency of a new inner loop in the cascode miller compensation method. As shown in fig. 3, the new inner loop SL has a zero advance z0=0 at frequency f=0, which is caused by capacitive CC coupling. At the output of LDO there is a new main pole p of internal small loop SL _1,SL Wherein p is _1,SL =1/(roeq×cl), roeq is the equivalent capacitance of the output terminal of the LDO. The secondary point p of the new inner small loop SL consisting of the capacitance CC and the source impedance 1/gm3 of the transistor Q3 _2,SL Wherein p is _2,SL Gm3/CC. The secondary point p of the new inner small loop SL consisting of the parasitic capacitance C1 of the output of the error amplifier a and the impedance roEA of the output of the error amplifier a _3,SL Wherein p is _3,SL ＝1/(roEA*C1)。

Thus, the secondary point p of the new inner small loop SL _3,SL The corresponding phase is 180 deg., resulting in a new inner loop SL with a phase easily exceeding 180 deg., which reduces the stability of the new inner loop.

Therefore, the new inner small loop SL has one zero and three poles, resulting in a decrease in the stability of the new inner small loop SL, which in turn, deteriorates the stability of the LDO.

If the stability of the new inner small loop SL is improved, one secondary point in the new inner small loop SL needs to be pushed out of the UGB of the new inner small loop SL. That is, the number of secondary poles of the new inner small loop SL is reduced.

At the secondary point p of the push-off new inner small loop SL _3,SL In the case of (a), the parasitic capacitance C1 at the output of the error amplifier a is generally determined by the size of the P-type power transistor, which is determined by the load current IL. Based on this, only the impedance roEA at the output of the error amplifier a can be reduced. However, this reduces the gain of the LDO loop, causing the output of the LDO to be electrical The error of the voltage VOUT increases, and the load adjustment rate of the LDO is reduced.

At the secondary point p of the push-off new inner small loop SL _2,SL The magnitude of the capacitance CC is determined by the stability of the LDO loop, while the maximum value of 1/gm3 of the source impedance of transistor Q3 is limited by the process and power consumption of transistor Q3. Based on this, the secondary point p of the new inner small loop SL _2,SL It is difficult to increase.

Based on the above analysis, if the stability of the new inner small loop SL is improved, one secondary pole of the new inner small loop SL needs to be pushed out of the UGB of the new inner small loop SL. Meanwhile, the impedance roEA of the output end of the error amplifier A is considered to be related to the precision of the output voltage VOUT of the LDO. Based on this, the secondary point p of the new inner small loop SL _2,SL Pushing out of the UGB of the new inner small loop SL.

Since the maximum value of 1/gm3 of the source impedance of transistor Q3 is limited by the process and power consumption of transistor Q3. Therefore, the present application increases the minor point p of the new inner small loop SL by decreasing the source impedance of transistor Q3 by 1/gm3 _2,SL . Therefore, the aim of the invention of maintaining the high precision of the output voltage VOUT of the LDO is achieved while the novel inner small loop SL of the LDO is stable.

The application provides a linear voltage stabilizing circuit, a chip and electronic equipment.

In the present application, the electronic device may be a mobile phone, a tablet computer, or a modem, which is not particularly limited in the embodiments of the present application.

The linear voltage stabilizing circuit can be a chip or a circuit module.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a linear voltage stabilizing circuit according to an embodiment of the present application. As shown in fig. 4, the linear voltage stabilizing circuit may include: the circuit comprises a cascode differential operational amplifier 100, a first impedance attenuation circuit 200, a second impedance attenuation circuit 300, a compensation circuit 400 and a voltage constant output circuit 500.

The cascode differential operational amplifier 100, the first impedance attenuation circuit 200, the second impedance attenuation circuit 300, the compensation circuit 400, and the voltage constant output circuit 500 may be separately provided or may be integrally provided.

In some examples, the compensation circuit is one capacitor, or a plurality of capacitors in series and/or parallel. For convenience of explanation, the following embodiments will be described taking the compensation circuit as one capacitor as an example.

The cascode differential operational amplifier 100 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, at least one fifth transistor M5, and at least one sixth transistor M6.

The first end of the fifth transistor M5, the first end of the sixth transistor M6 and the first end of the voltage constant output circuit 500 are all used for being connected to the power supply voltage VDD, the second end of the fifth transistor M5 is electrically connected to the first end of the first impedance attenuation circuit 200, the second end of the voltage constant output circuit 500 is electrically connected to the second end of the first impedance attenuation circuit 200, the first end of the first impedance attenuation circuit 200 is electrically connected to the second end of the first impedance attenuation circuit 200, the third end of the first impedance attenuation circuit 200 is electrically connected to the second end of the third transistor M3, the first end of the third transistor M3 is electrically connected to the second end of the first transistor M1, the fourth end of the first impedance attenuation circuit 200 is electrically connected between the first end of the third transistor M3 and the second end of the first transistor M1, the second end of the second impedance attenuation circuit 300 is electrically connected to the first end of the second impedance attenuation circuit 300, the second end of the second impedance attenuation circuit 300 is electrically connected to the second end of the fourth transistor M6, the second end of the second impedance attenuation circuit 300 is electrically connected to the second end of the fourth transistor M2 is electrically connected to the second end of the fourth impedance circuit 2, the common-gate differential amplifier circuit 2 is electrically connected to the fourth end of the fourth impedance circuit 2, and the fourth end of the common-gate amplifier is electrically connected to the fourth end of the fourth impedance circuit 300 is electrically connected to the fourth end of the fourth impedance circuit 2.

The first terminal of the compensation circuit 400 is electrically connected to the fourth terminal of the first impedance attenuation circuit 200, and the second terminal of the compensation circuit 400 is electrically connected to the third terminal of the voltage constant output circuit 500.

The control end of the fifth transistor M5 is electrically connected to the control end of the sixth transistor M6, the control end of the third transistor M3 is electrically connected to the control end of the fourth transistor M4, the control end of the first transistor M1 is used for accessing the reference voltage VREF, the control end of the second transistor M2 is electrically connected to the fourth end of the voltage constant output circuit 500, the fifth end of the voltage constant output circuit 500 is used for outputting the output voltage VOUT of the linear voltage stabilizing circuit, and the sixth end of the voltage constant output circuit 500 is grounded.

The first end of the wake source IT is a first end of the cascode differential operational amplifier 100, and the second end of the wake source IT is a second end of the cascode differential operational amplifier 100.

Wherein the number of the fifth transistors M5 is at least one, and the number of the sixth transistors M6 is at least one. As shown in fig. 5, the schematic structure of the linear voltage stabilizing circuit is shown in the case that the cascode differential operational amplifier 100 includes two fifth transistors M5 and two sixth transistors M6, and other cases are similar and will not be described in detail.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a linear voltage stabilizing circuit according to an embodiment of the present application. As shown in fig. 5, the first end of the fifth transistor M5', the first end of the sixth transistor M6, and the first end of the voltage constant output circuit 500 are all used for accessing the power supply voltage VDD, the second end of the fifth transistor M5' is electrically connected to the first end of the fifth transistor M5, the second end of the fifth transistor M5 is electrically connected to the first end of the first impedance attenuation circuit 200, the second end of the sixth transistor M6' is electrically connected to the first end of the sixth transistor M6, and the second end of the sixth transistor M6 is electrically connected to the first end of the second impedance attenuation circuit 300.

For ease of understanding, the embodiments of the present application will be described by taking the example in which the cascode differential operational amplifier 100 includes one fifth transistor M5 and one sixth transistor M6.

In fig. 4 and 5, the first end of the cascode differential operational amplifier 100 is denoted as 1, the second end of the cascode differential operational amplifier 100 is denoted as 2, the first end of the first impedance attenuation circuit is denoted as 1, the second end of the first impedance attenuation circuit is denoted as 2, the third end of the first impedance attenuation circuit is denoted as 3, the fourth end of the first impedance attenuation circuit is denoted as 4, the first end of the second impedance attenuation circuit is denoted as 1, the second end of the second impedance attenuation circuit is denoted as 2, the third end of the second impedance attenuation circuit is denoted as 3, the fourth end of the second impedance attenuation circuit is denoted as 4, the first end of the compensation circuit is denoted as 1, the second end of the compensation circuit is denoted as 2, the first end of the voltage constant output circuit is denoted as 1, the second end of the voltage constant output circuit is denoted as 2, the third end of the voltage constant output circuit is denoted as 3, the fourth end of the voltage constant output circuit is denoted as 4, the fifth end of the voltage constant output circuit is denoted as 5, and the fourth end of the voltage constant output circuit is denoted as 6.

Wherein the fifth transistor M5, the third transistor M3, the compensation circuit 400 and the voltage constant output circuit 500 form an inner small loop SL ', and the first impedance attenuation circuit 200 is within the inner small loop SL'.

The voltage constant output circuit 500 may transmit the feedback voltage VFB to the cascode differential operational amplifier 100.

The feedback voltage VFB is used to indicate the output voltage VOUT of the linear voltage stabilizing circuit. When the output voltage VOUT becomes large, the feedback voltage VFB becomes large. As the output voltage VOUT becomes smaller, the feedback voltage VFB becomes smaller.

The cascode differential operational amplifier 100 may perform error amplification on the reference voltage VREF and the feedback voltage VFB to obtain an amplified signal, and transmit the amplified signal to the voltage constant output circuit 500.

The voltage constant output circuit 500 may further output an output voltage VOUT of the linear voltage stabilizing circuit according to the amplified signal, and transmit a feedback voltage VFB to the cascode differential operational amplifier 100 according to the output voltage VOUT of the linear voltage stabilizing circuit.

Wherein the first impedance attenuation circuit 200 and the third transistor M3 form a negative feedback loop. The second impedance decay circuit 300 and the fourth transistor M4 form a negative feedback loop.

The second impedance attenuation circuit 300 may change the on-current of the fourth transistor M4 when the output voltage VOUT changes, so that the impedance at the source of the fourth transistor M4 decreases.

When the output voltage VOUT becomes large, the feedback voltage VFB becomes large, and the gate-source voltage of the second transistor M2 becomes large. In this way, the source voltage of the fourth transistor M4 increases, and the on-current of the fourth transistor M4 decreases. Further, the second impedance attenuation circuit 300 reduces the source voltage of the fourth transistor M4 by reducing the on-current of the fourth transistor M4, thereby reducing the source voltage of the fourth transistor M4. In this way, the on-current of the fourth transistor M4 increases, and negative feedback is introduced to the source of the fourth transistor M4, so that the impedance at the source of the fourth transistor M4 decreases.

Accordingly, the second impedance attenuation circuit 300 may increase the on-current of the fourth transistor M4 when the output voltage VOUT increases, so that the impedance at the source of the fourth transistor M4 decreases.

When the output voltage VOUT becomes smaller, the feedback voltage VFB becomes smaller, and the gate-source voltage of the second transistor M2 becomes smaller. In this way, the source voltage of the fourth transistor M4 becomes small, and the on-current of the fourth transistor M4 becomes large. Further, the second impedance attenuation circuit 300 increases the source voltage of the fourth transistor M4 to increase the source voltage of the fourth transistor M4 by increasing the on-current of the fourth transistor M4. In this way, the on-current of the fourth transistor M4 becomes small, and negative feedback is introduced to the source of the fourth transistor M4, so that the impedance at the source of the fourth transistor M4 is reduced.

Accordingly, the second impedance damping circuit 300 may reduce the on-current of the fourth transistor M4 when the output voltage VOUT becomes small, so that the impedance at the source of the fourth transistor M4 decreases.

In summary, the impedance at the source of the fourth transistor M4 can be balanced with the impedance at the source of the third transistor M3.

The first impedance attenuation circuit 200 may change the on-current of the third transistor M3 when the output voltage VOUT changes, so that the impedance on the source of the third transistor M3 decreases to eliminate the pole of the source of the third transistor M3.

When the output voltage VOUT increases, the output voltage VOUT is transmitted to the source of the third transistor M3 by the compensation circuit 400, so that the source voltage of the third transistor M3 increases and the on-current of the third transistor M3 decreases. Further, the first impedance attenuation circuit 200 decreases the source voltage of the third transistor M3 by decreasing the on-current of the third transistor M3, thereby decreasing the source voltage of the third transistor M3. In this way, the on-current of the third transistor M3 increases, so that negative feedback is introduced to the source of the third transistor M3, and the impedance at the source of the third transistor M3 decreases.

Accordingly, the first impedance attenuation circuit 200 may increase the on-current of the third transistor M3 when the output voltage VOUT increases, so that the impedance at the source of the third transistor M3 decreases.

When the output voltage VOUT decreases, the output voltage VOUT is transmitted to the source of the third transistor M3 by the compensation circuit 400, so that the source voltage of the third transistor M3 decreases and the on-current of the third transistor M3 increases. Further, the first impedance attenuation circuit 200 increases the source voltage of the third transistor M3 by increasing the on-current of the third transistor M3, thereby increasing the source voltage of the third transistor M3. In this way, the on-current of the third transistor M3 becomes small, and negative feedback is introduced to the source of the third transistor M3, so that the impedance at the source of the third transistor M3 is reduced.

Accordingly, the first impedance attenuation circuit 200 may reduce the on-current of the third transistor M3 when the output voltage VOUT decreases, so that the impedance at the source of the third transistor M3 decreases.

At this time, the impedance at the source of the fourth transistor M4 and the impedance at the source of the third transistor M3 can be expressed by formula (1):

wherein r is _in3 To introduce negative feedback on the source of the fourth transistor M4 and the source of the third transistor M3A is a multiple of the decrease in the impedance at the source of the fourth transistor M4 and the impedance at the source of the third transistor M3, g _m3 To the impedance at the source of the fourth transistor M4 and the impedance at the source of the third transistor M3 when no negative feedback is introduced at the source of the fourth transistor M4 and the source of the third transistor M3.

Based on this, the pole on the source of the third transistor M3 can be expressed by formula (2):

wherein P is _M3 Is the pole on the source of the third transistor M3, r _in3 To introduce negative feedback at the source of the fourth transistor M4 and the source of the third transistor M3, cc is the capacitance provided by the compensation circuit 400, and a is the multiple of the decrease in the impedance at the source of the fourth transistor M4 and the impedance at the source of the third transistor M3.

Due to the pole P on the source of the third transistor M3 _M3 Relative to the previous pole p _2,SL Gm3/Cc is increased by a-fold, whereas a is typically able to provide a gain of at least 10-20 dB. Thus, the pole P on the source of the third transistor M3 _M3 Can be pushed by 1-2 orders of magnitude. Thus, the pole P on the source of the third transistor M3 is easily turned on _M3 The design is outside the UGB of the inner small loop SL' of the LDO.

To sum up, the pole P on the source of the third transistor M3 is eliminated _M3 。

The linear voltage stabilizing circuit, the chip and the electronic equipment can change the conduction current of the fourth transistor when the output voltage changes through the second impedance attenuation circuit. In this way, the source of the fourth transistor introduces negative feedback, reducing the impedance at the source of the fourth transistor, enabling the impedance at the source of the fourth transistor to be balanced with the impedance at the source of the third transistor. The first impedance attenuation circuit can change the on current of the third transistor when the output voltage changes. In this way, negative feedback is introduced into the source of the third transistor, so that the impedance at the source of the third transistor is reduced, and the magnitude of the pole at the source of the third transistor is increased. Further, it is easy to design the pole on the source of the third transistor outside the UGB of the inner small loop of the LDO. Therefore, the pole of the source electrode of the third transistor is eliminated, the pole number of the inner small loop of the LDO is reduced, and the stability of the inner small loop and the stability of the LDO are improved.

Based on the description of the above embodiments, an exemplary, one possible implementation of the first impedance attenuation circuit 200. Referring to fig. 6, fig. 6 is a schematic structural diagram of a linear voltage stabilizing circuit according to an embodiment of the present application. As shown in fig. 6, the first impedance attenuation circuit 200 may include: the first operational amplifier component A1 and the first resistor R1.

The first end of the first resistor R1 is electrically connected to the second end of the fifth transistor M5, the second end of the first resistor R1 is electrically connected to the second end of the third transistor M3, the positive phase input end of the first operational amplifier component A1 is electrically connected to the second end of the constant voltage output circuit 500, the negative phase input end of the first operational amplifier component A1 is electrically connected to the second end of the third transistor M3, and the output end of the first operational amplifier component A1 is electrically connected between the first end of the third transistor M3 and the second end of the first transistor M1.

The first end of the first resistor R1 is a first end of the first impedance attenuation circuit 200, the non-inverting input end of the first operational amplifier component A1 is a second end of the first impedance attenuation circuit 200, the second end of the first resistor R1 is a third end of the first impedance attenuation circuit 200, and the output end of the first operational amplifier component A1 is a fourth end of the first impedance attenuation circuit 200.

The first operational amplifier component A1 can perform operational amplification on the voltages at two ends of the first resistor R1 under the action of changing the voltages at two ends, and output the changed first voltage.

Wherein the first voltage is used to change the on-current of the third transistor M3.

When the output voltage VOUT increases, the source voltage of the third transistor M3 increases, the on-current of the third transistor M3 decreases, and the voltage across the first resistor R1 decreases. The voltage across the first resistor R1 is reduced, and the voltage across the first resistor R1 is amplified, thereby outputting a reduced first voltage and reducing the source voltage of the third transistor M3. Further, the on-current of the third transistor M3 becomes large. Thus, the source of the third transistor M3 introduces negative feedback.

When the output voltage VOUT decreases, the source voltage of the third transistor M3 decreases, the on-current of the third transistor M3 increases, and the voltage across the first resistor R1 increases. The voltage across the first resistor R1 is amplified by the voltage across the resistor R1, and the amplified first voltage is outputted to increase the source voltage of the third transistor M3. Further, the on-current of the third transistor M3 becomes small. Thus, the source of the third transistor M3 introduces negative feedback.

In summary, the first operational amplifier component A1 can perform operational amplification on the voltages at two ends of the first resistor R1 under the action of the change of the voltages at two ends, and output the changed first voltage, so that the source voltage of the third transistor M3 is changed. Further, the on-current of the third transistor M3 is changed. Thus, the source of the third transistor M3 introduces negative feedback.

Based on the description of the above embodiments, an exemplary, one possible implementation of the second impedance attenuation circuit 300. As shown in fig. 5, the second impedance attenuation circuit 300 may include: the second operational amplifier component A2 and the second resistor R2.

The first end of the second resistor R2 is electrically connected with the second end of the sixth transistor M6, the second end of the second resistor R2 is electrically connected with the second end of the fourth transistor M4, the positive phase input end of the second operational amplifier component A2 is electrically connected with the control end of the sixth transistor M6, the negative phase input end of the second operational amplifier component A2 is electrically connected with the second end of the fourth transistor M4, and the output end of the second operational amplifier component A2 is electrically connected between the first end of the fourth transistor M4 and the second end of the second transistor M2.

The second operational amplifier component A2 can perform operational amplification on the voltages at two ends of the second resistor R2 under the effect of changing the voltages at two ends, and output a changed second voltage, where the second voltage is used to change the on current of the fourth transistor M4.

The first end of the second resistor R2 is the first end of the second impedance attenuation circuit 300, the non-inverting input end of the second operational amplifier component A2 is the second end of the second impedance attenuation circuit 300, the second end of the second resistor R2 is the third end of the second impedance attenuation circuit 300, and the output end of the second operational amplifier component A2 is the fourth end of the second impedance attenuation circuit 300.

When the output voltage VOUT increases, the source voltage of the fourth transistor M4 increases, the on-current of the fourth transistor M4 decreases, and the voltages at both ends of the second resistor R2 decreases. The voltage across the second resistor R2 is reduced, and the voltage across the second resistor R2 is amplified, thereby outputting a reduced second voltage and reducing the source voltage of the fourth transistor M4. Further, the on-current of the fourth transistor M4 becomes large. Thus, the source of the fourth transistor M4 introduces negative feedback.

When the output voltage VOUT decreases, the source voltage of the fourth transistor M4 decreases, the on-current of the fourth transistor M4 increases, and the voltage across the second resistor R2 increases. Under the action of the voltage increase of the two ends of the second resistor R2, the voltage of the two ends is subjected to operational amplification, the second voltage which is increased is output, and the source voltage of the fourth transistor M4 is increased. Further, the on current of the fourth transistor M4 becomes small. Thus, the source of the fourth transistor M4 introduces negative feedback.

In summary, the second operational amplifier component A2 can perform operational amplification on the voltages at two ends of the second resistor R2 under the action of changing the voltages at two ends, and output the changed second voltage, so that the source voltage of the fourth transistor M4 is changed. Further, the on-current of the fourth transistor M4 is changed. Thus, the source of the fourth transistor M4 introduces negative feedback.

The first operational amplifier component A1 and the second operational amplifier component A2 are operational amplifier components.

Based on the description of the above embodiments, one possible implementation of an op-amp component is exemplary. Referring to fig. 7, fig. 7 is a schematic structural diagram of a linear voltage stabilizing circuit according to an embodiment of the present application. As shown in fig. 7, the op-amp assembly may include: and a seventh transistor M7.

The first terminal of the seventh transistor M7 is electrically connected to the second terminal of the voltage constant output circuit 500 or to the control terminal of the sixth transistor M6, the control terminal of the seventh transistor M7 is electrically connected to the second terminal of the third transistor M3 or to the second terminal of the fourth transistor M4, and the second terminal of the seventh transistor M7 is electrically connected to the second terminal of the third transistor M3 or to the second terminal of the fourth transistor M4.

When the operational amplifier component is the first operational amplifier component A1, the connection relationship of the operational amplifier component is that the first end of the seventh transistor M7 is electrically connected to the second end of the constant voltage output circuit 500, the control end of the seventh transistor M7 is electrically connected to the second end of the third transistor M3, and the second end of the seventh transistor M7 is electrically connected to the second end of the third transistor M3.

When the operational amplifier component is the second operational amplifier component A2, the connection relationship of the operational amplifier component is that the control end of the sixth transistor M6 is electrically connected to the first end of the seventh transistor M7, the control end of the seventh transistor M7 is electrically connected to the second end of the fourth transistor M4, and the second end of the seventh transistor M7 is electrically connected to the second end of the fourth transistor M4.

The resistance of the first resistor R1 and the resistance of the second resistor R2 need to be such that the voltage across the first resistor R1 and the voltage across the second resistor R2 are greater than the threshold voltage of the seventh transistor M7. In this way, the seventh transistor M7 may be turned on.

Next, a process of how the first operational amplifier component changes the on-current of the third transistor M3 will be described in detail with reference to fig. 7, so that the impedance on the source of the third transistor M3 is reduced, and the pole on the source of the third transistor M3 is eliminated.

When the output voltage VOUT increases, the on-current of the third transistor M3 decreases, and both the voltage at the first terminal of the seventh transistor M7 and the voltage at the control terminal of the seventh transistor M7 decrease, so that the on-current of the seventh transistor M7 decreases. In this way, the voltage of the second terminal of the seventh transistor T1 decreases, so that the operational amplifier device can output the reduced first voltage. Further, the on-current of the third transistor M3 becomes large. Thus, the source of the third transistor M3 introduces negative feedback, reducing the impedance on the source of the third transistor M3.

When the output voltage VOUT decreases, the on-current of the third transistor M3 increases, and both the voltage at the first terminal of the seventh transistor M7 and the voltage at the control terminal of the seventh transistor M7 increase, thereby increasing the on-current of the seventh transistor M7. In this way, the voltage at the second end of the seventh transistor M7 increases, so that the operational amplifier component can output the first voltage that becomes larger. Further, the on-current of the third transistor M3 becomes small. Thus, the source of the third transistor M3 introduces negative feedback, reducing the impedance on the source of the third transistor M3.

At this time, the gain of the first operational amplifier component is about g _m7 r _o /2. As such, the impedance at the source of the third transistor M3 can be expressed by equation (3):

wherein r is _in3 G is the impedance at the source of the third transistor M3 _m7 r _o And/2 is the gain of the first operational amplifier component.

Based on this, the pole on the source of the third transistor M3 can be expressed by formula (4):

wherein P is _M3 Is the pole on the source of the third transistor M3, r _in3 Cc is the capacitance provided by the compensation circuit 400 for the impedance at the source of the third transistor M3.

Due to the pole P on the source of the third transistor M3 _M3 Relative to the previous pole p _2,SL Gm3/Cc increases g _m7 r _o 2 times the pole P on the source of the third transistor M3 _M3 By 1 order of magnitude. Thus, the pole P on the source of the third transistor M3 is easily turned on _M3 The design is outside the UGB of the inner small loop SL' of the LDO.

Meanwhile, since the first terminal of the seventh transistor M7 and the control terminal of the seventh transistor M7 are connected through the first resistor R1 or the second resistor R2, a variation in the voltage VEA of the second terminal of the fifth transistor M5 does not cause a variation in the on-current of the seventh transistor M7. Therefore, the seventh transistor M7 still exhibits a high impedance state at the second terminal of the fifth transistor M5. Thus, designing the op-amp component in this way does not reduce the impedance at the second end of the fifth transistor M5. Therefore, the high gain of the LDO loop is maintained, and the high precision of the output voltage VOUT of the LDO is realized.

In summary, the operational amplifier component changes the on-current of the third transistor M3 and the on-current of the fourth transistor M4 through the seventh transistor M7, so that the source of the fourth transistor M4 and the source of the third transistor M3 introduce negative feedback, and the impedance on the source of the third transistor M3 and the impedance on the source of the fourth transistor M4 are reduced. In addition, the operational amplifier component designed in the mode is simple, practical, efficient and low in power consumption.

Based on the description of the above embodiments, another possible implementation of the op-amp component is exemplary. Referring to fig. 8, fig. 8 is a schematic structural diagram of a linear voltage stabilizing circuit according to an embodiment of the present application. As shown in fig. 8, the op-amp assembly may include: an eighth transistor M8, a ninth transistor M9, and a bias current device.

The first terminal of the eighth transistor M8 is electrically connected to the second terminal of the third transistor M3 or to the second terminal of the fourth transistor M4, the first terminal of the ninth transistor M9 and the first terminal of the bias current device are electrically connected to the second terminal of the voltage constant output circuit 500 or to the control terminal of the sixth transistor M6, the second terminal of the eighth transistor M8 is electrically connected to the second terminal of the bias current device, the control terminal of the eighth transistor M8 and the second terminal of the eighth transistor M8 are electrically connected to the control terminal of the ninth transistor M9, and the second terminal of the ninth transistor M9 and the third terminal of the bias current device are electrically connected to the second terminal of the third transistor M3 or to the second terminal of the fourth transistor M4.

The bias current device may include a first bias current meter IB1, a second bias current meter IB2, and a third bias current meter 2IB.

When the operational amplifier component is the first operational amplifier component A1, the connection relationship of the operational amplifier component is that the first end of the eighth transistor M8 is electrically connected to the second end of the third transistor M3, the first end of the ninth transistor M9 and the first end of the bias current device are both electrically connected to the second end of the constant voltage output circuit 500, and the second end of the ninth transistor M9 and the third end of the bias current device are both electrically connected to the second end of the third transistor M3.

When the operational amplifier component is the second operational amplifier component A2, the connection relationship of the operational amplifier component is that the first end of the eighth transistor M8 is electrically connected with the second end of the fourth transistor M4, the first end of the ninth transistor M9 and the first end of the bias current device are both electrically connected with the control end of the sixth transistor M6, and the second end of the ninth transistor M9 and the third end of the bias current device are both electrically connected with the second end of the fourth transistor M4.

The operational amplifier component changes the on current of the third transistor M3 through the eighth transistor M8 and the ninth transistor M9, so that the requirements of the eighth transistor M8 and the ninth transistor M9 on the power supply voltage VDD are lower. That is, the operational amplifier module designed in this way can be used both in the case of a low supply voltage VDD and in the case of a high supply voltage VDD.

The process of changing the on-current of the third transistor M3 through the eighth transistor M8 and the ninth transistor M9 is similar to the process of changing the on-current of the third transistor M3 through the seventh transistor M7, and will not be described here.

In summary, the on-current of the third transistor M3 is changed by the eighth transistor M8 and the ninth transistor M9, so that the source of the fourth transistor M4 and the source of the third transistor M3 introduce negative feedback, and the impedance at the source of the third transistor M3 and the impedance at the source of the fourth transistor M4 are reduced. In addition, the operational amplifier component designed in the mode has lower requirement on the power supply voltage.

It should be noted that: the transistors in fig. 4-8 may be metal oxide semiconductor field effect transistor devices. Meanwhile, the transistor can also be an insulated gate bipolar transistor device, an integrated gate rectifying thyristor device, a gate turn-off thyristor device, a silicon controllable rectifying device, a junction gate field effect transistor device, a MOS controlled thyristor device, a gallium nitride-based power device, a silicon nitride-based power device and the like. The embodiment of the present application is not particularly limited thereto.

Based on the description of the above embodiments, one possible implementation of the voltage constant output circuit 500 is exemplary. As shown in fig. 6, 7, and 8, the voltage constant output circuit 500 may include: a power tube P and a feedback sub-circuit 510.

The first end of the power tube P is used for being connected to the power supply voltage VDD, the control end of the power tube P is electrically connected to the second end of the first impedance attenuation circuit 200, the second end of the power tube P is electrically connected to the first end of the feedback sub-circuit 510, the second end of the compensation circuit 400 is electrically connected between the second end of the power tube P and the first end of the feedback sub-circuit 510, the second end of the feedback sub-circuit 510 is electrically connected to the control end of the second transistor M2, and the third end of the feedback sub-circuit 510 is grounded.

The first end of the power tube P is the first end of the voltage constant output circuit 500, the control end of the power tube P is the second end of the voltage constant output circuit 500, the second end of the power tube P is the fifth end of the voltage constant output circuit 500, the first end of the feedback sub-circuit 510 is the third end of the voltage constant output circuit 500, the second end of the feedback sub-circuit 510 is the fourth end of the voltage constant output circuit 500, and the third end of the feedback sub-circuit 510 is the sixth end of the voltage constant output circuit 500.

Based on the description of the above embodiments, one possible implementation of the voltage constant output circuit 500 is exemplary. As shown in fig. 6, 7, and 8, the feedback sub-circuit 510 may include a third resistor R3 and a fourth resistor R4.

The first end of the third resistor R3 is electrically connected to the second end of the power tube P, the second end of the compensation circuit 400 is electrically connected between the first end of the third resistor R3 and the second end of the power tube P, the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4, the control end of the second transistor M2 is electrically connected between the second end of the third resistor R3 and the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded.

The first end of the third resistor R3 is the first end of the feedback sub-circuit 510, the connection point between the second end of the third resistor R3 and the first end of the fourth resistor R4 is the second end of the feedback sub-circuit 510, and the second end of the fourth resistor R4 is the third end of the feedback sub-circuit 510.

Referring to fig. 9, the contents of the load transient response of the linear voltage stabilizing circuit provided in the present application are described in detail below, compared to the LDO under the conventional cascode miller compensation under the same load condition.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating a load transient response of a linear voltage stabilizing circuit according to an embodiment of the present application. In fig. 9, E is a linear voltage stabilizing circuit provided in the embodiment of the present application, F is an LDO under conventional cascode miller compensation, T is time, V is an output voltage of the LDO, IL1 is a first load current, and IL2 is a second load current.

Because the transient overcharging voltage of the linear voltage stabilizing circuit provided by the application is smaller than that of the LDO under the traditional cascode Miller compensation at the moment of T1. Therefore, the transient overcharging voltage of the linear voltage stabilizing circuit is smaller.

Because the difference between the output voltage of the LDO under IL1 and the output voltage of the LDO under IL2 of the linear voltage stabilizing circuit provided by the application is smaller than the difference between the output voltage of the LDO under IL1 and the output voltage of the LDO under IL2 of the traditional cascode Miller compensation. Therefore, the load adjustment rate of the linear voltage stabilizing circuit is smaller.

Since the present application provides a linear voltage regulator circuit with less and less ripple than LDO under conventional cascode miller compensation. Therefore, the ripple of the linear voltage stabilizing circuit provided by the application is less and smaller.

Finally, it should be noted that: the above embodiments are merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A linear voltage regulator circuit, the linear voltage regulator comprising: the device comprises a cascode differential operational amplifier, a first impedance attenuation circuit, a second impedance attenuation circuit, a compensation circuit and a voltage constant output circuit;

the cascode differential operational amplifier comprises a first cascode branch, a second cascode branch and a load transistor, wherein the first cascode branch comprises a first transistor and a second transistor which form a cascode structure, the second cascode branch comprises a third transistor and a fourth transistor which form a cascode structure, and the load transistor comprises at least one fifth transistor and at least one sixth transistor;

The first end of the fifth transistor, the first end of the sixth transistor and the first end of the constant voltage output circuit are all used for being connected with a power supply voltage, the second end of the fifth transistor is electrically connected with the first end of the first impedance attenuation circuit, the second end of the constant voltage output circuit is electrically connected with the second end of the first impedance attenuation circuit, the first end of the first impedance attenuation circuit is electrically connected with the second end of the first impedance attenuation circuit, the third end of the first impedance attenuation circuit is electrically connected with the second end of the third transistor, the first end of the third transistor is electrically connected with the second end of the first transistor, the fourth end of the first impedance attenuation circuit is electrically connected between the first end of the third transistor and the second end of the first transistor, the second end of the sixth transistor is electrically connected with the first end of the second impedance attenuation circuit, the second end of the second impedance attenuation circuit is electrically connected with the control end of the sixth transistor, the first end of the second impedance attenuation circuit is electrically connected with the second end of the second impedance attenuation circuit, the third end of the second impedance attenuation circuit is electrically connected with the second end of the fourth transistor, the first end of the fourth transistor is electrically connected with the second end of the second transistor, the fourth end of the second impedance attenuation circuit is electrically connected between the first end of the fourth transistor and the second end of the second transistor, the first end of the first transistor and the first end of the second transistor are both electrically connected with the first end of the common-source common-gate differential operational amplifier, and the second end of the common-source common-gate differential operational amplifier is grounded;

The first end of the compensation circuit is electrically connected with the fourth end of the first impedance attenuation circuit, and the second end of the compensation circuit is electrically connected with the third end of the voltage constant output circuit;

the control end of the fifth transistor is electrically connected with the control end of the sixth transistor, the control end of the third transistor is electrically connected with the control end of the fourth transistor, the control end of the first transistor is used for accessing reference voltage, the control end of the second transistor is electrically connected with the fourth end of the voltage constant output circuit, the fifth end of the voltage constant output circuit is used for outputting the output voltage of the linear voltage stabilizing circuit, and the sixth end of the voltage constant output circuit is grounded;

the second impedance attenuation circuit is used for changing the on current of the fourth transistor when the output voltage changes so as to reduce the impedance on the source electrode of the fourth transistor;

the first impedance attenuation circuit is used for changing the on current of the third transistor when the output voltage changes, so that the impedance on the source electrode of the third transistor is reduced, and the pole of the source electrode of the third transistor is eliminated.

2. The linear voltage stabilizing circuit according to claim 1, wherein the second impedance attenuation circuit is configured to increase an on-current of the fourth transistor when the output voltage becomes larger, so as to decrease an impedance on a source electrode of the fourth transistor;

the first impedance attenuation circuit is used for increasing the on current of the third transistor when the output voltage is increased, so that the impedance on the source electrode of the third transistor is reduced, and the pole of the source electrode of the third transistor is eliminated;

or,

the second impedance attenuation circuit is used for reducing the on current of the fourth transistor when the output voltage is reduced so as to reduce the impedance on the source electrode of the fourth transistor;

and the first impedance attenuation circuit is used for reducing the on-current of the third transistor when the output voltage is reduced, so that the impedance on the source electrode of the third transistor is reduced, and the pole of the source electrode of the third transistor is eliminated.

3. The linear voltage regulator circuit of claim 1, wherein the first impedance attenuation circuit comprises: the first operational amplifier component and the first resistor;

The first end of the first resistor is electrically connected with the second end of the fifth transistor, the second end of the first resistor is electrically connected with the second end of the third transistor, the positive phase input end of the first operational amplifier component is electrically connected with the second end of the constant voltage output circuit, the negative phase input end of the first operational amplifier component is electrically connected with the second end of the third transistor, and the output end of the first operational amplifier component is electrically connected between the first end of the third transistor and the second end of the first transistor;

the first operational amplifier component is used for carrying out operational amplification on the voltages at two ends of the first resistor under the action of the change of the voltages at the two ends of the first resistor, outputting changed first voltage, and the first voltage is used for changing the on current of the third transistor.

4. The linear voltage regulator circuit of claim 1, wherein the second impedance attenuation circuit comprises: the second operational amplifier component and the second resistor;

the first end of the second resistor is electrically connected with the second end of the sixth transistor, the second end of the second resistor is electrically connected with the second end of the fourth transistor, the positive phase input end of the second operational amplifier component is electrically connected with the control end of the sixth transistor, the negative phase input end of the second operational amplifier component is electrically connected with the second end of the fourth transistor, and the output end of the second operational amplifier component is electrically connected between the first end of the fourth transistor and the second end of the second transistor;

The second operational amplifier component is configured to perform operational amplification on the voltages at two ends of the second resistor under the effect that the voltages at two ends of the second resistor are changed, and output a changed second voltage, where the second voltage is used to change the on current of the fourth transistor.

5. The linear voltage regulator circuit of claim 3 or 4, wherein the op-amp assembly comprises: a seventh transistor;

the first end of the seventh transistor is electrically connected to the second end of the voltage constant output circuit or to the control end of the sixth transistor, the control end of the seventh transistor is electrically connected to the second end of the third transistor or to the second end of the fourth transistor, and the second end of the seventh transistor is electrically connected to the second end of the third transistor or to the second end of the fourth transistor.

6. The linear voltage regulator circuit of claim 3 or 4, wherein the op-amp assembly comprises: an eighth transistor, a ninth transistor, and a bias current device;

the first end of the eighth transistor is electrically connected with the second end of the third transistor or with the second end of the fourth transistor, the first end of the ninth transistor and the first end of the bias current device are electrically connected with the second end of the voltage constant output circuit or with the control end of the sixth transistor, the second end of the eighth transistor is electrically connected with the second end of the bias current device, the control end of the eighth transistor and the second end of the eighth transistor are electrically connected with the control end of the ninth transistor, and the second end of the ninth transistor and the third end of the bias current device are electrically connected with the second end of the third transistor or with the second end of the fourth transistor.

7. The linear voltage regulator circuit of claim 1, wherein the voltage constant output circuit comprises: a power tube and a feedback sub-circuit;

the first end of the power tube is used for being connected with the power supply voltage, the control end of the power tube is electrically connected with the second end of the first impedance attenuation circuit, the second end of the power tube is electrically connected with the first end of the feedback sub-circuit, the second end of the compensation circuit is electrically connected between the second end of the power tube and the first end of the feedback sub-circuit, the second end of the feedback sub-circuit is electrically connected with the control end of the second transistor, and the third end of the feedback sub-circuit is grounded.

8. The linear voltage regulator circuit of claim 7, wherein the feedback sub-circuit comprises a third resistor and a fourth resistor;

the first end of the third resistor is electrically connected with the second end of the power tube, the second end of the compensation circuit is electrically connected between the first end of the third resistor and the second end of the power tube, the second end of the third resistor is electrically connected with the first end of the fourth resistor, the control end of the second transistor is electrically connected between the second end of the third resistor and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.

9. A chip, comprising: a linear voltage regulator as claimed in any one of claims 1 to 8.

10. An electronic device, comprising: the chip of claim 9.