CN117731301A

CN117731301A - Method and apparatus for dynamically configuring operational parameters of a brain neural signal processing circuit

Info

Publication number: CN117731301A
Application number: CN202311758189.6A
Authority: CN
Inventors: 孙腾; 姚镭
Original assignee: Lingang National Laboratory
Current assignee: Lingang National Laboratory
Priority date: 2023-12-19
Filing date: 2023-12-19
Publication date: 2024-03-22

Abstract

The present disclosure relates to a method and apparatus for dynamically configuring operational parameters of a brain neural signal processing circuit, providing an apparatus for brain neural signal processing, comprising: an identification device configured to identify a signal characteristic of a cranial nerve signal; and a processing device configured to dynamically set a signal processing configuration based on the signal characteristics of the identified brain nerve signals to process the identified brain nerve signals according to the corresponding signal processing configuration, wherein the signal processing configuration includes a configuration related to the operational parameters of the brain nerve signal processing circuit.

Description

Method and apparatus for dynamically configuring operational parameters of a brain neural signal processing circuit

Technical Field

The present disclosure relates to the field of signal processing, and in particular to processing of cranial nerve signals.

Background

As a core component for exploring brain activities, brain-computer interfaces have become a hotspot in the directions of smart medicine, artificial intelligence, and neurological disease treatment research. The brain-computer interface technology is a key means for interaction between a person and a machine and between a person and artificial intelligence, wherein the brain-computer interface technology is required to record brain nerve signals, and has very important significance for the landing of the brain-computer interface technology.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

The present disclosure provides improved schemes for brain nerve signal recording.

In one aspect, the present disclosure provides an apparatus for brain neural signal processing, comprising: an identification device configured to identify a signal characteristic of a cranial nerve signal; and a processing device configured to dynamically set a signal processing configuration based on the signal characteristics of the identified cranial nerve signal to process the identified cranial nerve signal according to a corresponding signal processing configuration, wherein the signal processing configuration includes a configuration related to an operating parameter of a processing circuit for processing the cranial nerve signal.

In another aspect, the present disclosure also provides a method for brain neural signal processing, comprising: an identifying step including identifying a signal characteristic of the cranial nerve signal; and a processing step including dynamically setting a signal processing configuration based on the signal characteristics of the identified cranial nerve signal to process the identified cranial nerve signal according to the corresponding signal processing configuration, wherein the signal processing configuration includes a configuration related to an operating parameter of a processing circuit for processing the cranial nerve signal.

According to some embodiments of the present disclosure, there is provided an electronic device including: a memory; and a processor coupled to the memory, the processor configured to perform the method of any of the embodiments described in the present disclosure based on instructions stored in the memory.

According to some embodiments of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, causes a method of implementing any of the embodiments described in the present disclosure.

According to some embodiments of the present disclosure, there is provided a computer program product comprising instructions which, when executed by a processor, cause a method of implementing any of the embodiments described in the present disclosure.

According to some embodiments of the present disclosure, there is provided a computer program comprising program code which, when executed by a processor, causes a method of implementing any of the embodiments described in the present disclosure.

Other features, aspects, and advantages of the present disclosure will become apparent from the following detailed description of the embodiments and the accompanying drawings.

Drawings

Preferred embodiments of the present disclosure will be described below with reference to the accompanying drawings. The accompanying drawings, which are included to provide a further understanding of the disclosure, are incorporated in and form a part of this specification, and are incorporated in and constitute a part of this specification. It is to be understood that the drawings in the following description are only related to some embodiments of the present disclosure and are not intended to limit the present disclosure. In the drawings:

FIG. 1 is a schematic diagram of a conventional form of a neuro-recording circuit;

FIG. 2 is a schematic diagram of APs and LFP signals contained in a cranial nerve signal;

FIG. 3A is a schematic flow chart of a method of processing a cranial nerve signal according to an embodiment of the present disclosure;

fig. 3B is a schematic block diagram of a cranial nerve signal processing device according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of frequency bin selection of brain nerve signals at specific time intervals according to an embodiment of the present disclosure;

fig. 5A is a schematic diagram of a signal processing circuit according to one embodiment of the present disclosure.

Fig. 5B is a schematic block diagram of a circuit system according to one embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a signal processing circuit according to one embodiment of the present disclosure.

Fig. 7 is a schematic block diagram of a circuit system according to one embodiment of the present disclosure.

Fig. 8A to 8C are schematic circuit configurations in different signal detection modes according to an embodiment of the present disclosure.

Fig. 9 is a schematic block diagram of a circuit system according to another embodiment of the present disclosure.

Fig. 10 is a schematic diagram of a delta-delta sigma ADC circuit configuration for LFPs signal detection mode according to one embodiment of the present disclosure.

Fig. 11 is a schematic diagram of a delta-delta sigma ADC architecture according to one embodiment of the disclosure.

Fig. 12 is a schematic diagram of a coarse analog-to-digital conversion circuit in the APs signal detection mode.

Fig. 13 is a schematic diagram of a fine analog-to-digital conversion circuit in the APs signal detection mode.

Fig. 14 is a schematic diagram of a computer system in which a cranial nerve processing method according to an embodiment of the present disclosure may be implemented.

Furthermore, to avoid obscuring the disclosure with unnecessary detail, only the processing steps and/or apparatus structures that are closely related to at least the schemes according to the present disclosure are shown in the drawings, while other details that are not greatly relevant to the present disclosure are omitted. It should be appreciated that for ease of description, the dimensions of the various parts shown in the figures are not necessarily drawn to actual scale. It should also be noted that like reference numerals and letters in the figures indicate the same or similar items, and thus once an item is defined in one figure, it is not necessary to discuss it again for subsequent figures.

Detailed Description

Technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, but it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. The following description of the embodiments is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. It should be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect. The relative arrangement of parts and steps, numerical expressions and numerical values set forth in these embodiments should be construed as exemplary only, and not limiting the scope of the present disclosure unless specifically stated otherwise.

The term "comprising" and variations thereof as used in this disclosure is meant to encompass at least the following elements/features, but not to exclude other elements/features, i.e. "including but not limited to". Furthermore, the term "comprising" and variations thereof as used in this disclosure means an open-ended term that includes at least, but does not exclude other elements/features, namely "including but not limited to". Thus, inclusion is synonymous with inclusion. The term "based on" means "based at least in part on.

Reference throughout this specification to "one embodiment," "some embodiments," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. For example, the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Moreover, appearances of the phrases "in one embodiment," "in some embodiments," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may.

It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units. Unless specified otherwise, the concepts of "first," "second," etc. are not intended to imply that the objects so described must be in a given order, either temporally, spatially, in ranking, or in any other manner.

It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be understood as "one or more" unless the context clearly indicates otherwise.

The recording of the brain nerve signals is one of the key steps of the brain-computer interface technology, and the obtained original nerve signals are converted into digital code streams which can be identified by a computer, so that the method has very important significance for the landing of the brain-computer interface technology. A brain nerve signal may generally refer to a subcortical nerve signal, which is typically acquired as the original signal in analog form.

Nerve signal recording electronic systems generally include an Analog Front End (AFE) that processes the raw nerve signal appropriately, such as amplifying, filtering, etc., and then provides it to the ADC for conversion, and an Analog-to-Digital (ADC) that translates the Analog Front End pre-processed nerve signal into a stable Digital code stream, which is an important link and key to the design in the signal chain in nerve signal recording applications, as shown in fig. 1 (1). Common nyquist ADCs are SAR ADCs, flash ADCs, pipeline ADCs, etc., with sampling frequencies typically slightly greater than twice the maximum signal frequency. In conventional nerve signal recording systems, AFE can provide high gain to reduce the requirements on ADC resolution, but the dynamic range of detection is limited and can result in additional loss of area and power consumption. Moreover, under the current standard CMOS process, if a mismatch calibration module is not added, it is difficult for a general nyquist ADC to achieve an accuracy of 12-bit significance and above, the minimum voltage resolved is limited, and the voltage input with a large dynamic range is difficult to be correctly quantized by the ADC.

The nerve signal recording system can also be in a direct conversion mode, as shown in fig. 1 (2), the component parts of the AFE are abandoned, the analog-to-digital conversion is directly carried out through the ADC, the dynamic range of detection is increased, the common Sigma-Delta ADC (Sigma-Delta ADC) is different from the Nyquist ADC, the requirement of the Sigma-Delta ADC on the device matching is not high, the precision of more than 16 bits can be realized based on the oversampling and noise shaping technology, the problem of chip power consumption and area increase caused by the factors such as mismatch calibration is avoided, and the Sigma-Delta ADC becomes a hot spot for the research of a nerve signal recording chip. The key parameter of the Over-sampling technology is the Over-sampling rate (OSR), which can be represented by the ratio of the Over-sampling frequency to the nyquist frequency, generally takes 16-1024, the suppression effect of the too low OSR on the in-band quantization noise is not obvious, and the too high OSR, although the corresponding signal detection accuracy can be improved, can bring about an increase in power consumption, which is unfavorable for the requirement of low power consumption of the neural signal recording chip.

In order to achieve a low power consumption, small area neural signal recording electronic system, in the present disclosure, improved recording for brain neural signals is presented. In particular, the present disclosure proposes a dynamic configuration that enables dynamic configuration of a signal processing circuit, particularly a Sigma-Delta ADC, based on signal characteristics of a brain nerve signal, so that detection accuracy of the brain nerve signal can be maintained while area and power consumption loss of the ADC can be reduced.

In one aspect, the present disclosure proposes to accurately identify a cranial nerve signal, in particular to identify a signal characteristic, in particular a signal variation characteristic, of the cranial nerve signal in order to accurately distinguish the type of the cranial nerve signal, and then to be able to dynamically set a corresponding processing configuration for the cranial nerve signal recording based on the identified cranial nerve signal type. In this way, different types of cranial nerve signals can be effectively separated and processed in corresponding configurations/modes, respectively, without affecting the signal recording integrity. Therefore, the detection precision of the cranial nerve signals can be maintained, and the power consumption loss of the processing circuit is reduced.

On the other hand, the present disclosure also proposes to dynamically configure the processing circuit of the cranial nerve signal in an appropriate manner, in particular to be able to dynamically configure the cranial nerve signal processing circuit constructed based on Sigma-Delta ADC. In particular, the oversampling rate of the Sigma-Delta ADC, or the dynamic switching circuit configuration/circuit structure, can be dynamically adjusted according to the signal characteristics of the cranial nerve signal. Thus, circuit multiplexing can be realized, the circuit design is relatively simple, and the area and the power consumption loss of the circuit are reduced.

The brain nerve signal recording scheme according to the present disclosure will be described in detail below with reference to the accompanying drawings. In the context of the present disclosure, a brain neural signal record generally refers primarily to the process of processing an acquired brain neural signal to obtain a corresponding digital signal, which may also be referred to as brain neural signal processing or a portion thereof.

According to some embodiments of the present disclosure, the acquisition of the brain nerve signals may be achieved in various suitable ways, for example, a currently conventional brain nerve signal interface circuit such as a probe and an electrode of a front end, etc., and the acquired brain nerve signals may be input into a brain nerve signal recording device according to the present disclosure for subsequent processing. The brain nerve signal recording device to which the present disclosure relates may also be referred to as a nerve signal recording electronic system, which may be included in a nerve signal acquisition/recording system further comprising a probe and electrode device at the front end followed by the electronic system, as an example, in one implementation. According to some embodiments of the present disclosure, the acquired cranial nerve signals generally include analog signals, which will not be described in detail herein.

Furthermore, according to some embodiments of the present disclosure, the cranial nerve signal may also be subjected to some processing in advance, including but not limited to filtering, noise reduction, encryption, encoding, etc., prior to being input to the cranial nerve signal recording device according to the present disclosure, so that the transmitted signal is more secure and accurate. Of course, these treatments are not necessary.

The inventors noted that the coverage of the cranial nerve signals is very broad, and may include small-amplitude and rapid-changing action potential (Action Potentials, APs) signals and large-amplitude and slow-changing local field potential (Local Field Potentials, LFPs) signals, as shown in fig. 2, fig. 2 shows a schematic diagram of subcutaneous APs and LFPs signals of the brain; as an example, the amplitude of APs is between 10 μV and 1mV, the frequency is 300Hz to 10kHz, and for LFPs, the amplitude and frequency are 100 μV to 5mV and 0.5Hz to 1000Hz, respectively. The inventors have found that, as an example, the number of significant bits of the APs signal detection may need to be above 12 bits and the number of significant bits of the LFPs signal detection may be 8 bits in order to achieve accurate detection. However, in conventional operation, for example, single mode ADC is always used to detect APs and LFPs signals, especially higher order ADC, which has poor stability and large area and power consumption. The inventors therefore propose to dynamically adapt the processing configuration for the cranial nerve signals according to the signal characteristics of the cranial nerve signals, in particular according to the type of cranial nerve signals, in particular to dynamically adapt different processing configurations for different types of cranial nerve signals, without always adapting a fixed configuration, for example without always adapting a Sigma-Delta ADC of a fixed structure, which may reduce the processing power consumption without affecting the detection/processing accuracy of the cranial nerve signals.

Fig. 3A shows a flowchart for a brain nerve signal processing method according to an embodiment of the present disclosure. In the method 300, in step S301 (identification step), signal characteristics of a cranial nerve signal are identified; and in step S302 (processing step), a signal processing configuration is dynamically set based on the signal characteristics of the identified cranial nerve signal to process the cranial nerve signal according to the corresponding signal processing configuration. In some embodiments, the processing of the cranial nerve signal includes analog-to-digital conversion (ADC) of the cranial nerve signal to obtain a digital signal, which may be performed, for example, by a signal processing circuit, where the signal processing configuration is also somewhat equivalent to the configuration of the signal processing circuit. In particular, the signal processing circuit is accordingly a variety of suitable ADC circuits, preferably analog to digital conversion circuits built based on Sigma-Delta ADCs.

According to embodiments of the present disclosure, a type of a cranial nerve signal may be identified based on signal characteristics of the cranial nerve signal, the cranial nerve signal including at least one of a first type signal and a second type signal; and the processing step includes dynamically setting a signal processing configuration based on the identified type of cranial nerve signal. In particular, the first type of signal may comprise a small amplitude and rapidly varying action potential signal, such as the aforementioned APs signal, while the second type of signal may comprise a large amplitude and slowly varying local field signal, such as the aforementioned LFPs signal.

According to embodiments of the present disclosure, for a first type of signal, such as an APs signal, the processing configuration can be dynamically set to facilitate processing of the cranial nerve signal with high signal detection accuracy, which may correspond to high signal resolution. For the second type of signals, such as LFPs signals, the processing configuration can be dynamically set to process the cranial nerve signals with low signal detection accuracy, which may correspond to low signal resolution.

The setting of the dynamic configuration and the signal processing described above may be performed in an appropriate manner, for example, with the recording of a cranial nerve signal, or may be performed for a recorded cranial nerve signal after, for example, recording a cranial nerve signal of a specific length or a specific number of cranial nerve signals. In particular, it may be dynamically adjusted during operation as the signal characteristics are identified.

As an example, the processing circuit may initially process with relatively low conventional signal detection accuracy, and then dynamically adjust the processing circuit to perform processing with varying detection accuracy as the type of cranial nerve signal is identified. For example, the processing circuit may initially process with regular signal detection accuracy and may maintain the regular signal detection accuracy and may even decrease the signal detection accuracy for processing when the LFPs signal is identified, while the processing circuit may be dynamically adjusted to configure to process the cranial nerve signal with high signal detection accuracy when the APs signal is identified, after which if the LFPs signal is identified, the processing circuit may be adjusted to switch back to regular signal detection accuracy and may even decrease the signal detection accuracy for processing, and subsequent cranial nerve signals will similarly in turn dynamically adjust the signal detection accuracy based on signal identification, which will not be described in detail.

The identification of cranial nerve signals in embodiments according to the present disclosure will be described below. In embodiments of the present disclosure, identifying/detecting the cranial nerve signal includes, among other things, identifying based on signal characteristics of the cranial nerve signal to determine a type of the cranial nerve signal.

In some embodiments, the cranial nerve signal is identified based on its frequency characteristics. In particular, the type of the cranial nerve signal is identified from the frequency variation characteristics of the cranial nerve signal, in particular the frequency variation characteristics of a specific time interval, for example belonging to the first type or the second type. According to some embodiments, the frequency variation characteristic of the specific time interval may be, for example, a frequency variation value of the specific time interval, such as a variation value between frequencies of the cranial nerve signals separated by the specific time interval. As an example, the specific time interval may be 50 μs and the identified frequency change may be a frequency difference around 50 μs. As shown in fig. 4.

According to some embodiments, a signal whose signal frequency variation value is greater than or equal to a specific frequency variation threshold value at a specific time interval is determined as a first type of signal, and a signal whose signal frequency variation value is less than the specific frequency variation threshold value at a specific time interval is determined as a second type of signal. It should be noted that the specific time interval, the specific frequency change threshold may be set appropriately, for example, based on empirical analysis of the cranial nerve signal, by the operator's experience, etc., as well as to other appropriate values, which will not be described in detail herein. Table 1 shows exemplary APs and LFPs signal frequency identification/detection in accordance with the present disclosure.

TABLE 1

The signal frequency variation value may be calculated in various suitable ways for the cerebral nerve signal flow. For example, the calculation may be performed from a specific time in the acquired brain nerve signal flow, for example, a difference between the start of the brain nerve signal flow and a signal in the signal flow at a specific time interval, and the difference processing is performed on each signal in sequence along the brain nerve signal flow.

Such frequency variation calculations may be implemented in various ways. In one example, a delay circuit may be added that may receive the stream of cranial nerve signals and delay signals in the stream of cranial nerve signals for a particular time, thereby frequency-differencing the signals in the acquired stream of cranial nerve signals with the signals in the delayed stream of cranial nerve signals output by the delay circuit, thereby enabling determination of the frequency variation characteristics of the signals for the relevant particular time interval. In another example, a buffer may be provided to buffer the received brain nerve signal flow, and then from the beginning of the brain nerve signal flow, a frequency difference between the beginning signal of the brain nerve signal flow and a signal spaced apart therefrom by a specific time interval is extracted and sequentially calculated, so that a signal frequency variation characteristic of the relevant specific time interval can be determined.

It should be noted that the identification of the type of cranial nerve signal may also be performed in other ways. In some embodiments, this can be performed based on the amplitude characteristics of the cranial nerve signal. In particular, the type of the cranial nerve signal is identified from the amplitude variation characteristic of the cranial nerve signal, especially at a specific time interval. The amplitude is a voltage amplitude, and the amplitude change may indicate a voltage amplitude change, particularly a change value between amplitudes of the cranial nerve signals at specific intervals. As an example, the specific time period may be 50 μs and the identified amplitude change may be an amplitude difference, e.g. a voltage amplitude difference, around 50 μs.

In some embodiments, a signal having a signal amplitude variation value greater than or equal to a particular amplitude difference threshold value at a particular time interval is determined as a first type signal and a signal having a signal amplitude variation value less than the particular amplitude difference threshold value at the particular time interval is determined as a second type signal. As an example, the amplitude difference threshold may be set to any suitable value, e.g., based on empirical analysis of the cranial nerve signal, by an operator experience, etc., such as may be 0.6mV.

The signal amplitude variation values at specific time intervals may be calculated in various suitable ways for the cerebral nerve signal flow and the way for the signal amplitude variation value calculation may also be implemented in various suitable ways, as described above for the frequency variation calculation, which will not be described in detail here.

Dynamic setting of a processing configuration for a cranial nerve signal according to an embodiment of the present disclosure will be described below with reference to an embodiment. In embodiments of the present disclosure, the respective signal processing is dynamically configured based on the identified type of the cranial nerve signal, and in particular, the processing configuration for each type of the cranial nerve signal is dynamically set or adjusted based on, for example, whether the cranial nerve signal is a first type signal or a second type signal, so that the processing of each type of the cranial nerve signal can be adaptively optimized, while the apparatus or circuit for signal processing can be low-power consumption.

In embodiments of the present disclosure, the dynamic setting of the processing configuration of the cranial nerve signal may particularly refer to the dynamic setting or adjustment of the operation mode of the signal processing device of the cranial nerve signal. In some embodiments, the mode of operation of the signal processing device for the cranial nerve signal can be dynamically configured according to the type of the identified cranial nerve signal. For example, for a first type of signal, the signal processing device for the cranial nerve signal can operate in a first mode of operation, which may correspond to a high signal detection accuracy. For example, for a second type of signal, the signal processing device for the cranial nerve signal can operate in a second mode of operation, which may correspond to low signal detection accuracy.

The dynamic setting of the operating mode of the signal processing device can be implemented in various suitable ways, such as dynamic setting or adjustment of at least one of the operating parameters, the operating mode, the circuit configuration, etc. of the signal processing device.

In some embodiments, the operating parameters of the signal processing device may be dynamically set/adjusted according to the type of cranial nerve signal. In particular, for the first type of signal, a first operating parameter is set so that the processing circuit for a cranial nerve signal can operate with high signal detection accuracy, and for the second type of signal, a second operating parameter is set so that the processing circuit for a cranial nerve signal can operate with low signal detection accuracy. By way of example, the signal processing means may comprise various suitable processing circuits, including in particular an analog-to-digital converter (ADC), such as a Sigma-Delta ADC, where the operating parameter may be indicative of the sampling rate of the ADC, in particular the oversampling rate of the Sigma-Delta ADC. The first mode of operation may correspond to the Sigma-Delta ADC operating at a high oversampling rate (as an example of a first operating parameter) and the second mode of operation may correspond to the Sigma-Delta ADC operating at a low oversampling rate (as an example of a second operating parameter). It should be noted that ADCs in this disclosure, such as Sigma-Delta ADCs, may have various orders and be implemented by various suitable structures, as known in the art, and will not be described in detail herein.

Table 2 below shows sample rate switching based on frequency identification of exemplary APs and LFPs signals.

TABLE 2

Status of	Trigger condition	Trigger action
			APs detection	Within 50 mu s, fb-fa is more than or equal to 0.6kHz	Switching high oversampling rate
LFPs detection	Within 50 mu s, fb-fa < 0.6kHz	Switching low oversampling rate

It should be noted that the high and low oversampling rates may be settable/applicable, for example, to a Sigma-Delta ADC, and their correspondence with the APs and LFPs signals may be preferably set so that the correspondence may be found according to the recognition result of the cranial nerve signal, thereby enabling the Sigma-Delta ADC to operate according to the corresponding oversampling rate.

In some examples, the Sigma-Delta ADC may operate at two available oversampling rates, with a higher oversampling rate being applicable to the APs signal corresponding to the high oversampling rate mode and a lower oversampling rate being applicable to the LFPs signal corresponding to the low sampling rate mode. For example, the Sigma-Delta ADC may initially operate at a lower oversampling rate and switch to a higher oversampling rate upon identification of an APs signal, and then switch back to a lower oversampling rate upon identification of an LFP signal. In other examples, the Sigma-Delta ADC may operate at more than two available oversampling rates, and may switch between multiple oversampling rates depending on the type of cranial nerve signal identified. In particular, the Sigma-Delta ADC may operate at a plurality of available oversampling rates and may initially operate at an initial oversampling rate (preset or default oversampling rate), with signal processing, the sampling rate may be adjusted according to the identified signal type, for example, increasing the oversampling rate for the APs signal (which may correspond to a high oversampling rate mode) or maintaining or decreasing the oversampling rate for the LFPs signal (which may correspond to a low oversampling rate mode). Here, the correspondence between the plurality of available oversampling rates and the APs signal or LFPs signal may also be appropriately set and stored in advance, so that dynamic setting/adjustment of the oversampling rate may be performed with reference to the correspondence according to the signal detection/recognition result.

In some embodiments of the present disclosure, the manner of operation or circuit configuration of the processing circuit for the cranial nerve signal may be dynamically set according to the type of the identified cranial nerve signal. In particular, the signal processing circuit may be switched to different modes of operation for different types of cranial nerve signals to perform signal processing, for example, the different modes of operation may be implemented by different circuit configurations or circuit structures of the signal processing circuit. Here, it should be noted that in this case, the operating parameters of the signal processing circuit may remain substantially unchanged. Of course, the operating parameters of the signal processing circuit may also be set dynamically, as described above.

According to some embodiments of the present disclosure, for a first type of signal, processing can be performed in a first manner of operation corresponding to high signal detection accuracy. In particular, the first mode of operation may include expanding the number of significant bits of the analog-to-digital conversion. In some embodiments, expanding the number of significant bits of the analog-to-digital conversion may include performing a two-step analog-to-digital conversion on the cranial nerve signal, including: coarse analog-to-digital conversion for conversion of a specific number of high-order bits of the cranial nerve signal; and fine analog-to-digital conversion for conversion of remaining bits of the cranial nerve signal other than the specific number of high-order bits. As an example, the first type of cranial nerve signal is an APs signal, the detection accuracy of which may be 16 bits, a specific number of high-order bits may be appropriately set, for example, 8 bits, and the remaining bits are 8 bits other than the high-order bits of 8 bits.

According to some embodiments of the present disclosure, for the second type of signal, processing can be performed in a second manner of operation corresponding to low signal detection accuracy. In this case, this may be done by means of conventional or low signal detection accuracy analog-to-digital conversion, or additionally or alternatively, the detection/conversion accuracy may be further improved by additional processing. As an example, the second mode of operation may include further attenuating low frequency components in the cranial nerve signal. In some embodiments, attenuating low frequency components in the cranial nerve signal includes subtracting the current sampled input signal from the input signal sampled at the previous clock cycle and analog-to-digital converting the resulting signal.

In some embodiments, the signal processing means of the cranial nerve signal may be constructed based on an ADC circuit, in particular a Sigma-Delta ADC, and the aforementioned first and second modes of operation may be implemented by adjusting the circuit configuration or circuit structure of the Sigma-Delta ADC. In particular, based on a multiplexing of conventional circuit configurations or circuit structures, such as Sigma-Delta ADC, in operation, switching between different circuit configurations or circuit structures may be performed according to the type of the identified cranial nerve signal to achieve the respective first and second modes of operation, respectively. As another example, the step-wise operation in the first operation mode may also further correspond to different circuit configurations or circuit structures, e.g. the coarse analog-to-digital conversion and the fine analog-to-digital conversion may be referred to as a first sub-operation mode and a second sub-operation mode, respectively, and may be implemented by different circuit structures, respectively. According to the embodiment, the circuit structure can be switched in different analog-to-digital conversion stages to realize corresponding analog-to-digital conversion, so that the processing of the brain nerve signals is optimized. It should be noted that the names of the above-described operation modes are merely exemplary, and may be expressed by other names, for example, the above-described first sub-operation mode, second operation mode may be referred to as first to third operation modes, respectively, and may be switched accordingly according to signal types during signal processing.

According to some embodiments of the present disclosure, dynamic setting/adjustment of circuit configuration may be implemented in the case of circuit multiplexing. In particular, the adjustment circuit configuration can be set adaptively for different types of signals on the basis of the basic ADC, for example by means of different circuit connections, or by implementing switching-in or switching-out of additional components. In this way, the configuration can be adaptively adjusted in the case of circuit multiplexing without always using a single circuit structure or operation, and circuit power consumption can be optimized while maintaining detection accuracy. Furthermore, the multiplexed circuit structure, such as an ADC, in particular a Sigma-Delta ADC, may be a low order or low oversampling rate circuit, whereas the switching of the circuit structure enables a high and low detection accuracy conversion, which in particular further reduces the circuit power consumption.

According to embodiments of the present disclosure, the foregoing dynamic configuration/adjustment may be implemented by a corresponding device or component, such as a controller or component, capable of receiving the signal recognition/detection result and outputting a control signal for the signal processing device/signal processing circuit, such as controlling the signal processing device/signal processing circuit to adjust its operation mode, circuit configuration/structure, and so forth. It should be noted that the dynamic configuration/adjustment may be implemented as a separate component, chip, etc. separate from or also included or integrated in the signal recognition/detection component, signal processing circuit/device, etc. In some embodiments of the present disclosure, dynamic settings/adjustments may correspond to various suitable components, such as switches, and the like.

Fig. 3B shows a schematic block diagram of a processing device for brain nerve signals according to an embodiment of the present disclosure. The processing device 400 comprises identification means 401 configured to identify signal characteristics of the cranial nerve signals; and a processing device 402 configured to dynamically set a signal processing configuration based on the signal characteristics of the identified cranial nerve signals to process the cranial nerve signals according to the corresponding signal processing configuration.

In some embodiments, the identifying means may comprise a signal frequency identifier configured to identify a frequency variation characteristic of the neural signal and to identify the signal type based on the identified frequency variation characteristic of the neural signal. Here, the signal frequency identifier may be implemented in various suitable ways, and may include, for example, a frequency comparator, a frequency analyzer, a frequency detector, and so on.

In some embodiments, the frequency variation characteristic of the cranial nerve signal may include a signal frequency variation value of a specific time interval of the cranial nerve signal, and the signal frequency identifier includes a comparator configured to compare the signal frequency variation value of the specific time interval with a specific frequency variation threshold value, wherein a signal having the signal frequency variation value of the specific time interval greater than or equal to the specific frequency variation threshold value is determined as the first type signal, and a signal having the signal frequency variation value of the specific time interval less than the specific frequency variation threshold value is determined as the second type signal.

In some embodiments, the identifying means comprises a signal amplitude identifier configured to identify an amplitude variation characteristic of the neural signal and to identify the signal type based on the identified amplitude variation characteristic of the neural signal. The signal amplitude identifier may be implemented in a variety of suitable ways, and may include, for example, a voltage comparator, a voltage detector, and the like.

In some embodiments, the amplitude variation characteristic of the cranial nerve signal may include a signal amplitude variation value of a specific time interval of the cranial nerve signal, the signal amplitude identifier includes a comparator configured to compare the signal amplitude variation value of the specific time interval with a specific amplitude variation threshold, wherein a signal in which the signal amplitude variation value of the specific time interval is greater than or equal to the specific amplitude variation threshold is determined as the first type signal, and a signal in which the signal amplitude variation value of the specific time interval is less than the specific amplitude variation threshold is determined as the second type signal.

In some embodiments, the processing device comprises a control component configured to dynamically set an operating mode of the corresponding signal processing device for different types of cranial nerve signals, the operating mode comprising, for example, at least one of an operating parameter, an operating mode, a circuit configuration, etc. of the signal processing circuit. It should be noted that the control unit may also be located outside the processing device, which inputs the signal type recognition result and outputs a control signal for dynamically setting the operation mode to the processing device. As an example, it may be contained in the identification means, even outside the identification means and the processing means.

In some embodiments, the control means may comprise an operating parameter control means configured to set operating parameters of the corresponding signal processing device for different types of cranial nerve signals. The operating parameters may be various suitable parameters depending on the implementation of the signal processing means. For example, in case the signal processing means is an ADC, in particular a Sigma-Delta ADC, the operating parameter is the oversampling rate. In particular, the operating parameter control means may comprise an oversampling rate control means configured to set the signal processing circuit to operate at a high oversampling rate for the first type of signal and to operate at a low oversampling rate for the second type of signal. In some embodiments, the sampling rate control component may be implemented as various suitable components, such as switches and the like, that are capable of switching the oversampling rate of the ADC.

In some embodiments, the control means comprises switching means configured to switch the operation mode of the signal processing circuit or the circuit configuration of the signal processing circuit for different types of cranial nerve signals. As an example, the switching means may be in different switching states according to the type of the brain nerve signal, thereby achieving switching of the operation mode or the circuit configuration. The switching means may be implemented in various suitable ways, for example as a switch, and the change in the circuit configuration and thus the manner of operation is achieved by different communication states of the switch.

In some embodiments, the processing device may be configured to switch to a first mode of operation for processing the cranial nerve signal if the cranial nerve signal of the first type is identified. The first mode of operation may include processing the cranial nerve signal by expanding the number of significant bits of analog-to-digital conversion. In particular, in some embodiments, processing the cranial nerve signal by expanding the number of significant bits of the analog-to-digital conversion may include performing a step-wise analog-to-digital conversion on the cranial nerve signal, including: coarse analog-to-digital conversion for conversion of a specific number of high-order bits of the cranial nerve signal; and fine analog-to-digital conversion for conversion of remaining bits of the cranial nerve signal other than the specific number of high-order bits.

Here, the first operation mode may correspond to and be implemented by a first circuit configuration or a first circuit structure, which may also be referred to as a first processing circuit, in other words, the processing means may also be referred to as including the first processing circuit, and in case of the first type signal switch to the first processing circuit to perform the processing according to the first operation mode, as described above. In some embodiments, in a first mode of operation, the first processing circuit may be switched to a sub-circuit configuration or structure corresponding to coarse analog-to-digital conversion and fine analog-to-digital conversion, respectively, and may be referred to as a first processing sub-circuit and a second processing sub-circuit, respectively. It should be noted that the processing sub-circuits may also be optional, and their corresponding functions or operations may be implemented by the first processing circuit, even by the processing means itself, by different circuit structures/connections etc. Here, switching to the first operation mode may correspond to the switching means being in a first switching state to switch to or implement the first circuit configuration, and in the first switching state, the switching means may also be switched to a first sub-switching state and a second sub-switching state, respectively, to switch to or implement the first and second processing sub-circuit configurations, respectively.

In some embodiments, the processing device may be configured to switch to a second mode of operation for processing the cranial nerve signal if a second type of cranial nerve signal is identified. In this case, the second operation mode may correspond to an analog-to-digital conversion mode of a conventional or low signal detection accuracy, or additionally or alternatively, additional processing may be included to further improve the detection/conversion accuracy. As an example, the second mode of operation may include attenuating low frequency components in the cranial nerve signal. In some embodiments, attenuating low frequency components in the cranial nerve signal includes: the input signal sampled in the previous clock cycle is subtracted from the current sampled input signal, and the resulting signal is analog-to-digital converted.

Here, the second operation mode may correspond to and be implemented by a second circuit configuration or a second circuit structure, which may also be referred to as a second processing circuit, that is, the processing means may also be referred to as including the second processing circuit, and in case of a second type signal, switch to the second processing circuit to perform the processing according to the second operation mode, as described above. Here, switching to the second operation mode may correspond to the switching means being in the second switching state to switch to or implement the second circuit configuration.

It should be noted that the names of the above-mentioned circuit structures are only exemplary, and may be expressed by other names, for example, the above-mentioned first sub-circuit structure, second circuit structure may be referred to as first to third circuit structures, respectively, and may be switched accordingly according to the signal type during signal processing. Further, as an exemplary implementation, two of the above-described first to third circuit structures may be a common circuit structure, so that the circuit design may be simplified. For example, the first sub-circuit structure and the second circuit structure may be a common circuit structure.

The switching between the above-mentioned first and second circuit configurations or circuit configurations, and the switching between the first processing sub-circuit and the second processing sub-circuit, may be achieved by the aforementioned switching means being in different switching states. It should be noted that the above-described switching means may be a suitable number of parts. For example, the switching state corresponding to each operation mode and circuit configuration described above may be realized as a single component, and switching of the circuit configuration may be realized.

As another example, two or more components are also possible. As an example, the switching means may comprise two switching means, for example a first switching means corresponding to a first operating mode and a second switching means corresponding to a second operating mode, respectively. Wherein the switching to the first circuit configuration is enabled by the first switching means being in a specific state, e.g. in particular the first switching means being in different sub-states respectively being switchable to the first sub-circuit configuration and the second sub-circuit configuration, and the switching to the second circuit configuration is enabled by the second switching means being in a specific state. Of course, the switching means may also comprise other numbers of means and be in other suitable switching states, as long as switching between different modes/circuit configurations is enabled.

In some embodiments, the processing device includes an analog-to-digital conversion circuit configured to convert the cranial nerve signal to a digital signal. Preferably, the analog-to-digital conversion circuit comprises a Sigma-Delta ADC, e.g. can be constructed based on a Sigma-Delta ADC.

Implementations according to some exemplary embodiments of the present disclosure will be described below.

A first embodiment of the present disclosure relates to dynamically setting operating parameters of a processing circuit for a cranial nerve signal based on identification of the cranial nerve signal. In this case, the circuit configuration of the processing circuit for the cranial nerve signal may be substantially unchanged, but may be capable of operating under different operating parameters based on the difference in signal type. As an example, the processing circuit for the cranial nerve signal may be various suitable Sigma-Delta ADCs, such as a Sigma-Delta ADC of the first order, although it should be noted that it may be a Sigma-Delta ADC of various suitable orders. And the operating parameter may correspond to a Sigma-Delta ADC oversampling rate.

Fig. 5A illustrates a circuit design for dynamically switching over-sampling rates for brain neural signal recording based on frequency identification according to the present disclosure, wherein a signal frequency comparator is introduced to discriminate frequency variation characteristics of acquired neural signals, and then signal class is judged in order to switch over-sampling rates. The circuit is designed as a first order Sigma-Delta ADC, comprising a differential amplifier, an integrator, a signal frequency comparator, a quantizer, a sampling filter and a digital-to-analog converter (Digtial to Analog Converter, DAC). Which receives the acquired raw neural signals and outputs converted digital signals. In this circuit, a differential amplifier is inputted with an input signal and a feedback signal, and an integrator provides a function of shaping quantization noise, and the quantization noise of analog-to-digital conversion is modulated and shaped to move from a low frequency to a high frequency. The quantizer with different digits compares the signals and converts the signals into bit streams, and the extraction filter filters the bit streams to obtain higher conversion resolution.

Here, the signal frequency comparator may correspond to the signal recognition apparatus according to the present disclosure, and may be used for frequency recognition of APs and LFPs. Frequency identification may be implemented in a variety of suitable ways, such as spectral analysis, phase analysis, etc., which will not be described in detail herein. It should be noted that the arrangement of the signal frequency comparators shown in the figures is merely exemplary, and that the signal frequency comparators may also be arranged elsewhere in the circuit or otherwise access the ADC circuit, as long as they are able to detect signal classes and control the operation of the circuit based on the signal classes.

In operation, the initial state is set to a lower oversampling rate (such as osr=64) for detection of LFPs signals, signal identification is performed after acquiring the nerve signals, when the difference between the frequencies of the nerve signals before and after 50 μs is higher than 0.6kHz (fb-fa is equal to or greater than 0.6 kHz), the signal is identified as an APs signal, and the sampling switch is controlled to switch to a higher oversampling rate (such as osr=512) for APs detection; when the difference between the frequencies of the signals within 50 μs is below 0.6kHz (fb-fa < 0.6 kHz), then the LFPs signal is identified, and the sampling switch is controlled to switch back to a lower oversampling rate (e.g., osr=64) for LFPs detection, so that the oversampling rate can be reduced during LFPs signal detection phase, thereby reducing the power consumption of the overall Sigma-Delta ADC circuit.

Here, as an example, the sampling switch may correspond to the aforementioned control means, in particular the operating parameter control means, which may be used to dynamically set or switch the oversampling rate, which may be implemented in various suitable ways, such as may be used to control a sampling clock in a circuit or the like.

The various components in the circuit may be implemented in a variety of suitable ways. As an example, as shown in fig. 5B, the integrator may be implemented by a voltage controlled oscillator (Voltage Controlled Oscillator, VCO) circuit, and the quantizer may be comprised of a D flip-flop and an exclusive-or gate array, and the VCO output is sampled and then subjected to a first order differentiation to produce a digital output. In particular, a frequency identification/comparator is implemented here with a phase frequency detector (PFD, phase Frequency Detector) for comparison of the integrated frequencies. The core area of each signal recording channel chip layout is 80 μm, 100 μm=0.008 mm ² About, the power consumption can be reduced to below 100 mu W.

Compared with the conventional method for detecting the mixture of the LFP signals and the APs signals or removing the LFP signals by using a high-pass filter and only detecting the APs signals, in the embodiment of the disclosure, on the one hand, a phase frequency detector part is introduced into a common circuit structure of the Sigma-Delta ADC, and the brain cortex brain electrical signals APs and the LFP signals are classified by utilizing frequency identification, so that the integrity of the recording of the APs and the LFP signals is ensured, and the two signals are separated from the frequency domain. On the other hand, because LFPs have low requirements on resolution and long signal duration, while APs have high requirements on resolution and short signal duration, if the same oversampling rate is always maintained as that of APs detection in operation, a large power consumption loss will be generated, and in the scheme of the present disclosure, by dynamically adjusting the oversampling rate of Sigma-Delta ADC, the low oversampling rate and the high oversampling rate are switched for LFPs and APs signals, respectively, the chip power consumption loss can be effectively reduced.

A second embodiment of the present disclosure relates to dynamically setting a circuit configuration of a processing circuit for a brain nerve signal according to recognition of the brain nerve signal so that the processing circuit for the brain nerve signal can operate in different circuit configurations or operation manners. As shown in fig. 6, in particular, the components of the processing circuit are similar to those described above with reference to fig. 5A, except that switching of the detection mode or operation mode is performed based on the signal frequency identification result. As an example, the processing circuit for the cranial nerve signal may comprise various suitable ADCs, in particular Sigma-Delta ADCs, for example the circuit structure of which may be dynamically adjusted to achieve different modes of operation. In this embodiment, in the case where the basic ADC circuit can be multiplexed, by the structure of the switching circuit, it is realized that the processing, such as conversion, is performed with the corresponding circuit structure for different types of cranial nerve signals.

Fig. 7 shows a circuit design of a reusable brain-computer interface signal record for a dynamically switched ADC circuit configuration according to an embodiment of the disclosure. In particular, the circuit design may be implemented by setting the switch sw based on a basic ADC structure, such as a Sigma-Delta ADC ₀ The switching of the circuit configuration/circuit configuration is thereby realized by the setting of the switch, and multiplexing of circuit components can be realized between various circuit configurations/circuit configurations. Here, the switch sw ₀ For controlling the input access of the circuit, different connection conditions are indicated by 1 and 0, respectively, as an example. In particular, sw ₀ =1 indicates that the input signal can be connected to the circuit, sw0= ₀ The input signal may be indicated as no longer connected to the circuit.

The combination of the switches here may correspond to the aforementioned control means, in particular the switching means, whereas a change of the switch between 1 and 0 may correspond to a change of the operating state of the switching means. Note that the signal frequency identifying part is omitted here for the sake of simplicity. Table 3 below shows the circuit configuration switching for different types of signals of the present embodiment.

TABLE 3 Table 3

Here, the implemented circuit structure, e.g. a delta-sigma ADC, may be used in common for the conversion of LFPs signals, as well as for the coarse analog-to-digital conversion of APs, which may be implemented by a conventional or low oversampling rate delta-sigma ADC.

Fig. 8A illustrates a detection circuit of a second type of signal (LFPs signal) according to an embodiment of the present disclosure, which is implemented based on the circuit of fig. 7, in particular. Identity recognition Setting sw when the LFP signal is not ₀ =1 (which may correspond to the second state of the switching element, as an example), the LFPs signal detection mode is a conventional ΔΣ ADC, such as a general or Delta Sigma-Delta ADC, vin is used as an input signal to the circuit, and the LFPs ADC bit number may be 8 bit precision when converted into a digital code stream by the integrator and the quantizer. Fig. 8B and 8C illustrate detection circuits for a first type of signal (APs signal) according to embodiments of the present disclosure. In the APs signal detection mode, the switch sw is used for switching ₀ The two-step detection is realized by the state switching of the (2), so that the precision of the APs signal detection is improved by expanding the effective digit by utilizing Coarse analog-to-digital conversion (Coarse ADC) and Fine analog-to-digital conversion (Fine ADC). Fig. 8B shows a circuit configuration at the time of performing coarse analog-to-digital conversion. Based on the circuit configuration shown in fig. 7, sw is set or held ₀ =1 (corresponding to the first sub-state of the switching element, which may be the same as the aforementioned second state, as an example) to perform coarse conversion, the circuit configuration may be a conventional Sigma-Delta ADC, for example for performing high-bit (8-bit) conversion as used for LFP signal detection, and the integrator stores the remaining voltage after left that is not converted. Fig. 8C shows a circuit configuration at the time of performing fine analog-to-digital conversion. Set to sw by switch ₀ =0 (e.g., corresponding to the second sub-state of the switching element), the circuit structure is transformed into a cyclic structure ADC (cyclic ADC), the integrator is switched into an amplifier to amplify the residual signal, the residual voltage is further transformed into low bits (8 bits), and hardware multiplexing is implemented, thereby reducing the chip area. The number of significant bits detected by APs is more than 16 bits, and the number of significant bits detected by LFPs is 8 bits.

It should be noted that, equivalently, the switch sw described above ₀ It can be regarded as a switching means corresponding to the operating mode, wherein 1 and 0 correspond to different states of the switch, respectively, so that the switch effects switching of the circuit configuration by being in different states. As an example, consider that LFPs signals are dominant in cranial nerve signals, and thus in operation, switch sw ₀ The initial state of (1) can be set as sw ₀ =1, i.e. the processing circuit is in a conventional delta-sigma ADC structure, with signal recognition, when an APs signal is recognized, the processing circuit is electrically connected to the signal recognition circuitThe circuit switches to a two-step operating state, in particular, the circuit enters a coarse analog-to-digital conversion stage and then further sw ₀ Switching to 0, the circuit switches to a cyclic structure ADC so that a fine analog to digital conversion stage can be entered, after which further along with signal recognition, by switching the state of the switch, different types of brain nerve signals can be dynamically set to different structured circuits so as to optimize signal processing. In this case, the conventional ADC circuit, such as a conventional ΔΣ ADC, does not need to use a high oversampling rate, and can accurately detect various types of nerve signals only by switching different operation modes or circuit structures for different types of nerve signals, and circuit multiplexing also makes the circuit design simple and power consumption reduced.

Fig. 9 illustrates a circuit design of a reusable brain-computer interface signal record of another dynamically switched ADC circuit configuration according to an embodiment of the disclosure. In particular, the circuit design may be implemented by providing additional circuit components, such as Delta modulation components, switches sw, on the basis of a basic ADC structure, such as a Sigma-Delta ADC ₀ And sw ₁ The switching of the circuit configuration/circuit configuration is thereby realized by the setting of the switch, and multiplexing of circuit components can be realized between various circuit configurations/circuit configurations.

Here, two switches sw ₀ And sw ₁ Loop usable for controlling the access of a circuit, in particular a switch sw ₀ For controlling input access to the circuit, switch sw ₁ For controlling the access of the delta modulation component. As an example, for two switches sw ₀ And sw ₁ A different connection condition is indicated with 1 and 0, respectively. In particular, sw ₀ =1 indicates that the input signal can be connected to the circuit, sw ₀ =0 indicates that the input signal is no longer connected to the circuit, sw ₁ =1 may indicate that the delta modulation component is connected to the circuit, sw ₁ =0 may indicate that the delta modulation component is not connected to the circuit.

The combination of the switches here may correspond to the aforementioned control means, in particular the switching means, whereas a change of the switch between 1 and 0 may correspond to a change of the operating state of the switching means. Note that the signal frequency identifying part is omitted here for the sake of simplicity. Table 4 below shows the circuit configuration switching for different types of signals of the present embodiment.

TABLE 4 Table 4

Fig. 10 illustrates a detection circuit for a second type of signal (LFPs signal) according to an embodiment of the present disclosure, which is implemented in particular based on the circuit of fig. 9, and further applies a spectrum equalization technique, which may be implemented by applying delta modulation, for example as an ADC applying delta modulation. In the circuit structure, a Delta feedback loop, also called spectrum equalization technology, is added on the basis of the traditional Sigma-Delta ADC. In particular, based on the circuit configuration shown in fig. 9, sw is set when the LFPs signal is recognized ₀ sw ₁ =11 (which may correspond to the second state of the switching element, as an example), the LFPs signal is detected in a delta-delta sigma ADC, vin is taken as an input signal to the circuit, and is converted into a digital stream by the integrator and the quantizer. The LFP has a large duty ratio of low frequency components, the input signal sampled in the previous clock period can be subtracted from the input signal sampled currently through delta modulation, the input signal without the direct current component is obtained, the low frequency components of the input signal are greatly attenuated, the dynamic range requirement of the processed signal is reduced, the input range of the signal is improved, the quantization error is reduced, and more accurate measurement of the LFP is realized.

Delta modulation can be implemented in a variety of suitable ways, such as analog circuitry, digital circuitry, etc., and ADCs employing delta modulation can be implemented in a variety of suitable circuit configurations. Fig. 11 shows an exemplary circuit architecture design. As an exemplary implementation of the integrator, gm-C technology is advantageous to achieve sufficiently low quantization noise and signal distortion, adding a chopping function to both the input signal and the Gm-C filter back-end, eliminating the effect of circuit 1/f noise, and feeding back the Current signal through a Current Digital-to-Analog Converter (IDAC). The quantizer output signal is processed in the digital domain, in particular, a Counter (UP-down Counter, UP/DW Counter) forms a digital integrator implementation in the loop digital domain implementation delta modulation, and digital weighted averaging (data weighted averaging, DWA) provides first order noise shaping of IDAC element mismatch. Finally, the out-of-band quantization noise is suppressed by a decimation filter (dec. Filter) and anti-aliasing filtering of the out-of-band signal is provided. The overall design can reduce more area and power consumption than the circuit design of a second-order ADC.

It should be noted that the circuit configuration of the ADC described herein, which applies delta modulation, is merely exemplary, and delta modulation may be implemented in other suitable ways, e.g. depending on the particular implementation, only the delta modulation feedback loop may be accessed, without being collocated with the DAC feedback loop as shown. It should be noted that the general or conventional or Delta ADC circuits shown herein, such as Sigma-Delta ADC circuits, may be implemented by a variety of suitable circuit structures, as known in the art, and will not be described in detail herein.

Fig. 12-13 illustrate detection circuits for a first type of signal (APs signal) in accordance with embodiments of the present disclosure. In the APs signal detection mode, two-step detection is adopted, and the precision of APs signal detection is improved by expanding the effective digit through Coarse analog-to-digital conversion (Coarse ADC) and Fine analog-to-digital conversion (Fine ADC). Wherein, the detection of each step is realized by the state switching of the two switches. As an example, the switch states for the APs signal detection mode may correspond to the first state of the switching means, in particular, the switch states respectively corresponding to the detection of each step may also correspond to the sub-states comprised in the first state of the switching means.

Fig. 12 shows a circuit configuration at the time of performing coarse analog-to-digital conversion. Based on the circuit structure shown in fig. 9, sw is set ₀ sw ₁ =10 (e.g., corresponding to the first sub-state of the switching element) to perform coarse conversion, the circuit structure is transformed into an Delta Sigma-Delta ADC, high-bit (8-bit) conversion is performed as in a general or Delta Sigma-Delta ADC, and the integrator stores the remaining voltage after left that is not converted. Fig. 13 shows a circuit configuration at the time of performing fine analog-to-digital conversion. Set to sw by switch ₀ sw ₁ Execution of =00 (e.g. corresponding to the second sub-state of the switching means)The circuit structure is converted into a cyclic structure ADC (cyclic ADC) by fine conversion, the integrator is switched into an amplifier to amplify the residual signal, and the residual voltage is further converted into low-bit (8-bit) to realize hardware multiplexing, so that the chip area is reduced. The core area of each signal recording channel chip layout is 60 μm 80 μm=0.0048 mm ² The power consumption can be reduced to below 8 mu W. The number of significant bits detected by APs is more than 16 bits, and the number of significant bits detected by LFPs is 8 bits.

It should be noted that equivalently, the two switches sw described above ₀ 、sw ₁ It can also be considered as a first switching element corresponding to a first mode of operation and a second switching element corresponding to a second mode of operation, respectively, wherein for each switch a 1 can correspond to a first state of the switch and a 0 can correspond to a second state of the switch. Specifically, sw ₁ A 1 may indicate that the second switching means is set to the first state such that the circuit is switched to the second circuit configuration, in particular a delta-delta sigma ADC. sw (sw) ₀ A value of 1 may indicate that the first switching element is set to a first state to cause the circuit to switch to a first sub-circuit configuration, e.g., delta sigma-delta ADC, sw ₀ A 0 may indicate that the first switching component is set to a second state such that the circuit switches to a second sub-circuit configuration, such as a loop configuration ADC.

As an example, consider that LFPs signals are dominant in brain nerve signals, so in operation, two switches sw ₀ 、sw ₁ The initial state of (1) can be set as sw ₀ sw ₁ =11, i.e. the processing circuit is in delta-delta sigma ADC configuration, when the APs signal is identified as the signal is identified, sw ₁ Switching to 0, the circuit switches to a conventional or Delta Sigma-Delta ADC so that the coarse analog to digital conversion stage can be entered and then further sw ₀ Switching to 0, the circuit switches to a cyclic structure ADC so that a fine analog to digital conversion stage can be entered, after which further along with signal recognition, by switching the state of the switch, different types of brain nerve signals can be dynamically set to different structured circuits so as to optimize signal processing.

In this embodiment of the present disclosure, the switching of the circuit structure is implemented according to the frequency classification of LFPs and APs, and in particular, in the detection mode of APs, the mode of expanding bits by combining coarse analog-to-digital conversion and fine analog-to-digital conversion improves the resolution of the detection of APs. And in the LFP detection process, detection with proper precision can be realized by adopting a conventional ADC (analog-to-digital converter), and particularly, the requirement of reducing the dynamic range by delta modulation can be further introduced, so that the input signal range is improved. Moreover, the multiplexing circuit structure can be shared by hardware, so that the area requirement of chip design is greatly reduced, and meanwhile, the detection precision can be kept. On the other hand, no matter the detection mode of the LFP or the APs is adopted, the detection precision is improved without a large OSR, the recording of two signals can be met by keeping a relatively low OSR after frequency identification, and the power consumption loss of a circuit can be reduced.

It will be appreciated that in this embodiment, the OSR dynamic setting in the previous embodiment may also be combined, thereby enabling further improved detection accuracy while maintaining appropriate circuit power consumption losses.

Although the above-described embodiments are mainly for dynamically adjusting the configuration of a processing circuit for a brain nerve signal based on frequency identification of the brain nerve signal, including an operation parameter (such as an oversampling rate), an operation manner, or a circuit structure, etc., it should be noted that the operation manner of the above-described embodiments is also applicable to dynamic configuration based on amplitude identification of the brain nerve signal, and similar effects can be achieved, and will not be described in detail here.

According to some embodiments of the present disclosure, acquisition or recording of the cranial nerve signal may be accomplished in various suitable ways, particularly automatically or triggered. In some embodiments, the acquisition or recording of the cranial nerve signal can be performed automatically on a periodic basis, such as by periodically acquiring or recording the cranial nerve signal. In other embodiments, the acquisition or recording of the cranial nerve signal may also be triggered to be performed, for example, after a particular type of signal is detected, or upon request by a worker. In some embodiments, the acquisition or recording of the cranial nerve signal may be automatically stopped for a specific time, or stopped upon request or upon satisfaction of a specific condition.

Recording of cranial nerve signalsThe transmission may be in a suitable format, e.g. may be adapted for signal transmission, e.g. in a cable transmission mode in various suitable cable transmission formats, e.g. in a wireless transmission mode in various suitable wireless transmission formats, the wireless communication may follow suitable communication protocols and techniques, e.g. 4G, 5G, 6G, even future developed suitable communication protocols and techniques, e.g. WiFi, bluetooth ^TM Etc., and will not be described in detail herein.

In accordance with some embodiments of the present disclosure, along with the recorded cranial nerve signals, an identifier corresponding to the cranial nerve signals may also be transmitted together, which may be used to distinguish the cranial nerve signals from other sources of cranial nerve signals. This is particularly suitable in the case where the processing of the brain nerve signals from multiple sources is effected in a centralized manner, the identifier of the brain nerve signal may be used to verify whether the brain nerve signal is one that needs to be processed. As an example, the identifier of the cranial nerve signal may indicate the source of the cranial nerve signal, e.g., an identity ID of a person acquiring the cranial nerve signal, which may be used for authentication.

In addition, according to some embodiments of the present disclosure, various operations/processes according to the present disclosure, when implemented by software and/or firmware, may be installed from a storage medium or network to a computer system having a dedicated hardware structure, such as the computer system 1400 shown in fig. 14, which is capable of performing various functions including functions such as those described previously, and the like, when various programs are installed. Fig. 14 is a block diagram illustrating an example structure of a computer system employable in an embodiment of the present disclosure.

In fig. 14, a Central Processing Unit (CPU) 1401 executes various processes according to a program stored in a Read Only Memory (ROM) 1402 or a program loaded from a storage section 1408 to a Random Access Memory (RAM) 1403. In the RAM 1403, data required when the CPU 1401 executes various processes and the like is also stored as needed. The central processing unit is merely exemplary, and it may also be other types of processors, such as the various processors or processing means described previously. The ROM 1402, RAM 1403, and storage portion 1408 may be various forms of computer-readable storage media, as described below. It should be noted that although ROM 1402, RAM 1403, and storage 1408 are shown in FIG. 14 separately, one or more of them may be combined or located in the same or different memories or storage modules.

The CPU 1401, ROM 1402, and RAM 1403 are connected to each other via a bus 1404. An input/output interface 1405 is also connected to the bus 1404.

The following components are connected to the input/output interface 1405: an input section 1406 such as a touch panel, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, or the like; an output portion 1407 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; a storage section 1408 including a hard disk, a tape, or the like; and a communication section 1409 including a network interface card such as a LAN card, a modem, and the like. The communication section 1409 allows communication processing to be performed via a network such as the internet. It will be readily appreciated that while the various devices or modules in the electronic device 1400 are shown in fig. 14 as communicating via the bus 1404, they may also communicate via a network or other means, wherein the network may include a wireless network, a wired network, and/or any combination of wireless and wired networks.

The driver 1410 is also connected to the input/output interface 1405 as needed. A removable medium 1411 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed on the drive 1410 as needed, so that a computer program read out therefrom is installed into the storage portion 1408 as needed.

In the case of implementing the above-described series of processes by software, a program constituting the software can be installed from a network such as the internet or a storage medium such as the removable medium 1411.

The processes described above with reference to flowcharts may be implemented as computer software programs according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program loaded on a computer readable medium, the computer program comprising program code for performing a method according to embodiments of the present disclosure. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 1409, or installed from the storage means 1408, or installed from the ROM 1402. When executed by the CPU 1401, the computer program performs the above-described functions defined in the method of the embodiments of the present disclosure.

It should be noted that in the context of this disclosure, a computer-readable medium can be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable medium may be a computer readable signal medium or a computer readable storage medium or any combination of the two. In the present disclosure, a computer readable storage medium may be any non-transitory medium containing or storing a program, such as, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing.

According to still further embodiments of the present disclosure, there is provided a computer readable storage medium having stored thereon instructions or a computer program which, when executed by a processor, implements the method of any of the embodiments described in the present disclosure.

According to some embodiments of the present disclosure, there is provided a computer program product comprising instructions which, when executed by a processor, implement the method of any of the embodiments described in the present disclosure.

In some embodiments, there is also provided a computer program comprising: instructions which, when executed by a processor, cause the processor to perform the method of any of the embodiments described above. For example, the instructions may be embodied as computer program code. In an embodiment of the present disclosure, computer program code for performing the operations of the present disclosure may be written in one or more programming languages, including but not limited to an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer, for example, through the internet using an internet service provider.

The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.

Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

The above description is merely illustrative of some embodiments of the present disclosure and of the principles of the technology applied. It should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The scope of the disclosure in the present disclosure is not limited to the specific combination of the above technical features, but also includes other technical features formed by any combination of the above technical features or their equivalents without departing from the concept of the disclosure.

Claims

1. An apparatus for brain neural signal processing, comprising:

an identification device configured to identify a signal characteristic of a cranial nerve signal; and

a processing device configured to dynamically set a signal processing configuration based on the signal characteristics of the identified brain nerve signals to process the identified brain nerve signals according to the corresponding signal processing configuration,

wherein the signal processing configuration comprises a configuration related to an operating parameter of a processing circuit for processing the cranial nerve signal.

2. The apparatus of claim 1, wherein the identifying means is configured to identify at least one of a frequency variation characteristic or an amplitude variation characteristic of the brain nerve signal and determine a signal type of the brain nerve signal based on the identified at least one of the frequency variation characteristic or the amplitude variation characteristic of the nerve signal.

3. The apparatus according to claim 1 or 2, wherein,

the cranial nerve signals include at least one of a first type of signal and a second type of signal,

wherein the first type of signal comprises a small amplitude and rapidly varying action potential signal,

wherein the second type of signal comprises a local field signal of large amplitude and slowly varying.

4. The apparatus according to claim 2 or 3, wherein the identifying means comprises a signal frequency identifier configured to identify a signal frequency variation value of a specific time interval of the cranial nerve signal,

wherein a signal whose signal frequency variation value is equal to or greater than a specific frequency variation threshold value at a specific time interval is determined as a first type signal, and a signal whose signal frequency variation value is less than the specific frequency variation threshold value at a specific time interval is determined as a second type signal.

5. The apparatus of claim 2 or 3, wherein the identifying means comprises a signal amplitude identifier configured to identify a signal amplitude variation value of a specific time interval of the cranial nerve signal,

wherein a signal whose signal amplitude variation value is greater than or equal to a specific amplitude variation threshold value at a specific time interval is determined as a first type signal, and a signal whose signal amplitude variation value is less than the specific amplitude variation threshold value at a specific time interval is determined as a second type signal.

6. The apparatus of any of claims 3-5, wherein,

the processing means are configured to dynamically set, for the identified different types of cranial nerve signals, corresponding operating parameters for the processing of the cranial nerve signals,

Wherein for the first type of signal, a first operating parameter is set so that the processing circuit for the cranial nerve signal can operate with high signal detection accuracy, and for the second type of signal, a second operating parameter is set so that the processing circuit for the cranial nerve signal can operate with low signal detection accuracy.

7. The device of any of claims 1-6, wherein the processing circuit comprises an analog-to-digital conversion (ADC) circuit configured to convert the cranial nerve signal to a digital signal,

wherein the processing circuit comprises a Sigma-Delta ADC, and

wherein the operating parameter comprises an oversampling rate of the Sigma-Delta ADC.

8. The apparatus of claim 7, wherein the processing device comprises an oversampling rate control component configured to dynamically set an oversampling rate of the Sigma-Delta ADC for the identified different types of cranial nerve signals.

9. The device of claim 8, wherein the sample rate control component is configured to set the Sigma-Delta ADC to operate at a high oversampling rate for a first type of signal and to set the Sigma-Delta ADC to operate at a low oversampling rate for a second type of signal.

10. The apparatus of claim 8 or 9, wherein the sample rate control component comprises a sample switch of a Sigma-Delta ADC.

11. A method for brain neural signal processing, comprising:

an identifying step including identifying a signal characteristic of the cranial nerve signal; and

a processing step including dynamically setting a signal processing configuration based on the signal characteristics of the identified cranial nerve signal to process the identified cranial nerve signal according to the corresponding signal processing configuration,

12. The method of claim 11, wherein the identifying step includes identifying at least one of a frequency variation characteristic or an amplitude variation characteristic of the cranial nerve signal and determining a signal type of the cranial nerve signal based on the identified at least one of the frequency variation characteristic or the amplitude variation characteristic of the cranial nerve signal.

13. The method according to claim 11 or 12, wherein,

14. The method of claim 12 or 13, wherein the identifying step identifies signal frequency variation values for specific time intervals of the cranial nerve signal,

15. The method of claim 12 or 13, wherein the identifying step includes identifying signal amplitude variation values for specific time intervals of the cranial nerve signal,

16. The method according to any one of claims 13-15, wherein,

the processing step includes dynamically setting corresponding operating parameters for the identified different types of cranial nerve signals for processing of the cranial nerve signals,

17. The method of any of claims 11-16, wherein the processing circuit comprises an analog-to-digital conversion (ADC) circuit configured to convert the cranial nerve signal to a digital signal,

wherein the processing circuit comprises a Sigma-Delta ADC, and

18. The apparatus of claim 17, wherein the processing step includes a sample rate control step for dynamically setting an oversampling rate of the Sigma-Delta ADC for the identified different types of signals.

19. The method of claim 18, wherein the sampling rate control step comprises setting the Sigma-Delta ADC to operate at a high oversampling rate for a first type of signal and setting the Sigma-Delta ADC to operate at a low oversampling rate for a second type of signal.

20. An electronic device, comprising:

a memory; and

a processor coupled to the memory, the memory having instructions stored therein that, when executed by the processor, cause the electronic device to perform the method of any of claims 11-19.

21. A computer readable storage medium having stored thereon a computer program which when executed by a processor results in the implementation of the method according to any of claims 11-19.

22. A computer program product comprising instructions which, when executed by a processor, cause the method according to any one of claims 11-19 to be implemented.