CN117727754A - Semiconductor structure and electrostatic protection circuit - Google Patents

Abstract

The present disclosure relates to a semiconductor structure and an electrostatic protection circuit. The semiconductor structure includes a substrate and a plurality of transistor cells. The transistor unit includes: the grid electrode, the source region, the drain region and the silicide blocking layer extend to the upper part of the shallow groove isolation structure along the second direction; the source region and the drain region are respectively positioned in the active regions at two sides of the grid electrode and extend along the second direction; a silicide blocking layer is located at least between the drain region and the gate electrode. At least one transistor unit in a first target area at the center of the active area is taken as a first target unit, and at least one transistor unit in a second target area at the edge of the active area is taken as a second target unit; the width of the silicide blocking layer in the first target cell is greater than the width of the silicide layer in the second target cell, the width of the silicide blocking layer being its dimension in the first direction. The present disclosure is advantageous for improving robustness and electrostatic protection capability of an electrostatic protection circuit.

Description

Semiconductor structure and electrostatic protection circuit

Technical Field

The present disclosure relates to the field of semiconductor integrated circuits, and more particularly, to a semiconductor structure and an electrostatic protection circuit.

Background

With the development of semiconductor integrated circuits, the size of semiconductor devices is smaller and smaller, the junction depth in the semiconductor structure is shallower and the gate oxide layer (GOX) is thinner and thinner, so that the threat of electrostatic discharge (Electro Static Discharge, ESD for short) to the performance of the semiconductor devices is greater and greater. In addition, due to the introduction of metal Silicide (silicon) process, the electrostatic breakdown of the semiconductor device becomes more sharp, and even causes the semiconductor device to burn out when serious. Therefore, in a semiconductor integrated circuit, each transistor cell in the ESD device is generally arranged in a multi-finger cross parallel structure (multi-finger) to electrostatically protect the semiconductor integrated circuit.

However, as the number of fingers (fingers) formed of source and drain regions in the multi-finger interdigitated parallel structure increases, the turn-on of each transistor cell corresponding to each finger is not uniform. In general, compared with the transistor cells in the edge area, the transistor cells in the central area of the multi-finger cross parallel structure are turned on in advance, so that a great amount of external charges are concentrated on the transistor cells in the central area, and the transistor cells in the central area are easily burnt before the transistor cells in the edge area are turned on, so that the electrostatic protection function of the ESD device is disabled.

Disclosure of Invention

Based on this, in a first aspect, embodiments of the present disclosure provide a semiconductor structure for improving the robustness and electrostatic protection capability of an electrostatic protection circuit in a semiconductor integrated circuit.

In some embodiments, a semiconductor structure includes a substrate and a plurality of transistor cells. The substrate is provided with a shallow slot isolation structure which is arranged in a ring shape, and an active area which is positioned in the ring of the shallow slot isolation structure. The plurality of transistor units are distributed in the active area side by side in the first direction. The transistor cell includes a gate electrode, a source region, a drain region, and a silicide blocking layer. The grid extends to the upper side of the shallow groove isolation structure along the second direction. The source region and the drain region are respectively positioned in the active regions at two sides of the grid electrode and extend along the second direction. A silicide blocking layer is located at least between the drain region and the gate electrode. Wherein the second direction intersects the first direction. In the embodiment of the disclosure, at least one transistor unit located in a first target area in the center of an active area is taken as a first target unit, and at least one transistor unit located in a second target area at the edge of the active area is taken as a second target unit. The width of the silicide blocking layer in the first target cell is greater than the width of the silicide layer in the second target cell, the width of the silicide blocking layer being its dimension in the first direction.

In some embodiments, the disclosed embodiments reference a transistor cell centered in an active region and maximum width a width of a silicide blocking layer in the reference cell. Among the plurality of transistor cells located on either side of the reference cell in the first direction, the width of the silicide blocking layer of each transistor cell gradually decreases in a direction away from the reference cell.

In some embodiments, among the plurality of transistor cells located on either side of the reference cell in the first direction, the width of the silicide blocking layer of each transistor cell is reduced in value in a direction away from the reference cell.

In some embodiments, any two adjacent transistor cells share the same source region. Any two adjacent transistor cells share the same drain region. The number of the reference units is two, and the two reference units share the same drain region in the center of the active region and are symmetrically arranged by taking the drain region as a symmetrical center.

In some embodiments, silicide barriers in two transistor cells sharing the same drain region are in communication at both ends of the drain region extending in the second direction so as to surround the periphery of the drain region.

In some embodiments, the distance of the drain region to the gate electrode in the first direction is greater than the distance of the source region to the gate electrode in the first direction.

In some embodiments, the semiconductor structure further comprises a ground electrode. The grounding electrode is annularly arranged on the outer side of the shallow slot isolation structure, which is away from the active area.

In some embodiments, the substrate has a first type well region, and the shallow trench isolation structure and the active region are located within the first type well region. The source region and the drain region are respectively a second type doped region. Wherein the silicide blocking layer at least covers part of the surface of the drain region.

In some embodiments, the semiconductor structure further includes a source contact layer and a drain contact layer. The source contact layer at least covers part of the surface of the source region. The drain contact layer is positioned on the surface of the drain region which is not covered by the silicide blocking layer.

In a second aspect, the present disclosure also provides, according to some embodiments, an electrostatic protection circuit. The electrostatic protection circuit is applied to an integrated circuit. The electrostatic protection circuit comprises a semiconductor structure as described in the first aspect of the embodiments of the present disclosure. The grid electrode is electrically connected with the source region.

Embodiments of the present disclosure may/have at least the following advantages:

in the embodiment of the disclosure, at least one transistor unit located in a first target area in the center of the active area is taken as a first target unit, at least one transistor unit located in a second target area at the edge of the active area is taken as a second target unit, the width (i.e. the dimension in the first direction) of the silicide blocking layer in the first target unit is larger than that of the silicide blocking layer in the second target unit, and the resistance between the grid electrode and the drain region in the first target unit is at least relatively increased, so that the current flowing through the first target unit in the electrostatic discharge process is relatively reduced, and the time from heat accumulation to thermal failure of the first target unit can be effectively prolonged compared with that of the second target unit. In this way, in the process of performing electrostatic protection based on the semiconductor structure, the first target unit is turned on before the second target unit (i.e. when the transistor units arranged side by side are asynchronously turned on), but the widths of silicide blocking layers in the first target unit and the second target unit are different, so that the time from heat accumulation to heat failure of the first target unit can be adaptively prolonged, and the robustness and the electrostatic protection capability of the electrostatic protection circuit where the semiconductor structure is located are improved.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic diagram of a semiconductor structure provided in some embodiments;

FIG. 2 is a schematic partial cross-sectional view of the semiconductor structure shown in FIG. 1 along the AA' direction;

FIG. 3 is a schematic diagram of another semiconductor structure provided in some embodiments;

FIG. 4 is a schematic diagram of a GGNMOS electrostatic discharge circuit provided in some embodiments;

fig. 5 is a graph showing the current versus voltage for two transistor cells provided in some embodiments during electrostatic discharge.

Reference numerals illustrate:

1-substrate, STI-shallow trench isolation structure, 11-first target region, 12-second target region, 2-transistor cell, 21-gate, 211-gate dielectric layer, 21A-gate extraction electrode, 22-source, 22A-source extraction electrode, 23-drain, 23A-drain extraction electrode, 24-silicide barrier layer, 2A-first target cell, 2 b-second target cell, 2 c-reference cell, 3-ground electrode, 3A-ground electrode extraction electrode, 41-source contact layer, 42-drain contact layer.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," or "connected to" …, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Electrostatic discharge (Electrostatic Discharge, ESD) refers to the transfer of charge caused by objects having different electrostatic potentials being in close proximity or in direct contact with each other. When an object with electrostatic charge (i.e., electrostatic source) is in contact with another object, there will be a flow of charge to offset the voltage by the principle of charge neutralization for these two objects with different electrostatic potentials. In most cases, ESD processes tend to produce transient pulsed currents (i.e., ESD currents), especially when a live conductor or a live human body holding a metal object produces a spark discharge to a ground conductor, which can be tens of amperes or even hundreds of amperes in intensity.

In a semiconductor integrated circuit, a multi-finger cross-finger gate grounded N-type metal oxide semiconductor (GGNMOS) device is generally used as an electrostatic discharge protection structure. In the multi-finger cross parallel structure, since the transistor cells corresponding to the center finger (finger) are far from the ground electrode of the edge of the substrate and the other transistor cells are relatively close to the ground electrode of the edge of the substrate, the transistor cells in the center region have a larger substrate resistance, and the substrate resistances of the other transistor cells are smaller. And for GGNMOS devices, the larger the substrate resistance, the easier the turn-on of the transistor cell. Therefore, in the electrostatic discharge process of the multi-finger cross parallel structure, the turn-on of each transistor unit corresponding to each finger is not uniform, and the transistor unit in the central area of the multi-finger cross parallel structure is turned on in advance compared with the transistor unit in the edge area, so that a great amount of external charges are concentrated on the transistor unit in the central area, and the transistor unit in the central area is easily burnt before the transistor unit in the edge area is turned on, thereby further causing the failure of the electrostatic protection function of the ESD device.

Based on this, in a first aspect, embodiments of the present disclosure provide a semiconductor structure for improving the robustness and electrostatic protection capability of an electrostatic protection circuit in a semiconductor integrated circuit.

In some embodiments, referring to fig. 1, a semiconductor structure includes a substrate 1 and a plurality of transistor cells 2. The substrate 1 has shallow trench isolation structures 11 arranged in a ring shape, and an active region located within the ring of shallow trench isolation structures 11. The plurality of transistor cells 2 are distributed side by side in the first direction (e.g. X-direction) in the active region. The transistor cell 2 comprises a gate 21, a source region 22, a drain region 23 and a silicide blocking layer 24. The gate 21 extends in a second direction (e.g., Y-direction) over the shallow trench isolation structure STI. The source region 22 and the drain region 23 are respectively located in the active regions on both sides of the gate electrode 21 and extend in a second direction (e.g., Y direction). Wherein the second direction intersects the first direction.

In some examples, with continued reference to fig. 1, any two adjacent transistor cells 2 share the same source region 22. Any two adjacent transistor cells 2 share the same drain region 23.

The semiconductor structure provided by the embodiment of the disclosure adopts a multi-finger cross-parallel structure (multi-finger). In the multi-finger cross parallel structure, a plurality of transistor cells 2 are connected in parallel and any adjacent two of the transistor cells 2 share the same source region 22 and any adjacent two of the transistor cells 2 share the same drain region 23. That is, the source regions 22 and the drain regions 23 of the plurality of transistor cells 2 are alternately arranged to form an interdigital. In this semiconductor structure, since the transistor cells 2 corresponding to the fingers are connected in parallel, the voltages across the transistor cells 2 are equal.

In some embodiments, with continued reference to fig. 1, the distance from drain region 23 to gate 21 in the first direction (e.g., X-direction) is greater than the distance from source region 22 to gate 21 in the first direction (e.g., X-direction).

In some embodiments, with continued reference to fig. 1, a silicide blocking layer 24 is located at least between drain region 23 and gate 21. That is, the silicide blocking layer 24 may be located only between the drain region 23 and the gate electrode 21, for example, as understood in conjunction with fig. 1 and 2, the silicide blocking layer 24 covers a portion of the surface of the drain region 23. Alternatively, the silicide blocking layer 24 may be located between the drain region 23 and the gate 21 and between the source region 22 and the gate 21, for example, the silicide blocking layer 24 may cover a portion of the surface of the drain region 23 and a portion of the surface of the source region 22. The following embodiments of the present disclosure are illustrated with the silicide blocking layer 24 being located only between the drain region 23 and the gate 21, but it will be appreciated that other possible implementations of the silicide blocking layer 24 are also possible.

Illustratively, the material of the silicide blocking layer 24 includes, but is not limited to, an oxide, for example, the material may be silicon dioxide (SiO ₂ ）。

It should be noted that, in some embodiments, please continue to refer to fig. 1, silicide blocking layers 24 in two transistor units 2 sharing the same drain region 23 are connected at two ends of the drain region 23 extending along the second direction (for example, the Y direction) so as to surround the periphery of the drain region 23. In this way, the resistance between the drain region 23 and the gate electrode 21 in the corresponding transistor unit 2 can be increased by the silicide blocking layer 24, so as to improve the problem of poor withstand voltage of the semiconductor structure due to the shallow junction formed by adopting the lightly doped drain structure (Light Doped Drain, abbreviated as LDD) in the semiconductor structure. Also, embodiments of the present disclosure may regulate the resistance between the drain region 23 and the gate electrode 21 by regulating the width of the silicide blocking layer 24. Illustratively, the larger the width of the silicide blocking layer 24, the greater the resistance between the drain region 23 and the gate 21 of the corresponding transistor cell 2.

In some embodiments, please continue to refer to fig. 1, with at least one transistor cell 2 in the first target region 11 at the center of the active region being a first target cell 2a, and at least one transistor cell 2 in the second target region 12 at the edge of the active region being a second target cell 2b. The width of the silicide blocking layer 24 in the first target unit 2a is greater than the width of the silicide layer in the second target unit 2b, the width of the silicide blocking layer 24 being its dimension in the first direction.

In some examples, with continued reference to fig. 1, the width of the silicide blocking layer 24 of at least one first target cell 2a located within the first target region 11 in the center of the active region is, for example, w1, the width of the silicide blocking layer 24 of at least one transistor cell 2 located within the intermediate region between the first target region 11 and the second target region 12 is, for example, w2, and the width of the silicide blocking layer 24 of at least one second target cell 2b located within the second target region 12 at the edge of the active region is, for example, w3. Wherein w1 > w2 > w3.

It should be noted that in the multi-finger cross parallel structure, the transistor cell 2 located at the center of the active region is far from the substrate edge, and the transistor cell 2 located at the edge of the active region is near to the substrate edge, so that the substrate resistance of the transistor cell 2 located at the center of the active region is greater than the substrate resistance of the transistor cell 2 located at the edge of the active region. The transistor cell 2 is turned on more easily as the substrate resistance is larger. During the electrostatic protection of the semiconductor structure, the transistor unit 2 located in the center of the active region is turned on in advance with respect to the other transistor units 2.

In the embodiment of the disclosure, at least one transistor unit 2 in the first target region 11 located at the center of the active region is a first target unit 2a, at least one transistor unit 2 in the second target region 12 located at the edge of the active region is a second target unit 2b, and the width (i.e. the dimension in the first direction) of the silicide blocking layer 24 in the first target unit 2a is larger than the width of the silicide blocking layer 24 in the second target unit 2b, so that the resistance between the gate 21 and the drain region 23 in the first target unit 2a is at least relatively increased, and the current flowing through the first target unit 2a during the electrostatic discharge process is relatively reduced, so that the time for heat accumulation to thermal failure of the first target unit 2a can be effectively prolonged compared with that of the second target unit 2b. In this way, in the process of performing electrostatic protection based on the semiconductor structure, the first target unit 2a is turned on before the second target unit 2b (i.e. when the transistor units 2 arranged side by side are turned on asynchronously), but the widths of the silicide blocking layers 24 in the first target unit 2a and the second target unit 2b are different, so that the time for the first target unit 2a to accumulate heat to fail thermally can be adaptively prolonged, thereby improving the robustness and the electrostatic protection capability of the electrostatic protection circuit in which the semiconductor structure is located.

It should be noted that the number of the first target unit 2a, the second target unit 2b, and the transistor unit 2 in the middle area in the embodiment of the disclosure may be one or more, which is not limited in the embodiment of the disclosure.

In other embodiments, referring to fig. 3, the transistor cell 2 located at the center of the active region is used as the reference cell 2c, and the width (i.e., the dimension in the first direction) of the silicide blocking layer 24 in the reference cell 2c is used as the maximum width. Among the plurality of transistor cells 2 located on either side of the reference cell 2c in the first direction (e.g., X-direction), the width of the silicide blocking layer 24 of each transistor cell 2 (i.e., the dimension in the first direction) gradually decreases in a direction away from the reference cell 2 c.

In some examples, referring to fig. 3, the number of reference cells 2c in the semiconductor structure may be two, that is, the two reference cells 2c may share the same drain region 23 and be symmetrically disposed about the drain region 23 as a symmetry center, specifically, axisymmetric in the first direction (for example, X direction) about a center line of the drain region 23 extending along the Y direction as a symmetry center. Accordingly, the plurality of transistor cells 2 in the semiconductor structure may be axisymmetric in the first direction (for example, X direction) with respect to the center line of symmetry along which the aforementioned drain region 23 extends in the Y direction.

The silicide blocking layers 24 in the two transistor cells 2 which are located on both sides of the same drain region 23 in the first direction (for example, X direction) and share the drain region 23 have the same width.

In some examples, referring to fig. 3, with the width of the silicide blocking layer 24 in the reference cell 2c being w0 (i.e., the maximum width), the width of the silicide blocking layer 24 in each of the transistor cells 2 located on either side of the reference cell 2c and distributed in a direction away from the reference cell 2c is w01, w02, w03, etc. in order, where w0 > w01 > w02 > w03 … ….

In the embodiment of the disclosure, the width (i.e., the dimension in the first direction) of the silicide blocking layer 24 of each transistor unit 2 gradually decreases in the direction away from the reference unit 2c, and accordingly, the resistance between the drain region 23 and the gate 21 of each transistor unit 2 gradually decreases in the direction away from the reference unit 2c, so that the current flowing through each transistor unit 2 during the electrostatic discharge can gradually increase in the direction away from the reference unit 2 c. In this way, the transistor unit 2 located in the center of the active region has a longer heat accumulation time than the transistor unit 2 located at the edge of the active region due to the early turn-on and turn-on, so that the uniformity of heat accumulation on each transistor unit 2 during the electrostatic discharge process is improved by relatively reducing the current flowing through the transistor unit 2 in the center of the active region (i.e., slowing down the heat accumulation speed of the transistor unit 2 in the center of the active region).

In some embodiments, among the plurality of transistor cells 2 located on either side of the reference cell 2c in the first direction (e.g., X-direction), the width of the silicide blocking layer 24 of each transistor cell 2 (i.e., the dimension in the first direction) decreases in value in a direction away from the reference cell 2 c.

Here, the decrease in the width (i.e., the dimension in the first direction) of the silicide blocking layer 24 of each transistor unit 2 and the like means: the difference in width of the silicide blocking layers 24 of any two adjacent transistor units 2 is a constant or substantially constant value.

In addition, the width (i.e., the dimension in the first direction) of the silicide blocking layer 24 of each transistor unit 2 is gradually reduced, which may also be expressed as: a step-down or a group-down, etc., which is not limiting to the present disclosure.

It is to be appreciated that in some embodiments, the width (i.e., the dimension in the first direction) of the silicide blocking layer 24 of the one or more target transistor cells located in the central region of the active region is greater than the width of the silicide blocking layer 24 of the one or more target transistor cells located in the edge region of the active region. That is, the embodiments of the present disclosure may further increase the resistance between the drain region 23 and the gate 21 in the target transistor unit by selectively increasing the width of the silicide blocking layer 24 of the transistor unit 2 (i.e., the target transistor unit) that is easy to turn on and turn off in each transistor unit 2, so as to reduce the current flowing through the target transistor unit during the electrostatic discharge process, thereby purposefully extending the time from the heat accumulation to the thermal failure of the target transistor unit, and further improving the robustness and the electrostatic protection capability of the electrostatic protection circuit in which the semiconductor structure is located.

It should be noted that, in some embodiments, the silicide blocking layer 24 may also be located between the source region 22 and the gate 21, and regulate the resistance between the source region 22 and the gate 21 of the transistor unit 2. The regulation of the width of the silicide blocking layer 24 between the source region 22 and the gate 21 may be achieved with reference to some of the embodiments of the present disclosure described earlier, which will not be described in detail in this disclosure.

For example, the transistor unit 2 may be a Grounded Gate 21N-type metal oxide semiconductor (GGNMOS) for short.

To sum up, in some embodiments of the present disclosure, taking each transistor unit 2 in the semiconductor structure as a Grounded Gate N-type metal oxide semiconductor (GGNMOS) as an example, before and after the width adjustment of the silicide blocking layer 24 of the transistor unit 2, the voltage-dependent variation curve (i.e. the discharge curve) of the current on the transistor unit 2 during the electrostatic discharge process is verified, and the verification result is shown in fig. 5.

It should be noted that, referring to fig. 4, in the GGNMOS, the gate 21 and the source region 22 are shorted to the substrate 1 of the semiconductor structure and grounded, and a parasitic triode (which may be equivalent to an NPN parasitic triode) is present in the GGNMOS, and a low-impedance discharge path is formed between the drain region 23 of the GGNMOS and the substrate 1 through the parasitic triode, so that an ESD-generated electrostatic discharge current I _ESD The discharge can be performed from the drain region 23 of the GGNMOS through the discharge path (the flow direction of the current in the GGNMOS during the electrostatic discharge is shown by the arrow in fig. 4), thereby realizing the electrostatic protection function. Wherein the electrostatic discharge current passes through the substrate resistor R in the process of discharging _sub 。

It should be noted that, as understood from fig. 4 and fig. 5 (a), when the voltage on the GGNMOS reaches the primary breakdown voltage V _t1 When parasitic triode in GGNMOS breaks down once (e.g. avalanche breakdown) and turns on, electrostatic discharge current I _ESD Through which parasitic transistor it flows to the substrate 1 for bleeding. After breakdown, the GGNMOS exhibits negative resistance, and the discharge curve is turned back (snap-back) to a point (V) _t1 ，I _t1 ). As the discharge process proceeds, the GGNMOS turns back to the sustain point (V _h ，I _h ) After changing to positive resistance again, on GGNMOSThe voltage and current start to increase synchronously. With the further progress of the discharging process, the temperature of the GGNMOS is gradually increased due to the thermal effect, and when the voltage on the GGNMOS reaches the second breakdown voltage V _t2 When GGNMOS breaks down secondarily (i.e. thermally breaks down) and thermally fails, its discharge curve enters the thermal failure region, and the thermal failure point is (V _t2 ，I _t2 ）。

For example, referring to fig. 5 (a), before the silicide blocking layer 24 is subjected to width adjustment (i.e., the width of the silicide blocking layer 24 of the GGNMOS is increased), the second breakdown voltage of the GGNMOS is V _t2 The voltage on GGNMOS is controlled by the maintaining voltage V _h Increase to a second breakdown voltage V _t2 The time required is short (and the heat accumulation in the GGNMOS is faster at this time), and the GGNMOS is liable to be thermally disabled.

For example, referring to fig. 5 (b), after the silicide blocking layer 24 of each transistor cell 2 in the first target cell 2a is subjected to width adjustment (i.e., the width of the silicide blocking layer 24 of the GGNMOS is increased), the secondary breakdown voltage of the GGNMOS is V _t2 '. Compared with the graph (a) in FIG. 5, the second breakdown voltage is obviously improved, and the voltage on the GGNMOS is relatively prolonged from the maintenance voltage Vh to the second breakdown voltage V _t2 The' required time (and slowing down the heat build-up in the GGNMOS) prolongs the time for effective electrostatic protection of the GGNMOS.

From the above, by increasing the width of the silicide blocking layer 24 of the transistor cell 2 in the embodiments of the present disclosure, the resistance between the drain region 23 and the gate 21 of the transistor cell 2 is increased without changing the foldback (snap-back) characteristic of the transistor cell 2, i.e., without changing the foldback point (V _t1 ，I _t1 ) And maintenance point (V) _h ，I _h ). Therefore, the embodiment of the disclosure can effectively prolong the time from heat accumulation to heat failure of the transistor unit 2 on the premise of not changing the foldback characteristic, and effectively improve the robustness and the electrostatic protection capability of the semiconductor structure.

In some embodiments, referring to fig. 1, the semiconductor structure further comprises a ground electrode 3. The grounding electrode 3 is annularly arranged on the outer side of the shallow trench isolation structure STI, which faces away from the active region.

In some examples, the ground electrode 3 is electrically connected to the substrate 1.

By way of example, the material of the substrate 1 may be any suitable substrate material known in the art, for example at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon carbon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and also include multilayer structures of these semiconductors, and the like, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or may be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), and the like, which is not limited by the present disclosure.

In some examples, substrate 1 has a first type well region within which shallow trench isolation structures STI and active regions are located. The source region 22 and the drain region 23 are respectively second type doped regions.

The first type well region may be an N type well region or a P type well region, for example.

The ground electrode 3 is illustratively a doped region of the first type.

Illustratively, the second type doped region and the first type well region are of different conductivity types. For example, the first type well region is an N type well region, the second type doped region is a P type doped region, and vice versa, the first type well region is a P type well region, and the second type doped region is an N type doped region.

Illustratively, the isolation material of the shallow trench isolation structure STI is an insulating material, including but not limited to oxide. For example, the isolation material of the shallow trench isolation STI may be silicon dioxide (SiO ₂ ）。

Illustratively, the shape of the shallow trench isolation structure STI includes, but is not limited to, a rectangular ring or a circular or elliptical ring, etc.

Illustratively, the orthographic projection of the gate 21 onto the substrate 1 extends beyond the active region in a second direction (e.g., the Y-direction).

Illustratively, the material of the gate 21 includes, but is not limited to, polysilicon.

In some examples, as will be appreciated in conjunction with fig. 2, a gate dielectric layer 211 is disposed between the gate electrode 21 and the active region of the substrate 1, and the material of the gate dielectric layer 211 includes, but is not limited to, oxide. For example, the gate dielectric layer may be made of silicon dioxide (SiO 2).

In some examples, as will be appreciated in conjunction with fig. 1 and 2, the semiconductor structure further includes a drain region extraction electrode 23A, a source region extraction electrode 22A, a gate extraction electrode 21A, and a ground electrode extraction electrode 3A. Wherein the drain region extraction electrode 23A is electrically connected with the drain region 23; the gate lead-out electrode 21A is electrically connected with the gate 21; the source region extraction electrode 22A is electrically connected with the source region 22; the ground electrode lead electrode 3A is electrically connected to the ground electrode 3.

Illustratively, the orthographic projection of the gate extraction electrode 21A onto the substrate 1 is located outside the active region.

Illustratively, the drain region extraction electrode 23A, the source region extraction electrode 22A, the gate extraction electrode 21A, and/or the ground electrode extraction electrode 3A may employ conductive pillars or conductive interconnection structures including conductive pillars, and may be constituted of conductive pillars and metal leads, for example. The conductive posts may be formed of a metallic material, for example.

In some embodiments, referring to fig. 2, the semiconductor structure further includes a source contact layer 41 and a drain contact layer 42. The source contact layer 41 covers at least a part of the surface of the source region 22. The drain contact layer 42 is located on the surface of the drain region 23 not covered by the silicide blocking layer 24.

In some examples, the semiconductor structure further includes a ground electrode contact layer. The ground electrode contact layer covers at least both sides of the ground electrode 3 facing away from the center in the first direction (e.g., X-direction).

It should be noted that, with continued reference to fig. 2, a source contact layer 41 is located between the source region 22 and the source region extraction electrode 22A, a drain contact layer 42 is located between the drain region 23 and the drain region extraction electrode 23A, and a ground electrode contact layer is located between the ground electrode extraction electrode 3A and the ground electrode 3.

Illustratively, the source contact layer 41, drain contact layer 42, and/or ground electrode contact layer include, but are not limited to, a silicide layer.

In the preparation of the semiconductor structure, the silicide blocking layer 24 is formed before the silicide layer and covers a portion of the surface of the drain region 23 between the gate electrode 21 and the drain region 23, so that the surface of the drain region 23 covered with the silicide blocking layer 24 does not form a silicide layer when the silicide layer is prepared, thereby increasing the resistance between the gate electrode 21 and the drain region 23. Also, in forming the silicide layer, it is necessary to form the silicide layer in the etched region of the silicide block layer 24 by etching the silicide block layer 24.

In the embodiment of the disclosure, by providing the source contact layer 41, the drain contact layer 42 and/or the ground electrode contact layer, the contact resistance between the test source region 22 and the source region extraction electrode 22A, between the drain region 23 and the drain region extraction electrode 23A and between the ground electrode 3 and the ground electrode extraction electrode 3A is effectively reduced, which is beneficial to improving the discharge capability of the semiconductor structure to electrostatic discharge current, thereby being beneficial to improving the electrostatic protection capability of the semiconductor structure.

In a second aspect, the present disclosure also provides, according to some embodiments, an electrostatic protection circuit. The electrostatic protection circuit also has technical advantages of the semiconductor structure. It should be noted that, in the same or corresponding parts as those of the above embodiments, reference may be made to the corresponding descriptions of the above embodiments, and detailed descriptions thereof will be omitted.

The electrostatic protection circuit is applied to an integrated circuit.

In some embodiments, the electrostatic protection circuit comprises a semiconductor structure as described in the first aspect of the embodiments of the present disclosure. Wherein, the gate 21 is electrically connected to the source region 22.

In some examples, the gate 21, the source region 22 are electrically connected to the substrate 1 and grounded through the ground electrode 3.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples represent only a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure.

Claims (10)

1. A semiconductor structure, comprising:

the substrate is provided with a shallow groove isolation structure which is arranged in a ring shape, and an active area which is positioned in the ring of the shallow groove isolation structure;

a plurality of transistor units distributed in the active area side by side in the first direction; the transistor unit includes:

the grid electrode extends to the upper part of the shallow groove isolation structure along the second direction;

the source region and the drain region are respectively positioned in the active regions at two sides of the grid electrode and extend along the second direction;

a silicide blocking layer located at least between the drain region and the gate electrode;

wherein the second direction intersects the first direction; taking at least one transistor unit located in a first target area in the center of the active area as a first target unit, and taking at least one transistor unit located in a second target area at the edge of the active area as a second target unit; the width of the silicide blocking layer in the first target unit is larger than the width of the silicide layer in the second target unit, and the width of the silicide blocking layer is the dimension of the silicide blocking layer in the first direction.

2. The semiconductor structure of claim 1, wherein a reference cell is the transistor cell centered in the active region, the width of the silicide blocking layer in the reference cell being a maximum width;

among the plurality of transistor cells located on either side of the reference cell in the first direction, the width of the silicide blocking layer of each of the transistor cells gradually decreases in a direction away from the reference cell.

3. The semiconductor structure of claim 2 wherein a width of said silicide blocking layer of each of said transistor cells in a plurality of said transistor cells located on either side of said reference cell in said first direction is equi-valued in a direction away from said reference cell.

4. The semiconductor structure of claim 2, wherein any two adjacent transistor cells share the same source region; any two adjacent transistor units share the same drain region;

the number of the reference units is two, and the two reference units share the same drain region at the center of the active region and are symmetrically arranged by taking the drain region as a symmetry center.

5. The semiconductor structure of claim 4, wherein said silicide blocking layers in two of said transistor cells sharing a same said drain region are in communication at both ends of said drain region extending in said second direction so as to surround a peripheral side of said drain region.

6. The semiconductor structure of claim 1, wherein a distance from the drain region to the gate electrode along the first direction is greater than a distance from the source region to the gate electrode along the first direction.

7. The semiconductor structure of claim 1, further comprising:

the grounding electrode is annularly arranged at the outer side of the shallow slot isolation structure, which is away from the active area.

8. The semiconductor structure of any of claims 1-7, wherein the substrate has a first type well region, the shallow trench isolation structure and the active region being located within the first type well region; the source region and the drain region are respectively a second type doped region;

and the silicide blocking layer at least covers part of the surface of the drain region.

9. The semiconductor structure of claim 8, further comprising:

a source contact layer at least covering part of the surface of the source region;

and the drain contact layer is positioned on the surface of the drain region which is not covered by the silicide blocking layer.

10. An electrostatic protection circuit, applied to an integrated circuit, comprising the semiconductor structure of any one of claims 1-9; the grid electrode is electrically connected with the source region.