CN117723937A - Chip grouping test method and system - Google Patents
Chip grouping test method and system Download PDFInfo
- Publication number
- CN117723937A CN117723937A CN202311727851.1A CN202311727851A CN117723937A CN 117723937 A CN117723937 A CN 117723937A CN 202311727851 A CN202311727851 A CN 202311727851A CN 117723937 A CN117723937 A CN 117723937A
- Authority
- CN
- China
- Prior art keywords
- chip
- node
- sub
- peripheral
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010998 test method Methods 0.000 title description 13
- 238000004891 communication Methods 0.000 claims abstract description 235
- 230000002093 peripheral effect Effects 0.000 claims abstract description 147
- 238000012360 testing method Methods 0.000 claims abstract description 87
- 238000000034 method Methods 0.000 claims abstract description 41
- 230000004044 response Effects 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 10
- 238000010276 construction Methods 0.000 claims description 4
- 238000012795 verification Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Communication Control (AREA)
Abstract
The invention relates to the technical field of chip testing, and discloses a chip grouping testing method and a system, wherein the method comprises the following steps: selecting a main chip capable of performing normal chip communication from the chips by using a preset enumeration algorithm, and transmitting a first data communication protocol from the main chip to peripheral chips of the main chip so as to verify whether the peripheral chips can perform normal chip communication with the main chip through the first data communication protocol; after a second data communication protocol is sent from the primary sub-chip to the second peripheral chip, constructing a multi-stage sub-chip of the primary sub-chip by utilizing the second peripheral chip, and constructing an initial chip group of chips by utilizing the main chip, the primary sub-chip and the multi-stage sub-chip; judging whether a target chip capable of operating a normal chip exists in the sub-node subtrees; grouping the initial chip groups for first adjustment to obtain first adjustment groups; and grouping the initial chip groups for second adjustment to obtain second adjustment groups. The invention can have both speed and accuracy.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a method and a system for chip packet testing.
Background
The chip test before chip packaging can detect the chips with faults, and the workload of sequentially testing each chip is huge due to the large number of chips, so that the chips are subjected to grouping test in a chip divide-and-conquer mode in many chip test schemes at present, and the test times can be greatly reduced.
At present, the chip dividing and treating method comprises methods such as a two-by-two chip grouping method and a chip tree structure method, wherein the two-by-two chip grouping method is a process of detecting the B chip by the A chip and the A chip by the B chip, the workload of the method can only be reduced by half, the chip tree structure method is a method of realizing chip testing of subtrees under the root node by utilizing the root node chip, if no normal chip exists in the tree structure, the detection between father and child nodes and the detection between brother nodes in the tree structure can be invalid, because the A chip and the B chip are bad when the A chip and the B chip are mutually tested, the B chip feedback A chip is bad, and the feedback of which chip is not known, however, the normal chip before the tree structure is constructed is selected from a large number of chips by a method of sequentially testing the chips, the method is redundant before the tree structure is constructed, the efficiency is lower, and the existing chip grouping should be the chips in each grouping and the communication between the chips can be normally carried out, and the communication technology can not be considered. Therefore, the speed and accuracy of the existing chip grouping cannot be achieved.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and a system for testing chip grouping, which can combine speed and accuracy in chip grouping.
In a first aspect, the present invention provides a chip packet testing method, including:
selecting a main chip capable of performing normal chip communication from chips by using a preset enumeration algorithm, and transmitting a first data communication protocol from the main chip to peripheral chips of the main chip so as to verify whether the peripheral chips can perform normal chip communication with the main chip through the first data communication protocol;
when the peripheral chips can perform normal chip communication with the main chips, taking a first peripheral chip which can perform normal chip communication with the main chips in the peripheral chips as a first-stage sub-chip of the main chips, and selecting a second peripheral chip which cannot perform normal chip communication with the main chips from the peripheral chips;
after a second data communication protocol is sent from the primary sub-chip to the second peripheral chip, constructing a multi-stage sub-chip of the primary sub-chip by using the second peripheral chip based on the second data communication protocol, and constructing an initial chip group of the chips by using the main chip, the primary sub-chip and the multi-stage sub-chip;
Identifying an end child node in the initial chip group, determining a child node subtree of the end child node in the initial chip group, and judging whether a target chip capable of performing normal chip operation exists in the child node subtree;
when the target chip does not exist, grouping the initial chip group for first adjustment to obtain a first adjustment group, and completing a first chip group test of the chip by using the first adjustment group to obtain a first chip group test result;
and when the target chip exists, grouping the initial chip group for second adjustment to obtain a second adjustment group, and completing a second chip group test of the chip by using the second adjustment group to obtain a second chip group test result.
In a possible implementation manner of the first aspect, the preset enumeration algorithm includes:
identifying chip coordinates of the chip;
calculating the coordinate distance between every two chip coordinates in the chip coordinates by using the following formula:
wherein S is ij Representing the coordinate distance, x i 、y i Representing the ith chip coordinate, x, of the chip coordinates j 、y j Representing the jth chip coordinate in the chip coordinates;
Dividing the chips into groups when the coordinate distance is smaller than a preset distance;
extracting random chips from each of the chip clusters;
transmitting a data communication protocol for detecting a communication function of the random chip to the random chip;
and when the response communication protocol of the random chip is received within the preset timing time, the random chip is used as a main chip capable of carrying out normal chip communication.
In a possible implementation manner of the first aspect, the verifying, by the first data communication protocol, whether the peripheral chip may perform normal chip communication with the main chip includes:
when a first response communication protocol of the peripheral chip relative to the first data communication protocol is received from the main chip within a preset timing time, judging that the peripheral chip can perform normal chip communication with the main chip;
and when a first response communication protocol of the peripheral chip relative to the first data communication protocol is not received from the main chip within the preset timing time, judging that the peripheral chip can not perform normal chip communication with the main chip.
In a possible implementation manner of the first aspect, after the sending the second data communication protocol from the primary sub-chip to the second peripheral chip, the method further includes:
identifying the chip type of the primary sub-chip;
determining an applicable communication protocol of the primary sub-chip based on the chip type;
and respectively transmitting a plurality of applicable communication protocols in the applicable communication protocols from the primary sub-chip to the second peripheral chip so as to complete the process of transmitting a second data communication protocol from the primary sub-chip to the second peripheral chip.
In a possible implementation manner of the first aspect, the constructing, based on the second data communication protocol, a multi-level sub-chip of the one-level sub-chip with the second peripheral chip includes:
when a second response communication protocol of the second peripheral chip about the second data communication protocol is received in the primary sub-chip, the second peripheral chip which feeds back the second response communication protocol in the second peripheral chip is taken as a sub-chip of the primary sub-chip;
querying a second peripheral chip which does not feed back the second response communication protocol from the second peripheral chip;
Performing chip communication between the sub-chip and the second peripheral chip which does not feed back the second response communication protocol, so as to construct a sub-cluster of the sub-chip by using the second peripheral chip which does not feed back the second response communication protocol;
splicing the sub-chip and the sub-cluster to obtain a first multi-level sub-chip;
when a second response communication protocol of the second peripheral chip relative to the second data communication protocol is not received in the primary sub-chip, after chip communication between every two chips is carried out in the second peripheral chip, a chip cluster of the second peripheral chip is constructed;
and taking the chip cluster as a second multi-level sub-chip of the first-level sub-chip.
In a possible implementation manner of the first aspect, the constructing an initial chip group of the chips by using the main chip, the primary sub-chip and the multi-stage sub-chip includes:
taking the primary sub-chip as a root left sub-tree of the main chip;
selecting a first chip which can form a communication relation with the first-level sub-chip from the multi-level sub-chips;
constructing a first-level left sub-tree of the first-level sub-chip by using the first chip;
Selecting a second chip which cannot form a communication relation with the first-level sub-chip from the multi-level sub-chips;
constructing a first-level right sub-tree of the first-level sub-chip by using the first chip;
selecting a third chip which cannot form a communication relation with the main chip from the multi-level sub-chips;
constructing a root right sub-tree of the main chip by using the third chip;
an initial chip grouping of the chips is determined based on the root left subtree, the first level right subtree, and the root right subtree.
In one possible implementation manner of the first aspect, the determining whether a target chip capable of performing normal chip operation exists in the child node subtree includes:
identifying a last child node in the child node subtree;
starting from the last sub-node, traversing each node in the sub-node subtree by using a preset right-left middle traversing algorithm, and then determining a node testing sequence among each node in the sub-node subtree;
based on the node test sequence, detecting whether the nodes in the child node subtrees can perform normal chip operation or not;
when the node in the sub-node subtree can perform normal chip operation, determining that a target chip capable of performing normal chip operation exists in the sub-node subtree;
And when the node in the sub-node subtree can not perform normal chip operation, determining that a target chip capable of performing normal chip operation does not exist in the sub-node subtree.
In a possible implementation manner of the first aspect, the detecting, based on the node test order, whether a node in the child node subtree can perform normal chip operation includes:
dividing a master node and a slave node in the child node subtree;
analyzing a main operation result of the main node by using the slave node;
based on the main operation result, calculating a normal operation index of the main node by using the following formula:
wherein I is 1 Indicating the normal operation index of the master node, n u Representing a first main operation result in main operation results analyzed by a U-th slave node, wherein U represents the number of the main operation results which are the first main operation result, and m v Representing a second main operation result in the main operation results analyzed by the V-th slave node, wherein V represents the number of the second main operation results in the main operation results, and n u And m is equal to v The values of (2) are all 1;
when the normal operation index is not smaller than a preset index, judging that the main node can perform normal chip operation;
when the normal operation index is smaller than the preset index, judging that the main node can not perform normal chip operation;
The master node is used as a node intermediary for mutual testing between every two slave nodes in the sub-node subtrees;
and detecting whether the slave node can perform normal chip operation or not by using the node intermediaries based on the node testing sequence.
In a possible implementation manner of the first aspect, the grouping the initial chip group into a first adjustment group includes:
querying a first subtree root node in the subtree of the child node when the subtree of the child node belongs to the left subtree of the initial chip group;
inquiring whether a normal operation chip capable of performing normal chip operation exists in the first subtree root node and an upper left subtree where a father node of the first subtree root node is located;
judging whether the normal operation chip is a father node of the first subtree root node or not when the normal operation chip capable of performing normal chip operation exists in the upper left subtree where the first subtree root node and the father node of the first subtree root node are located;
when the normal operation chip is not a father node of the first subtree root node, the normal operation chip is used for replacing the father node of the first subtree root node to obtain a first replacement node, the left subtree of the father node of the first subtree root node is used as the left subtree of the first replacement node, and the father node of the first subtree root node is used as a first connection node for node connection between the first replacement node and the root node of the initial chip group;
The first alternative node, the left subtree of the first alternative node and the first connecting node are utilized to complete the first adjustment of the grouping of the initial chip grouping, and a first adjustment grouping is obtained;
when normal operation chips capable of performing normal chip operation do not exist in the upper-level left subtrees where the first subtree root node and the father node of the first subtree root node are located, traversing the initial chip groups layer by layer according to the sequence from the lower layer to the upper layer so as to complete first adjustment of the initial chip groups and obtain first adjustment groups.
In a second aspect, the present invention provides a chip packet testing system, the system comprising:
the communication verification module is used for selecting a main chip capable of performing normal chip communication from chips by using a preset enumeration algorithm, and sending a first data communication protocol from the main chip to peripheral chips of the main chip so as to verify whether the peripheral chips can perform normal chip communication with the main chip or not through the first data communication protocol;
the peripheral selecting module is used for taking a first peripheral chip which can be used for carrying out normal chip communication with the main chip in the peripheral chips as a first-stage sub-chip of the main chip when the peripheral chips can be used for carrying out normal chip communication with the main chip, and selecting a second peripheral chip which cannot be used for carrying out normal chip communication with the main chip from the peripheral chips;
The grouping construction module is used for constructing a multi-stage sub-chip of the primary sub-chip by using the second peripheral chip based on the second data communication protocol after the secondary data communication protocol is sent from the primary sub-chip to the second peripheral chip, and constructing an initial chip grouping of the chip by using the main chip, the primary sub-chip and the multi-stage sub-chip;
the target judging module is used for identifying the tail sub-node in the initial chip group, determining a sub-node subtree of the tail sub-node in the initial chip group, and judging whether a target chip capable of operating a normal chip exists in the sub-node subtree;
the first adjustment module is used for carrying out first adjustment on the initial chip group to obtain a first adjustment group when the target chip does not exist, and completing a first chip group test of the chip by using the first adjustment group to obtain a first chip group test result;
and the second adjustment module is used for grouping the initial chip groups for second adjustment when the target chip exists, so as to obtain second adjustment groups, and completing second chip grouping test of the chips by using the second adjustment groups, so as to obtain a second chip grouping test result.
Compared with the prior art, the technical principle and beneficial effect of this scheme lie in:
the embodiment of the invention selects the main chip capable of carrying out normal chip communication from the chips by utilizing the preset enumeration algorithm to realize chip communication between the main chip and other chips by utilizing the main chip, thereby converting a large number of chips which can pass through into a chip tree structure which can communicate with each other layer by layer, further, the embodiment of the invention verifies whether the peripheral chips can carry out normal chip communication with the main chip by utilizing the first data communication protocol to be used for establishing a communication relationship between the main chip and other chips, thus, when the chips are subjected to two-to-two mutual chip test, the chips can carry out data transmission, the embodiment of the invention can establish chip communication between the sub-chips and the second peripheral chips by utilizing the first data communication protocol when the main chip can not establish communication with the second peripheral chips, thus, the number of chips which do not participate in chip communication can be minimized, further, the embodiment of the invention can ensure that the chips can carry out data transmission between the chips by utilizing the second data communication protocol to establish the sub-chips by utilizing the second peripheral chips, and the sub-chips which are not in communication with the second peripheral chips, and the other peripheral chips are further established by utilizing the first peripheral chips, the method and the device are used for establishing initial chip clusters which can be communicated with each other and independent clusters which cannot be communicated with other clusters based on the communication relation between chips, and taking the clusters as groups, so that when chip testing is carried out later, mutual testing between every two chips can be realized based on the communication relation between chips only by sending chip testing data to root nodes in the clusters. Therefore, the chip grouping test method and system provided by the embodiment of the invention can achieve speed and accuracy in chip grouping.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a flow chart of a chip grouping test method according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a multi-level sub-chip of the chip group test method of FIG. 1 according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating initial chip grouping of the chip grouping test method of FIG. 1 according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first adjustment packet of the chip packet testing method of FIG. 1 according to an embodiment of the present invention;
fig. 5 is a schematic block diagram of a chip packet testing system according to an embodiment of the invention.
Detailed Description
It should be understood that the detailed description is presented by way of example only and is not intended to limit the invention.
The embodiment of the invention provides a chip grouping test method, and an execution body of the chip grouping test method comprises, but is not limited to, at least one of a server, a terminal and the like which can be configured to execute the method provided by the embodiment of the invention. In other words, the chip packet test method may be performed by software or hardware installed in a terminal device or a server device. The service end includes but is not limited to: microprocessors, system-on-chip chips, central processing, graphics processors, and the like.
Referring to fig. 1, a flow chart of a chip packet testing method according to an embodiment of the invention is shown. The chip grouping test method depicted in fig. 1 comprises the following steps:
s1, selecting a main chip capable of performing normal chip communication from chips by using a preset enumeration algorithm, and sending a first data communication protocol from the main chip to peripheral chips of the main chip so as to verify whether the peripheral chips can perform normal chip communication with the main chip through the first data communication protocol.
According to the embodiment of the invention, the main chip capable of carrying out normal chip communication is selected from the chips by utilizing the preset enumeration algorithm, so that the chip communication between the main chip and other chips is realized by utilizing the main chip, and a large number of chips which can pass through the main chip are converted into a chip tree structure which is communicated with each other layer by layer.
In an embodiment of the present invention, the preset enumeration algorithm includes: identifying chip coordinates of the chip; calculating the coordinate distance between every two chip coordinates in the chip coordinates by using the following formula:
wherein S is ij Representing the coordinate distance, x i 、y i Representing the ith chip coordinate, x, of the chip coordinates j 、y j Representing the jth chip coordinate in the chip coordinates;
dividing the chips into groups when the coordinate distance is smaller than a preset distance; extracting random chips from each of the chip clusters; transmitting a data communication protocol for detecting a communication function of the random chip to the random chip; and when the response communication protocol of the random chip is received within the preset timing time, the random chip is used as a main chip capable of carrying out normal chip communication.
It should be noted that the number of the main chips is only one.
The data communication protocol and the response communication protocol belong to the same type of communication protocol, and it should be noted that the data communication protocol includes a plurality of different types of data communication protocols, because different types of chips have different communication modes, and no matter what type of data communication protocol, when the communication between the main chip and other chips can be realized, the response communication protocol is only consistent with the data communication protocol that can realize the communication between the main chip and other chips.
Optionally, the process of transmitting the data communication protocol for detecting the communication function of the random chip to the random chip is: a plurality of different types of data communication protocols are transmitted to the random chip because a single data communication protocol is transmitted, and the opposite chip does not necessarily respond.
Further, the embodiment of the invention verifies whether the peripheral chips can perform normal chip communication with the main chip through the first data communication protocol, so as to be used for establishing the communication relationship between the main chip and other chips, and therefore, the data transmission between the chips can be ensured when the chip-to-chip mutual chip test is performed subsequently.
Wherein the peripheral chips refer to all chips except the main chip, and further, the first data communication protocol is consistent with the data communication protocol, that is, the first data communication protocol includes a plurality of different types of data communication protocols.
In an embodiment of the present invention, the verifying, by the first data communication protocol, whether the peripheral chip can perform normal chip communication with the main chip includes: when a first response communication protocol of the peripheral chip relative to the first data communication protocol is received from the main chip within a preset timing time, judging that the peripheral chip can perform normal chip communication with the main chip; and when a first response communication protocol of the peripheral chip relative to the first data communication protocol is not received from the main chip within the preset timing time, judging that the peripheral chip can not perform normal chip communication with the main chip.
S2, when the peripheral chips can perform normal chip communication with the main chips, taking a first peripheral chip which can perform normal chip communication with the main chips in the peripheral chips as a primary sub-chip of the main chips, and selecting a second peripheral chip which cannot perform normal chip communication with the main chips from the peripheral chips.
S3, after the second data communication protocol is sent from the primary sub-chip to the second peripheral chip, constructing a multi-stage sub-chip of the primary sub-chip by using the second peripheral chip based on the second data communication protocol, and constructing an initial chip group of the chips by using the main chip, the primary sub-chip and the multi-stage sub-chip.
According to the embodiment of the invention, the second data communication protocol is sent from the primary sub-chip to the second peripheral chip, so that when the main chip cannot establish communication with the second peripheral chip, the chip communication between the primary sub-chip and the second peripheral chip is established, and the number of chips which do not participate in the chip communication can be minimized.
In an embodiment of the present invention, after the sending the second data communication protocol from the primary sub-chip to the second peripheral chip, the method further includes: identifying the chip type of the primary sub-chip; determining an applicable communication protocol of the primary sub-chip based on the chip type; and respectively transmitting a plurality of applicable communication protocols in the applicable communication protocols from the primary sub-chip to the second peripheral chip so as to complete the process of transmitting a second data communication protocol from the primary sub-chip to the second peripheral chip.
It should be noted that the applicable communication protocol and the second data communication protocol are consistent with the data communication protocol described above.
Further, the embodiment of the invention constructs the multi-level sub-chip of the primary sub-chip by utilizing the second peripheral chip based on the second data communication protocol, so as to be used for continuing to construct the communication relationship between chips in the rest chips which do not establish communication when the primary sub-chip establishes communication with part of the chips in the second peripheral chip.
The multi-level sub-chip refers to a chip with a cluster structure of father-son relationship, which is obtained by converting the communication relationship between the second peripheral chip and the level-one sub-chip.
In an embodiment of the present invention, the constructing the multi-level sub-chip of the one-level sub-chip using the second peripheral chip based on the second data communication protocol includes: when a second response communication protocol of the second peripheral chip about the second data communication protocol is received in the primary sub-chip, the second peripheral chip which feeds back the second response communication protocol in the second peripheral chip is taken as a sub-chip of the primary sub-chip; querying a second peripheral chip which does not feed back the second response communication protocol from the second peripheral chip; performing chip communication between the sub-chip and the second peripheral chip which does not feed back the second response communication protocol, so as to construct a sub-cluster of the sub-chip by using the second peripheral chip which does not feed back the second response communication protocol; splicing the sub-chip and the sub-cluster to obtain a first multi-level sub-chip; when a second response communication protocol of the second peripheral chip relative to the second data communication protocol is not received in the primary sub-chip, after chip communication between every two chips is carried out in the second peripheral chip, a chip cluster of the second peripheral chip is constructed; and taking the chip cluster as a second multi-level sub-chip of the first-level sub-chip.
It should be noted that, after the sub-clusters and the chip clusters are all provided with separate clusters which are not connected with other clusters, the chip capable of establishing a communication relationship with the sub-chip and the chip incapable of establishing a communication relationship with the sub-chip in the second peripheral chip without feedback of the second response communication protocol can be determined after the sub-chip communicates with the second peripheral chip without feedback of the second response communication protocol, the chip capable of establishing a communication relationship with the sub-chip is used as the next-stage chip of the sub-chip, the chip incapable of establishing a communication relationship with the sub-chip is used as the separate cluster, the chip capable of establishing a communication relationship with the sub-chip is used as the next-stage chip of the sub-chip, the chip capable of communicating with the second peripheral chip is continuously selected according to the principle of performing the chip communication between the sub-chip and the second peripheral chip without feedback of the second response communication protocol, the chip is constructed as the next-stage of the sub-chip and the second peripheral chip with the last chip, the chip is constructed as the sub-cluster, the two chips can be mutually communicated with each other chip with each other after the two peripheral chips are further mutually different from each other, the largest difference between the sub-clusters and the chip clusters is that: the root node of the sub-cluster is a sub-chip, all the sub-chips can communicate with the primary sub-chip, and all the root nodes of the chip cluster cannot communicate with the primary sub-chip.
Referring to fig. 2, a schematic diagram of a multi-level sub-chip of the chip grouping test method provided in fig. 1 according to an embodiment of the invention is shown. In fig. 2, 1 denotes a primary sub-chip, 2 denotes a sub-chip, 3 denotes a chip which can communicate with 2 in a second peripheral chip which does not feed back the second response communication protocol, 4 denotes a chip which cannot communicate with 2 in a second peripheral chip which does not feed back the second response communication protocol, and 5 denotes the chip cluster.
Further, the embodiment of the invention constructs the initial chip grouping of the chips by utilizing the main chip, the primary sub-chip and the multi-stage sub-chip, so as to be used for establishing initial chip clusters which can be mutually communicated and independent clusters which can not be communicated with other clusters based on the communication relationship between the chips, and takes the clusters as the grouping, thus, when the chip test is carried out subsequently, the mutual test between every two chips can be realized based on the communication relationship between the chips by only sending the chip test data to the root node in the clusters.
In an embodiment of the present invention, the constructing the initial chip group of the chips by using the main chip, the primary sub-chip and the multi-stage sub-chip includes: taking the primary sub-chip as a root left sub-tree of the main chip; selecting a first chip which can form a communication relation with the first-level sub-chip from the multi-level sub-chips; constructing a first-level left sub-tree of the first-level sub-chip by using the first chip; selecting a second chip which cannot form a communication relation with the first-level sub-chip from the multi-level sub-chips; constructing a first-level right sub-tree of the first-level sub-chip by using the first chip; selecting a third chip which cannot form a communication relation with the main chip from the multi-level sub-chips; constructing a root right sub-tree of the main chip by using the third chip; an initial chip grouping of the chips is determined based on the root left subtree, the first level right subtree, and the root right subtree.
It should be noted that, the first-level left subtree includes the aforementioned sub-chip, the first-level right subtree includes the aforementioned sub-cluster, and the root right subtree includes the aforementioned chip cluster.
Referring to fig. 3, a schematic diagram of an initial chip grouping of the chip grouping test method provided in fig. 1 according to an embodiment of the invention is shown. In fig. 3, 6 denotes a main chip, 7 denotes a root left subtree, 8 denotes a first-level left subtree, 9 denotes a first-level right subtree, and 10 denotes a root right subtree.
S4, identifying an end sub-node in the initial chip group, determining a sub-node subtree of the end sub-node in the initial chip group, and judging whether a target chip capable of operating a normal chip exists in the sub-node subtree.
The embodiment of the invention judges whether the target chip capable of operating the normal chip exists in the sub-tree of the child nodes, so as to ensure that each sub-tree or cluster in the initial chip group has the normal chip, and therefore, when the mutual detection of every two chips is carried out, the mutual detection reliability of every two chips can be judged according to the detection result of the correct one chip.
Wherein, the last child node refers to the last child node of the last layer in the initial chip packet.
In an embodiment of the present invention, the determining whether a target chip capable of performing normal chip operation exists in the child node subtree includes: identifying a last child node in the child node subtree; starting from the last sub-node, traversing each node in the sub-node subtree by using a preset right-left middle traversing algorithm, and then determining a node testing sequence among each node in the sub-node subtree; based on the node test sequence, detecting whether the nodes in the child node subtrees can perform normal chip operation or not; when the node in the sub-node subtree can perform normal chip operation, determining that a target chip capable of performing normal chip operation exists in the sub-node subtree; and when the node in the sub-node subtree can not perform normal chip operation, determining that a target chip capable of performing normal chip operation does not exist in the sub-node subtree.
The preset right-left middle traversing algorithm is an algorithm for traversing right nodes, traversing left nodes and traversing root nodes.
In yet another embodiment of the present invention, the detecting whether the node in the child node subtree can perform normal chip operation based on the node test sequence includes: dividing a master node and a slave node in the child node subtree; analyzing a main operation result of the main node by using the slave node; based on the main operation result, calculating a normal operation index of the main node by using the following formula:
Wherein I is 1 Indicating the normal operation index of the master node, n u Representing a first main operation result in main operation results analyzed by a U-th slave node, wherein U represents the number of the main operation results which are the first main operation result, and m v Representing a second main operation result in the main operation results analyzed by the V-th slave node, wherein V represents the number of the second main operation results in the main operation results, and n u And m is equal to v The values of (2) are all 1;
when the normal operation index is not smaller than a preset index, judging that the main node can perform normal chip operation; when the normal operation index is smaller than the preset index, judging that the main node can not perform normal chip operation; the master node is used as a node intermediary for mutual testing between every two slave nodes in the sub-node subtrees; and detecting whether the slave node can perform normal chip operation or not by using the node intermediaries based on the node testing sequence.
The relationship between the master node and the slave node is a relationship between a father node and a child node, further, the first master operation result is a good result, that is, the slave chip feeds back that the master chip is normal, the second master operation result is a bad result, that is, the slave chip feeds back that the master chip is abnormal, further, the preset index is 0, that is, when the total number of the first master operation result is consistent with the total number of the second master operation result or the former is greater than the latter, it is determined that the master node can perform normal chip operation.
In an exemplary embodiment, the process of detecting whether the slave node can perform normal chip operation by using the node intermediary based on the node test sequence is that when detecting the normal state of the slave node 1, the slave node 1 is detected by sending detection information from the master node, and mutual detection between the remaining other slave nodes and the slave node 1 is implemented by using the communicable relationship between the remaining other slave nodes and the master node, so that a plurality of normal or abnormal analysis results of the slave node 1 can be obtained.
S5, when the target chip does not exist, grouping the initial chip group for first adjustment to obtain a first adjustment group, and completing a first chip group test of the chip by using the first adjustment group to obtain a first chip group test result.
The embodiment of the invention reduces the large-scale adjustment amount from the upper layer to the lower layer in a mode of adjusting the sub-nodes to the upper layer of the tree structure step by grouping the initial chip groups for the first adjustment to ensure that each cluster has a root node in a normal running state.
In an embodiment of the present invention, the grouping the initial chip group to obtain a first adjustment group includes: querying a first subtree root node in the subtree of the child node when the subtree of the child node belongs to the left subtree of the initial chip group; inquiring whether a normal operation chip capable of performing normal chip operation exists in the first subtree root node and an upper left subtree where a father node of the first subtree root node is located; judging whether the normal operation chip is a father node of the first subtree root node or not when the normal operation chip capable of performing normal chip operation exists in the upper left subtree where the first subtree root node and the father node of the first subtree root node are located; when the normal operation chip is not a father node of the first subtree root node, the normal operation chip is used for replacing the father node of the first subtree root node to obtain a first replacement node, the left subtree of the father node of the first subtree root node is used as the left subtree of the first replacement node, and the father node of the first subtree root node is used as a first connection node for node connection between the first replacement node and the root node of the initial chip group; the first alternative node, the left subtree of the first alternative node and the first connecting node are utilized to complete the first adjustment of the grouping of the initial chip grouping, and a first adjustment grouping is obtained; when normal operation chips capable of performing normal chip operation do not exist in the upper-level left subtrees where the first subtree root node and the father node of the first subtree root node are located, traversing the initial chip groups layer by layer according to the sequence from the lower layer to the upper layer so as to complete first adjustment of the initial chip groups and obtain first adjustment groups.
It should be noted that, when the normal running chip is the parent node of the first subtree root node, the first adjustment of grouping is not performed on the initial chip grouping, further, when the normal running chip is substituted for the parent node of the first subtree root node, the child node of the normal running chip continues to follow the normal running chip, further, the left subtree refers to a subtree that can normally communicate, so that in the initial chip grouping, the left subtree can communicate with each other, and the right subtree is a cluster that cannot communicate with each other, that is, a sibling cluster is between clusters that cannot communicate with each other, and the sibling cluster is converted into a right subtree of the tree structure, thereby realizing that all chip clusters are connected into a tree structure, and the left subtree also exists under the right subtree.
Fig. 4 is a schematic diagram of a first adjustment packet of the chip packet testing method provided in fig. 1 according to an embodiment of the invention. In fig. 4, 15 denotes an end child node, 13 denotes a first subtree root node among the subtree of child nodes, 14 denotes a normal operation chip when the normal operation chip is not a parent node of the first subtree root node, 12 denotes a parent node of the first subtree root node, 11 denotes a parent node of 12, 16 denotes an upper left subtree, and 17 denotes a left subtree of the parent node of the first subtree root node.
It should be noted that, the process of completing the first chip grouping test of the chip by using the first adjustment grouping to obtain the first chip grouping test result includes: after the first adjustment group is obtained, the data needed to perform chip test on the chip is sent to the root node of the first adjustment group, and then the root node can utilize the communication relation with the lower node to realize communication with the left subtree and chip test on the left subtree, for example, the main chip A and the left subtree B mutually test and feedback whether the opposite chip is normal or not, and further, with respect to the right subtree of the first adjustment group, the chip test data needs to be sent to the right subtree independently.
And S6, when the target chip exists, grouping the initial chip groups for second adjustment to obtain second adjustment groups, and completing second chip grouping test of the chips by using the second adjustment groups to obtain second chip grouping test results.
In an embodiment of the present invention, the grouping the initial chip group to obtain a second adjustment group includes: when the target chip is not a father node in the subtree of the child node, the target chip is substituted for the father node in the subtree of the child node, so as to obtain a second substituted node; taking the child node subtree as a left subtree of the second alternative node; a father node in the child node subtree is used as a second connection node for node connection between the second substitution node and the root node of the initial chip group; and finishing grouping second adjustment on the initial chip grouping by using the second alternative node, the left subtree of the second alternative node and the second connection node to obtain a second adjustment grouping.
It should be noted that, the principle of using the second adjustment packet to complete the second chip packet test of the chip to obtain the second chip packet test result is similar to the principle of using the first adjustment packet to complete the first chip packet test of the chip to obtain the first chip packet test result, and further description is omitted herein.
It can be seen that, in the embodiment of the present invention, by selecting a master chip capable of performing normal chip communication from chips by using a preset enumeration algorithm, the master chip is used to implement chip communication between the master chip and other chips, so that a large number of chips that can pass through are converted into a chip tree structure capable of performing layer-by-layer communication with each other, further, the first data communication protocol is used to verify whether the peripheral chips can perform normal chip communication with the master chip, so as to be used to establish a communication relationship between the master chip and other chips, so that when two chips are tested with each other, data can be transmitted between chips in a subsequent chip-to-chip mutual test, in the embodiment of the present invention, by sending a second data communication protocol from the primary sub-chip to the second peripheral chip, so that when the master chip cannot establish communication with the second peripheral chip, chip communication between the primary sub-chip and the second peripheral chip can be minimized, further, the embodiment of the present invention can further establish a chip communication relationship between the primary sub-chip and the second peripheral chip by using the second data communication protocol, and the primary sub-chip is further constructed by using the first sub-chip and the primary sub-chip, when the primary chip communication is further established with the primary chip, the method and the device are used for establishing initial chip clusters which can be communicated with each other and independent clusters which cannot be communicated with other clusters based on the communication relation between chips, and taking the clusters as groups, so that when chip testing is carried out later, mutual testing between every two chips can be realized based on the communication relation between chips only by sending chip testing data to root nodes in the clusters. Therefore, the chip grouping test method provided by the embodiment of the invention can achieve speed and accuracy in chip grouping.
FIG. 5 is a functional block diagram of a chip packet test system according to the present invention.
The chip packet test system 500 of the present invention may be installed in an electronic device. Depending on the implemented functions, the chip packet test system may include a communication verification module 501, a peripheral selection module 502, a packet construction module 503, a target discrimination module 504, a first adjustment module 505, and a second adjustment module 506. The module of the invention, which may also be referred to as a unit, refers to a series of computer program segments, which are stored in the memory of the electronic device, capable of being executed by the processor of the electronic device and of performing a fixed function.
In the embodiment of the present invention, the functions of each module/unit are as follows:
the communication verification module 501 is configured to select a master chip capable of performing normal chip communication from chips by using a preset enumeration algorithm, and send a first data communication protocol from the master chip to peripheral chips of the master chip, so as to verify whether the peripheral chips can perform normal chip communication with the master chip through the first data communication protocol;
the peripheral selecting module 502 is configured to, when the peripheral chip can perform normal chip communication with the main chip, use a first peripheral chip that can perform normal chip communication with the main chip in the peripheral chip as a first-stage sub-chip of the main chip, and select a second peripheral chip that cannot perform normal chip communication with the main chip from the peripheral chips;
The packet construction module 503 is configured to construct, based on the second data communication protocol, a multi-level sub-chip of the first level sub-chip using the second peripheral chip, and construct an initial chip packet of the chip using the main chip, the first level sub-chip, and the multi-level sub-chip after sending the second data communication protocol from the first level sub-chip to the second peripheral chip;
the target judging module 504 is configured to identify an end child node in the initial chip group, determine a child node subtree where the end child node is located in the initial chip group, and judge whether a target chip capable of performing normal chip operation exists in the child node subtree;
the first adjustment module 505 is configured to perform a first adjustment on the initial chip packet to obtain a first adjustment packet when the target chip does not exist, and complete a first chip packet test of the chip by using the first adjustment packet to obtain a first chip packet test result;
and the second adjustment module 506 is configured to perform a second adjustment on the initial chip group to obtain a second adjustment group when the target chip exists, and complete a second chip group test of the chip by using the second adjustment group to obtain a second chip group test result.
In detail, the modules in the chip packet testing system 500 in the embodiment of the present invention use the same technical means as the chip packet testing method described in fig. 1 and can produce the same technical effects, which are not described herein.
In addition, each functional module in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units can be realized in a form of hardware or a form of hardware and a form of software functional modules.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for chip packet testing, the method comprising:
selecting a main chip capable of performing normal chip communication from chips by using a preset enumeration algorithm, and transmitting a first data communication protocol from the main chip to peripheral chips of the main chip so as to verify whether the peripheral chips can perform normal chip communication with the main chip through the first data communication protocol;
when the peripheral chips can perform normal chip communication with the main chips, taking a first peripheral chip which can perform normal chip communication with the main chips in the peripheral chips as a first-stage sub-chip of the main chips, and selecting a second peripheral chip which cannot perform normal chip communication with the main chips from the peripheral chips;
after a second data communication protocol is sent from the primary sub-chip to the second peripheral chip, constructing a multi-stage sub-chip of the primary sub-chip by using the second peripheral chip based on the second data communication protocol, and constructing an initial chip group of the chips by using the main chip, the primary sub-chip and the multi-stage sub-chip;
Identifying an end child node in the initial chip group, determining a child node subtree of the end child node in the initial chip group, and judging whether a target chip capable of performing normal chip operation exists in the child node subtree;
when the target chip does not exist, grouping the initial chip group for first adjustment to obtain a first adjustment group, and completing a first chip group test of the chip by using the first adjustment group to obtain a first chip group test result;
and when the target chip exists, grouping the initial chip group for second adjustment to obtain a second adjustment group, and completing a second chip group test of the chip by using the second adjustment group to obtain a second chip group test result.
2. The method of claim 1, wherein the pre-set enumeration algorithm comprises:
identifying chip coordinates of the chip;
calculating the coordinate distance between every two chip coordinates in the chip coordinates by using the following formula:
wherein S is ij Representing the coordinate distance, x i 、y i Representing the ith chip coordinate, x, of the chip coordinates j 、y j Representing the jth chip coordinate in the chip coordinates;
Dividing the chips into groups when the coordinate distance is smaller than a preset distance;
extracting random chips from each of the chip clusters;
transmitting a data communication protocol for detecting a communication function of the random chip to the random chip;
and when the response communication protocol of the random chip is received within the preset timing time, the random chip is used as a main chip capable of carrying out normal chip communication.
3. The method of claim 1, wherein verifying, via the first data communication protocol, whether the peripheral chip can communicate with the master chip normally comprises:
when a first response communication protocol of the peripheral chip relative to the first data communication protocol is received from the main chip within a preset timing time, judging that the peripheral chip can perform normal chip communication with the main chip;
and when a first response communication protocol of the peripheral chip relative to the first data communication protocol is not received from the main chip within the preset timing time, judging that the peripheral chip can not perform normal chip communication with the main chip.
4. The method of claim 1, wherein after the sending the second data communication protocol from the primary sub-chip to the second peripheral chip, further comprising:
identifying the chip type of the primary sub-chip;
determining an applicable communication protocol of the primary sub-chip based on the chip type;
and respectively transmitting a plurality of applicable communication protocols in the applicable communication protocols from the primary sub-chip to the second peripheral chip so as to complete the process of transmitting a second data communication protocol from the primary sub-chip to the second peripheral chip.
5. The method of claim 1, wherein the constructing the multi-level sub-chip of the one-level sub-chip with the second peripheral chip based on the second data communication protocol comprises:
when a second response communication protocol of the second peripheral chip about the second data communication protocol is received in the primary sub-chip, the second peripheral chip which feeds back the second response communication protocol in the second peripheral chip is taken as a sub-chip of the primary sub-chip;
querying a second peripheral chip which does not feed back the second response communication protocol from the second peripheral chip;
Performing chip communication between the sub-chip and the second peripheral chip which does not feed back the second response communication protocol, so as to construct a sub-cluster of the sub-chip by using the second peripheral chip which does not feed back the second response communication protocol;
splicing the sub-chip and the sub-cluster to obtain a first multi-level sub-chip;
when a second response communication protocol of the second peripheral chip relative to the second data communication protocol is not received in the primary sub-chip, after chip communication between every two chips is carried out in the second peripheral chip, a chip cluster of the second peripheral chip is constructed;
and taking the chip cluster as a second multi-level sub-chip of the first-level sub-chip.
6. The method of claim 1, wherein constructing an initial chip group of the chips using the master chip, the primary sub-chip, and the multi-stage sub-chip comprises:
taking the primary sub-chip as a root left sub-tree of the main chip;
selecting a first chip which can form a communication relation with the first-level sub-chip from the multi-level sub-chips;
constructing a first-level left sub-tree of the first-level sub-chip by using the first chip;
Selecting a second chip which cannot form a communication relation with the first-level sub-chip from the multi-level sub-chips;
constructing a first-level right sub-tree of the first-level sub-chip by using the first chip;
selecting a third chip which cannot form a communication relation with the main chip from the multi-level sub-chips;
constructing a root right sub-tree of the main chip by using the third chip;
an initial chip grouping of the chips is determined based on the root left subtree, the first level right subtree, and the root right subtree.
7. The method of claim 1, wherein the determining whether the target chip capable of normal chip operation exists in the sub-node subtree comprises:
identifying a last child node in the child node subtree;
starting from the last sub-node, traversing each node in the sub-node subtree by using a preset right-left middle traversing algorithm, and then determining a node testing sequence among each node in the sub-node subtree;
based on the node test sequence, detecting whether the nodes in the child node subtrees can perform normal chip operation or not;
when the node in the sub-node subtree can perform normal chip operation, determining that a target chip capable of performing normal chip operation exists in the sub-node subtree;
And when the node in the sub-node subtree can not perform normal chip operation, determining that a target chip capable of performing normal chip operation does not exist in the sub-node subtree.
8. The method of claim 7, wherein the detecting whether the node in the child node subtree is capable of normal chip operation based on the node test order comprises:
dividing a master node and a slave node in the child node subtree;
analyzing a main operation result of the main node by using the slave node;
based on the main operation result, calculating a normal operation index of the main node by using the following formula:
wherein I is 1 Indicating the normal operation index of the master node, n u Representing a first main operation result in the main operation results analyzed by the U-th slave node, wherein U represents the main operation resultIn is the number of the first main operation results, m v Representing a second main operation result in the main operation results analyzed by the V-th slave node, wherein V represents the number of the second main operation results in the main operation results, and n u And m is equal to v The values of (2) are all 1;
when the normal operation index is not smaller than a preset index, judging that the main node can perform normal chip operation;
When the normal operation index is smaller than the preset index, judging that the main node can not perform normal chip operation;
the master node is used as a node intermediary for mutual testing between every two slave nodes in the sub-node subtrees;
and detecting whether the slave node can perform normal chip operation or not by using the node intermediaries based on the node testing sequence.
9. The method of claim 1, wherein grouping the initial chip group into a first adjustment group comprises:
querying a first subtree root node in the subtree of the child node when the subtree of the child node belongs to the left subtree of the initial chip group;
inquiring whether a normal operation chip capable of performing normal chip operation exists in the first subtree root node and an upper left subtree where a father node of the first subtree root node is located;
judging whether the normal operation chip is a father node of the first subtree root node or not when the normal operation chip capable of performing normal chip operation exists in the upper left subtree where the first subtree root node and the father node of the first subtree root node are located;
When the normal operation chip is not a father node of the first subtree root node, the normal operation chip is used for replacing the father node of the first subtree root node to obtain a first replacement node, the left subtree of the father node of the first subtree root node is used as the left subtree of the first replacement node, and the father node of the first subtree root node is used as a first connection node for node connection between the first replacement node and the root node of the initial chip group;
the first alternative node, the left subtree of the first alternative node and the first connecting node are utilized to complete the first adjustment of the grouping of the initial chip grouping, and a first adjustment grouping is obtained;
when normal operation chips capable of performing normal chip operation do not exist in the upper-level left subtrees where the first subtree root node and the father node of the first subtree root node are located, traversing the initial chip groups layer by layer according to the sequence from the lower layer to the upper layer so as to complete first adjustment of the initial chip groups and obtain first adjustment groups.
10. A chip packet testing system, the system comprising:
The communication verification module is used for selecting a main chip capable of performing normal chip communication from chips by using a preset enumeration algorithm, and sending a first data communication protocol from the main chip to peripheral chips of the main chip so as to verify whether the peripheral chips can perform normal chip communication with the main chip or not through the first data communication protocol;
the peripheral selecting module is used for taking a first peripheral chip which can be used for carrying out normal chip communication with the main chip in the peripheral chips as a first-stage sub-chip of the main chip when the peripheral chips can be used for carrying out normal chip communication with the main chip, and selecting a second peripheral chip which cannot be used for carrying out normal chip communication with the main chip from the peripheral chips;
the grouping construction module is used for constructing a multi-stage sub-chip of the primary sub-chip by using the second peripheral chip based on the second data communication protocol after the secondary data communication protocol is sent from the primary sub-chip to the second peripheral chip, and constructing an initial chip grouping of the chip by using the main chip, the primary sub-chip and the multi-stage sub-chip;
The target judging module is used for identifying the tail sub-node in the initial chip group, determining a sub-node subtree of the tail sub-node in the initial chip group, and judging whether a target chip capable of operating a normal chip exists in the sub-node subtree;
the first adjustment module is used for carrying out first adjustment on the initial chip group to obtain a first adjustment group when the target chip does not exist, and completing a first chip group test of the chip by using the first adjustment group to obtain a first chip group test result;
and the second adjustment module is used for grouping the initial chip groups for second adjustment when the target chip exists, so as to obtain second adjustment groups, and completing second chip grouping test of the chips by using the second adjustment groups, so as to obtain a second chip grouping test result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311727851.1A CN117723937A (en) | 2023-12-15 | 2023-12-15 | Chip grouping test method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311727851.1A CN117723937A (en) | 2023-12-15 | 2023-12-15 | Chip grouping test method and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117723937A true CN117723937A (en) | 2024-03-19 |
Family
ID=90204718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311727851.1A Pending CN117723937A (en) | 2023-12-15 | 2023-12-15 | Chip grouping test method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117723937A (en) |
-
2023
- 2023-12-15 CN CN202311727851.1A patent/CN117723937A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101542402A (en) | Methods and apparatus providing advanced classification for power over ethernet | |
| CN108092854B (en) | Test method and device for train-level Ethernet equipment based on IEC61375 protocol | |
| CN103138988B (en) | Positioning treatment method and positioning treatment device of network faults | |
| CN108776616A (en) | A kind of method, block chain node and the system of determining block chain node trusted status | |
| CN106646186B (en) | Batch test method and system for chips | |
| US20180124048A1 (en) | Data transmission method, authentication method, and server | |
| CN112367191B (en) | Service fault positioning method under 5G network slice | |
| US9240940B2 (en) | Scalable infiniband interconnect performance and diagnostic tool | |
| CN103186440B (en) | Detect subcard method, apparatus and system in place | |
| CN102694692A (en) | Fault detecting method and device of distributed equipment | |
| CN102664755B (en) | Control channel fault determining method and device | |
| CN115022022A (en) | Method for improving Raft consensus mechanism based on node past behavior analysis | |
| CN111865745A (en) | Non-delay polling method and system for automatically identifying slave equipment | |
| CN108512675B (en) | Network diagnosis method and device, control node and network node | |
| CN117723937A (en) | Chip grouping test method and system | |
| US20130325203A1 (en) | Methods and systems for monitoring a vehicle for faults | |
| CN115658078A (en) | Database pre-compiling processing method, device, equipment and medium | |
| CN114610544A (en) | Artificial intelligence big data analysis processing system and method based on block chain | |
| CN107103134A (en) | Low-speed wireless sensor network testability analysis method based on Bayesian network | |
| CN114448834A (en) | Multiprocessor network fault node diagnosis method based on folding hypercube | |
| CN106649352A (en) | Data processing method and apparatus | |
| CN111367838A (en) | Method and device for detecting data storage system and data storage system | |
| CN112765925B (en) | Interconnected circuit system, verification system and method | |
| RU2801825C2 (en) | Method, complex for processing information about failures of devices of wireless sensor networks for data transmission and related networks | |
| CN117172758B (en) | Cloud edge fusion-based drug production line equipment fault detection method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240524 Address after: 201203 3rd floor, building 19, building 8, No. 498, GuoShouJing Road, Pudong New Area pilot Free Trade Zone, Shanghai Applicant after: Shanghai Xinzhong Youshu Technology Co.,Ltd. Country or region after: China Address before: Room 505, Building 1, No. 560 Shengxia Road, Pudong New Area, Shanghai, October 2012 Applicant before: Chuangshengxin Semiconductor (Shanghai) Co.,Ltd. Country or region before: China |