CN117715469A - Display panel - Google Patents
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- CN117715469A CN117715469A CN202311862057.8A CN202311862057A CN117715469A CN 117715469 A CN117715469 A CN 117715469A CN 202311862057 A CN202311862057 A CN 202311862057A CN 117715469 A CN117715469 A CN 117715469A
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Abstract
The embodiment of the invention discloses a display panel, which comprises a driving circuit layer and a plurality of light emitting devices, wherein the driving circuit layer comprises a first power line at least partially positioned in a display area; the light emitting device is arranged on the driving circuit layer and is arranged in the display area, the first power line is electrically connected with the second electrode, namely, a parallel structure is formed between the first power line and the second electrode of the light emitting device in the display area, and the parallel structure of the first power line and the second electrode of the light emitting device has smaller resistance relative to the second electrode of the light emitting device, so that voltage drop is reduced during power signal transmission. The first power line is in a grid shape, so that the resistance of the first power line is smaller, correspondingly, the voltage drop when the power signal is transmitted to the second electrode of the light-emitting device through the first power line is reduced, the voltage difference of the power signal received by the second electrode of the light-emitting device at different positions is reduced, the display uniformity of the display panel can be improved, and the picture display quality is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel.
Background
With the development of display technology, the requirements of users on the display quality of pictures are also increasing.
The uniformity of brightness of the display screen is an important factor affecting the display quality of the screen, and in the related art, there is a problem that the uniformity of brightness of the display screen is poor, resulting in lower display quality of the screen.
Disclosure of Invention
The invention provides a display panel, which is used for improving the brightness uniformity of the display panel and improving the display quality.
The embodiment of the invention provides a display panel, which comprises a display area and further comprises:
the driving circuit layer comprises a first power line, a second power line and a plurality of pixel circuits, wherein the first power line is at least partially positioned in the display area, the second power line is at least partially positioned in the display area and is electrically connected with the pixel circuits, and the driving current generated by the pixel circuits is related to the voltage transmitted by the second power line;
the light-emitting devices are located on the driving circuit layer and arranged in the display area, and each light-emitting device comprises a first electrode, a light-emitting layer and a second electrode which are arranged in a stacked mode, wherein a first power line is electrically connected with the second electrode, and the first power line is in a grid shape.
Optionally, the first power line includes a first sub power line and a second sub power line, and the first sub power line and the second sub power line are electrically connected; at least part of the first sub power line extends along a first direction, at least part of the second sub power line extends along a second direction, and the first direction and the second direction are intersected; the driving circuit layer comprises a plurality of metal layers which are laminated on one side of the substrate; wherein the first sub-power line and the second sub-power line are located in different metal layers;
Optionally, the driving circuit layer at least includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked from one side of the substrate; one of the first sub power line and the second sub power line is positioned on the third metal layer, and the other is positioned on the fourth metal layer;
optionally, each first sub-power line is correspondingly connected with a plurality of first power line connecting parts, the first power line connecting parts are located on the third metal layer, orthographic projection of the first power line connecting parts on the substrate of the display panel is overlapped with the second sub-power lines, and the second sub-power lines are connected with the first power line connecting parts through via holes;
optionally, an output terminal of the pixel circuit is electrically connected to the first electrode of the at least one light emitting device, and the pixel circuit includes at least two thin film transistors and at least one capacitor; the grid electrode of the thin film transistor is positioned on the first metal layer, one polar plate of the capacitor is positioned on the first metal layer, the other polar plate of the capacitor is positioned on the second metal layer, and the source electrode and the drain electrode of the thin film transistor are positioned on the third metal layer;
optionally, the materials of the metal layers where the first sub power line and the second sub power line are located are titanium-aluminum-titanium;
optionally, the material of the second metal layer is molybdenum.
Optionally, the second power line is in a grid shape;
optionally, the second power line includes a third sub power line and a fourth sub power line, at least part of the third sub power line extends along the first direction, at least part of the fourth sub power line extends along the second direction, the third sub power line and the fourth sub power line are electrically connected, and the third sub power line and the fourth sub power line are located in different metal layers;
optionally, one of the third sub-power line and the fourth sub-power line is located in the third metal layer, and the other is located in the fourth metal layer;
optionally, each third sub-power line is correspondingly connected with a plurality of second power line connecting parts, the second power line connecting parts are located on the third metal layer, orthographic projection of the second power line connecting parts on the substrate of the display panel is overlapped with the fourth sub-power line, and the fourth sub-power line is connected with the second power line connecting parts through the through holes;
optionally, the pixel circuits are arranged in an array, the row direction of the pixel circuit arrangement is a first direction, the column direction of the pixel circuit arrangement is a second direction, and one polar plate of the capacitor in the pixel circuit in the same row is connected with each other and is connected to the third sub power line or the fourth sub power line;
optionally, the materials of the metal layers where the third sub-power line and the fourth sub-power line are located are titanium-aluminum-titanium.
Optionally, the pixel circuit includes a driving transistor, a first initializing transistor for initializing a gate of the driving transistor, and a second initializing transistor for initializing a first electrode of the light emitting device; the display panel further comprises a first initialization line and a second initialization line, wherein the first initialization line is electrically connected with the first initialization transistor, and the second initialization line is electrically connected with the second initialization transistor; the first initialization line is in a grid shape and/or the second initialization line is in a grid shape;
optionally, the first initializing line includes a first sub-initializing line and a second sub-initializing line, the first sub-initializing line extends along a first direction, the second sub-initializing line extends along a second direction, the first sub-initializing line and the second sub-initializing line are electrically connected, and the first sub-initializing line and the second sub-initializing line are located in different metal layers;
optionally, the first sub-initialization line is located in the second metal layer;
optionally, the second sub-initializing line and the second sub-power line are located on the same metal layer;
optionally, the second initializing line includes a third sub-initializing line and a fourth sub-initializing line, the third sub-initializing line extends along the first direction, the fourth sub-initializing line extends along the second direction, the third sub-initializing line and the fourth sub-initializing line are electrically connected, and the third sub-initializing line and the fourth sub-initializing line are located in different metal layers;
Optionally, the third sub-initialization line is located in the second metal layer;
optionally, the fourth sub-initializing line and the second sub-power line are located on the same metal layer.
Optionally, the display panel further includes a plurality of column units, the column units include a first column unit and a second column unit, the first column unit and the second column unit include two columns of pixel circuits, and the first column unit and the second column unit are alternately arranged;
each first column unit is correspondingly connected with a second sub-initialization line and a fourth sub-initialization line; each second column unit is correspondingly provided with two second sub power lines;
optionally, the relative position of one of the second sub power lines connected to the second column unit in the second column unit is the same as the relative position of the second sub initialization line connected to the first column unit in the first column unit; the relative position of the other second sub-power line connected with the second column unit in the second column unit is the same as the relative position of the fourth sub-initialization line connected with the first column unit in the first column unit.
Optionally, in the first column unit and the second column unit, the first initializing transistor and the second initializing transistor in one pixel circuit are arranged in mirror image with the first initializing transistor and the second initializing transistor in the other pixel circuit in the two pixel circuits in the same row;
Optionally, the first initializing transistor and the second initializing transistor in one pixel circuit are arranged in a mirror image manner, and the first initializing transistor and the second initializing transistor in the other pixel circuit are arranged between the two first initializing transistors;
optionally, in the first column unit, a fourth sub-initialization line is located between the two columns of pixel circuits;
optionally, in the first column unit, the second sub-initialization line is located at one side of the two columns of pixel circuits.
Optionally, the first sub-initialization lines and the third sub-initialization lines are alternately arranged along the second direction;
each first sub-initialization line is correspondingly connected with a plurality of first initialization connecting parts, the first initialization connecting parts are positioned on the third metal layer, and the first initialization connecting parts are also positioned on two first initialization transistors in the same row;
optionally, the first initializing connection portion connects two first initializing transistors in the pixel circuits located in the same row in the adjacent first column unit and the second column initializing unit;
optionally, the orthographic projection of the first initializing connection portion on the substrate overlaps with the second sub-initializing line or the second sub-power line, the first initializing connection portion is electrically connected with the second sub-initializing line through the via hole, and the first initializing connection portion is insulated from the second sub-power line.
Optionally, the first sub-initialization lines and the third sub-initialization lines are alternately arranged along the second direction;
each third sub-initialization line is correspondingly connected with a plurality of second initialization connecting parts, the second initialization connecting parts are positioned on the third metal layer, and the second initialization connecting parts are also connected with second initialization transistors positioned in two pixel circuits of the same row;
optionally, the second initializing connection portion connects two second initializing transistors in the pixel circuits located in the same row in the adjacent first column units;
optionally, the orthographic projection of the second initialization connection part on the substrate overlaps with the fourth sub-initialization line or the second sub-power line, and the second initialization connection part is electrically connected with the fourth sub-initialization line through the via hole; the second initialization connection part is arranged in an insulating way with the second sub power line.
Optionally, the display panel further includes a plurality of first scan lines and second scan lines, and the first scan lines are electrically connected to the first initializing transistor and the second initializing transistor; the pixel circuit further includes a data writing transistor writing a data signal to a gate of the driving transistor according to a signal on the second scanning line;
the first scanning line is positioned between the first sub-initialization line and the third sub-initialization line along the second direction, and the second scanning line is positioned at one side of the third sub-initialization line far away from the first sub-initialization line;
The first sub power line is positioned at one side of the first sub initialization line far away from the third sub initialization line;
the first initialization connecting part and the second initialization connecting part are positioned between the first sub power line and the second scanning line along the second direction;
optionally, the connection via hole between the first initialization connection part and the second sub-initialization line, the connection via hole between the second initialization connection part and the fourth sub-initialization line, and the connection via hole between the first power line connection part and the second sub-power line are located between the first sub-initialization line and the adjacent third sub-initialization line; the connecting lines of the first initializing connecting part and the second initializing line, the connecting via of the second initializing connecting part and the fourth initializing line, and the connecting via of the first power line connecting part and the second initializing line are straight lines extending along the first direction.
Optionally, the driving circuit layer further includes a data line, and the metal layer where the data line is located is on one side of the metal layer where the first power line is located, which is close to the light emitting device;
optionally, each column of pixel circuits is correspondingly connected with two data lines, and the pixel circuits in the odd rows and the pixel circuits in the even rows are connected with different data lines.
The display panel comprises a driving circuit layer and a plurality of light emitting devices, wherein the driving circuit layer comprises a first power line at least partially positioned in a display area; the light emitting device is arranged on the driving circuit layer and is arranged in the display area, the first power line is electrically connected with the second electrode, namely, a parallel structure is formed between the first power line and the second electrode of the light emitting device in the display area, and the parallel structure of the first power line and the second electrode of the light emitting device has smaller resistance relative to the second electrode of the light emitting device, so that voltage drop is reduced during power signal transmission. The first power line is in a grid shape, so that the resistance of the first power line is smaller, correspondingly, the voltage drop when the power signal is transmitted to the second electrode of the light-emitting device through the first power line is reduced, the voltage difference of the power signal received by the second electrode of the light-emitting device at different positions is reduced, the display uniformity of the display panel can be improved, and the picture display quality is improved.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a top view of a first power line in a display panel according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a pixel circuit in the related art;
FIG. 5 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic view of the structure of the active layer and the first metal layer of FIG. 5;
FIG. 7 is a schematic view of the structure of the second metal layer and the third metal layer in FIG. 5;
fig. 8 is a schematic structural view of the third metal layer and the fourth metal layer in fig. 5.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
In the related art, there is a problem that uniformity of brightness of a display screen is poor, resulting in lower quality of the display screen. The inventors have found that the above problem arises because the display panel includes a pixel circuit and a light emitting device, and the pixel circuit can drive the light emitting device to emit light. The display panel further includes a power line electrically connected to the pixel circuit or the light emitting device. The resistance of the power line is larger, so that the voltage drop is larger when the power line transmits power signals, and the power signals received by the pixel circuits or the light emitting devices at different positions in the display panel are different, so that the uniformity of the brightness of a display picture is poor, and the display quality of the picture is lower.
For the foregoing reasons, an embodiment of the present invention provides a display panel, fig. 1 is a schematic structural diagram of the display panel provided by the embodiment of the present invention, fig. 2 is a top view of a first power line in the display panel provided by the embodiment of the present invention, and referring to fig. 1 and 2, the display panel includes a display area, and the display panel further includes: the driving circuit layer 100, the driving circuit layer 100 includes a first power line VSS, a second power line VDD and a plurality of pixel circuits 10, the first power line VSS is at least partially located in the display area, the second power line VDD is at least partially located in the display area and electrically connected to the pixel circuits 10, and a driving current generated by the pixel circuits 10 is related to a voltage transmitted by the second power line VDD; the light emitting devices 200 are disposed on the driving circuit layer 100 and in the display region, the light emitting devices 200 include a first electrode 210, a light emitting layer 220, and a second electrode 230 stacked together, the first power line VSS is electrically connected to the second electrode 230, and the first power line VSS is in a grid shape.
The display panel may include a display area and a non-display area. In the display region, the driving circuit layer 100 may include a plurality of pixel circuits 10, and the pixel circuits 10 may include at least two thin film transistors. The driving current generated by the pixel circuit 10 is related to the voltage transmitted by the second power line VDD, alternatively, the driving current generated by the pixel circuit 10 is positively related to the voltage transmitted by the second power line VDD. In the non-display region, the driving circuit layer 100 may include a bezel circuit, which may be a gate driving circuit including a gate electrode supplying a driving signal to a gate electrode of a thin film transistor in the pixel circuit.
In this embodiment, the light emitting device 200 includes a first electrode 210, a light emitting layer 220, and a second electrode 230 sequentially stacked on the driving circuit layer 100, wherein the first electrode 210 may be an anode of the light emitting device 200 and the second electrode 230 may be a cathode of the light emitting device 200. The first electrode 210, i.e., the anode, is a reflective electrode, i.e., an opaque electrode, and the anode may have a three-layer structure, wherein the first layer and the third layer may be metal oxide layers, such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), aluminum Zinc Oxide (AZO), and the second layer in between may be a metal layer (such as silver or copper). The cathode may be an ITO transparent electrode or a magnesium silver alloy. The light emitting layer 220 may include only a single film layer, i.e., only a light emitting material layer; a multi-layered structure formed of a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, an electron injection layer, and the like, which are stacked from the first electrode 210 to the second electrode 230, may also be included. Optionally, the light emitting layer 220 includes at least a red light emitting layer, a green light emitting layer, and a blue light emitting layer, so that a display with multiple colors can be realized.
In the related art, a power line connected to the second electrode 230 of the light emitting device 200 is not provided in the display area, the second electrode 230 of the light emitting device 200 is of an entire structure, the entire second electrode 230 is connected to the power line in the non-display area, and in the display area, a power signal is transmitted only through the entire second electrode 230, and the second electrode 230 is thinner in thickness and larger in resistance, so that a transmission voltage drop is large, and power signals received by the second electrode 230 at the light emitting device 200 at different positions are greatly different, thereby affecting display uniformity. In this embodiment, the driving circuit layer 100 further includes a first power line VSS located in the display area, where the first power line VSS is electrically connected to the second electrode 230 of the light emitting device 200, and the first power line VSS may be electrically connected to the second electrode 230 in the display area, or may be electrically connected to the second electrode 230 of the light emitting device 200 in the non-display area, that is, in the display area, the first power line VSS and the second electrode 230 of the light emitting device 200 form a parallel structure, and the parallel structure of the first power line VSS and the second electrode 230 of the light emitting device 200 has a smaller resistance compared to the second electrode 230 of the light emitting device 200, so that a voltage drop during power signal transmission is reduced. The second electrodes 230 of the light emitting devices 200 in this embodiment may be connected to each other to form a whole structure, or may be in a mutually independent block structure, or may divide the display area into different sub-display areas, and the second electrodes 230 of the light emitting devices 200 in the same sub-display area are electrically connected, and the second electrodes 230 of the light emitting devices 200 in different sub-display areas are mutually insulated. The first power line VSS is in a grid shape, so that the resistance of the first power line VSS is smaller, and accordingly, the voltage drop when the power signal is transmitted to the second electrode 230 of the light emitting device 200 through the first power line VSS is reduced, so that the voltage difference of the power signals received by the second electrodes 230 of the light emitting devices 200 at different positions is reduced, and further, the display uniformity of the display panel can be improved, and the display quality of the picture is improved.
The display panel of the embodiment comprises a driving circuit layer and a plurality of light emitting devices, wherein the driving circuit layer comprises a first power line at least partially positioned in a display area; the light emitting device is arranged on the driving circuit layer and is arranged in the display area, the first power line is electrically connected with the second electrode, namely, a parallel structure is formed between the first power line and the second electrode of the light emitting device in the display area, and the parallel structure of the first power line and the second electrode of the light emitting device has smaller resistance relative to the second electrode of the light emitting device, so that voltage drop is reduced during power signal transmission. The first power line is in a grid shape, so that the resistance of the first power line is smaller, correspondingly, the voltage drop when the power signal is transmitted to the second electrode of the light-emitting device through the first power line is reduced, the voltage difference of the power signal received by the second electrode of the light-emitting device at different positions is reduced, the display uniformity of the display panel can be improved, and the picture display quality is improved. In addition, the resistance of the first power line is smaller, so that the power consumption of the screen body can be reduced.
Fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 3, optionally, the first power line VSS includes a first sub power line VSS1 and a second sub power line VSS2, where the first sub power line VSS1 and the second sub power line VSS2 are electrically connected; at least a portion of the first sub power line VSS1 extends in a first direction x1, at least a portion of the second sub power line VSS2 extends in a second direction y1, and the first direction x1 and the second direction y1 intersect; the driving circuit layer 100 includes a plurality of metal layers stacked on one side of a substrate; wherein the first sub power line VSS1 and the second sub power line VSS2 are located in different metal layers.
Specifically, in this embodiment, the first power line VSS includes a first sub power line VSS1 and a second sub power line VSS2, where the first sub power line VSS1 and the second sub power line VSS2 are located in different metal layers and can be connected through a via. At least part of the first sub power line VSS1 extends along the first direction x1, at least part of the second sub power line VSS2 extends along the second direction y1, and the first sub power line VSS1 and the second sub power line VSS2 are connected to each other to form a grid-shaped first power line VSS, so that the impedance of the first power line VSS is ensured to be smaller.
In an alternative embodiment of the present invention, the first sub power line VSS1 extends along the first direction x1, and the second sub power line VSS2 extends along the second direction y 1. In another alternative embodiment of the present invention, the extending direction of the whole first sub power line VSS1 is the first direction x1, but may include a first bending portion 300, where the first bending portion 300 may extend along a direction different from the first direction x1, and the arrangement of the first bending portion 300 may avoid the conductive structure of the same metal layer but transmitting different electrical signals, so as to avoid the short circuit between the first sub power line VSS1 and the conductive structure of the same metal layer transmitting other electrical signals, and ensure the reliability of the display panel. In another alternative embodiment of the present invention, the extending direction of the whole second sub power line VSS2 is the second direction y1, but may include a second bending portion (not shown in fig. 3), and the effect of the second bending portion is similar to that of the first bending portion 300, which is not described herein again.
With continued reference to fig. 3, on the basis of the above technical solution, optionally, the driving circuit layer 100 includes at least a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 that are sequentially stacked from one side of the substrate; one of the first and second sub power lines VSS1 and VSS2 is located in the third metal layer M3, and the other is located in the fourth metal layer M4.
The driving circuit layer 100 further includes an active layer PS1, which may be disposed between at least one metal layer and the substrate. Optionally, the driving circuit layer 100 further includes a plurality of pixel circuits, wherein an output terminal of the pixel circuit is electrically connected to the first electrode 210 of the at least one light emitting device 200, and the pixel circuit includes at least two thin film transistors and at least one capacitor; the grid electrode of the thin film transistor is positioned on the first metal layer M1, one polar plate of the capacitor is positioned on the first metal layer M1, the other polar plate of the capacitor is positioned on the second metal layer M2, and the source electrode and the drain electrode of the thin film transistor are positioned on the third metal layer M3. Because the pixel circuits provided by the first metal layer M1 and the second metal layer M2 have more constituent structures, one of the first sub-power line VSS1 and the second sub-power line VSS2 is provided in the third metal layer M3, and the other is provided in the fourth metal layer M4, so that the wiring difficulty of the first sub-power line VSS1 and the second sub-power line VSS2 is lower.
On the basis of the above technical solution, optionally, the materials of the metal layers where the first sub power line VSS1 and the second sub power line VSS2 are located are titanium-aluminum-titanium; accordingly, one of the first sub-power line VSS1 and the second sub-power line VSS2 is located in the third metal layer M3, and when the other is located in the fourth metal layer M4, the metal of the third metal layer M3 and the fourth metal layer M4 is titanium-aluminum-titanium. The resistance of the titanium-aluminum-titanium material is smaller, the materials of the first sub power line VSS1 and the second sub power line VSS2 are titanium-aluminum-titanium, so that the resistance of the first power line VSS can be further reduced, the transmission voltage drop of a power signal on the first power line VSS is further reduced, and the display uniformity is further improved. Optionally, the material of the second metal layer M2 is molybdenum, and the resistance of molybdenum is greater than that of titanium-aluminum-titanium, so that compared with the case that the first sub-power line VSS1 or the second sub-power line VSS2 is disposed on the second metal layer M2, the case that the first sub-power line VSS1 or the second sub-power line VSS2 is disposed on the third metal layer M3 or the fourth metal layer M4 can make the resistance of the first sub-power line VSS1 or the second sub-power line VSS2 smaller, and reduce the transmission voltage drop of the power signal on the first power line VSS.
On the basis of the above technical solution, optionally, each first sub power line VSS1 is correspondingly connected to a plurality of first power line connection parts, the first power line connection parts are located in the third metal layer M3, the orthographic projection of the first power line connection parts on the substrate of the display panel overlaps with the second sub power line VSS2, and the second sub power line VSS2 is connected to the first power line connection parts through vias; through setting up first power cord connecting portion in display panel, every first sub-power cord VSS1 is connected with second sub-power cord VSS2 electricity through a plurality of first power cord connecting portions, through setting up the different shapes and the size of first power cord connecting portion, can adjust the position of the connection via hole of first sub-power cord VSS1 and second sub-power cord VSS2 in a flexible way, guarantee that the connection of first sub-power cord VSS1 and second sub-power cord VSS2 can not influence the setting of other conductive structures in the display panel.
Fig. 4 is a schematic structural diagram of a pixel circuit in the related art, with continued reference to fig. 3 and fig. 4, and based on the above technical solutions, optionally, the driving circuit layer 100 further includes a second power line VDD, where the second power line VDD is electrically connected to the pixel circuit, and a driving current generated by the pixel circuit is related to a voltage transmitted by the second power line VDD; for the driving circuit shown in fig. 4, the driving current i=k (Vdd-Vdata) generated by the pixel circuit 2 Where k is a constant, vdd represents the voltage transmitted by the second power line Vdd, and Vdata represents the Data voltage transmitted by the Data line Data.
Optionally, the second power line VDD is in a grid shape; through setting up latticed second power cord VDD structure, can make the resistance of second power cord VDD less, and then can make the voltage drop when second power cord VDD transmits voltage signal can reduce, because the drive current that the pixel circuit produced is correlated with the voltage that second power cord VDD transmitted, the voltage drop of second power cord VDD transmitted voltage signal reduces, can make the voltage difference that the pixel circuit in different positions received the second power cord VDD transmission in display panel reduce, and then make the difference that the pixel circuit produced drive current in different positions reduce, be favorable to further promoting the display homogeneity, promote the picture display quality.
Optionally, the second power line VDD includes a third sub power line VDD1 and a fourth sub power line VDD2, at least a portion of the third sub power line VDD1 extends along the first direction x1, at least a portion of the fourth sub power line VDD2 extends along the second direction y1, the third sub power line VDD1 and the fourth sub power line VDD2 are electrically connected, and the third sub power line VDD1 and the fourth sub power line VDD2 are located at different metal layers.
Specifically, in this embodiment, the second power line VDD includes a third sub power line VDD1 and a fourth sub power line VDD2, where the third sub power line VDD1 and the fourth sub power line VDD2 are located in different metal layers, and may be connected through a via. At least part of the third sub power line VDD1 extends along the first direction x1, at least part of the fourth sub power line VDD2 extends along the second direction y1, and the third sub power line VDD1 and the fourth sub power line VDD2 are connected to each other to form a grid-shaped second power line VDD, so that the impedance of the second power line VDD is ensured to be smaller. In an alternative embodiment of the present invention, the third sub power line VDD1 extends along the first direction x1, and the fourth sub power line VDD2 extends along the second direction y1. In another alternative embodiment of the present invention, the extending direction of the third sub power line VDD1 is the first direction x1. In yet another alternative embodiment of the present invention, the extending direction of the fourth sub power line VDD2 as a whole is the second direction y1.
On the basis of the above technical solution, optionally, one of the third sub power line VDD1 and the fourth sub power line VDD2 is located in the third metal layer M3, and the other is located in the fourth metal layer M4.
As described in the above embodiment, since the first metal layer M1 and the second metal layer M2 are more in the composition structure of the pixel circuit, one of the third sub-power line VDD1 and the fourth sub-power line VDD2 is disposed on the third metal layer M3, and the other is disposed on the fourth metal layer M4, so that the wiring difficulty of the third sub-power line VDD1 and the fourth sub-power line VDD2 is lower.
Optionally, the materials of the metal layers where the third sub power line VDD1 and the fourth sub power line VDD2 are located are titanium-aluminum-titanium. Accordingly, when one of the third sub-power line VDD1 and the fourth sub-power line VDD2 is located in the third metal layer M3 and the other is located in the fourth metal layer M4, the metal of the third metal layer M3 and the fourth metal layer M4 is titanium-aluminum-titanium. The resistance of the titanium-aluminum-titanium material is smaller, the materials of the third sub power line VDD1 and the fourth sub power line VDD2 are titanium-aluminum-titanium, so that the resistance of the first power line VSS can be further reduced, the transmission voltage drop of the power signal on the first power line VSS is further reduced, and the display uniformity is further improved.
Optionally, each third sub power line VDD1 is correspondingly connected to a plurality of second power line connection parts, the second power line connection parts are located in the third metal layer M3, orthographic projection of the second power line connection parts on the substrate of the display panel overlaps with the fourth sub power line VDD2, and the fourth sub power line VDD2 is connected with the second power line connection parts through via holes; through setting up second power cord connecting portion in display panel, every third sub-power cord VDD1 is connected with fourth sub-power cord VDD2 electricity through a plurality of second power cord connecting portions, through setting up the different shapes and the size of second power cord connecting portion, can adjust the position of the connection via hole of third sub-power cord VDD1 and fourth sub-power cord VDD2 in a flexible way, guarantee that the connection of third sub-power cord VDD1 and fourth sub-power cord VDD2 can not influence the setting of other conductive structures in the display panel.
Optionally, the pixel circuits are arranged in an array, the row direction of the pixel circuit arrangement is a first direction x1, the column direction of the pixel circuit arrangement is a second direction y1, and one polar plate of the capacitor in the pixel circuit of the same row is connected with each other and is connected to a third sub power line VDD1 or a fourth sub power line VDD2; by the arrangement, the voltage drop of the transmission voltage of the second power line VDD can be smaller, and display uniformity is further improved.
Fig. 5 is a schematic structural view of another display panel according to an embodiment of the present invention, fig. 6 is a schematic structural view of the active layer and the first metal layer in fig. 5, fig. 7 is a schematic structural view of the second metal layer and the third metal layer in fig. 5, fig. 8 is a schematic structural view of the third metal layer and the fourth metal layer in fig. 5, and with continued reference to fig. 4-8, the pixel circuit includes a driving transistor T1, a first initializing transistor T4 and a second initializing transistor T7, where the first initializing transistor T4 is used for initializing the gate electrode of the driving transistor T1, and the second initializing transistor T7 is used for initializing the first electrode 210 of the light emitting device 200; the display panel further comprises a first initialization line Vref1 and a second initialization line Vref2, the first initialization line Vref1 is electrically connected with the first initialization transistor T4, and the second initialization line Vref2 is electrically connected with the second initialization transistor T7; the first initialization line Vref1 is in a grid shape and/or the second initialization line Vref2 is in a grid shape.
The first initializing line Vref1 is in a grid structure, so that the resistance of the first initializing line Vref1 is smaller, the transmission voltage drop is smaller when the first initializing line Vref1 transmits the first initializing voltage, the difference of the first initializing voltages received by pixel circuits at different positions in the display panel is smaller, and accordingly, the difference of the first initializing voltages received by the grid electrodes of the driving transistors T1 of the pixel circuits at different positions is smaller, the grid electrodes of the driving transistors T1 of the pixel circuits at different positions are consistent in initializing degree, and further improvement of the picture display quality is facilitated.
Similarly, the second initializing line Vref2 is in a grid structure, so that the resistance of the second initializing line Vref2 is smaller, and further, the transmission voltage drop is smaller when the second initializing line Vref2 transmits the second initializing voltage, so that the difference of the second initializing voltages received by the pixel circuits at different positions in the display panel is ensured to be smaller, and accordingly, the difference of the second initializing voltages received by the first electrodes 210 of the light emitting devices 200 of the pixel circuits at different positions is smaller, so that the initialized degree of the first electrodes 210 of the light emitting devices 200 connected with the pixel circuits at different positions is consistent, which is favorable for further improving the picture display quality.
On the basis of the above technical solution, optionally, the first initializing line Vref1 includes a first sub-initializing line Vref11 and a second sub-initializing line Vref12, the first sub-initializing line Vref11 extends along the first direction x1, the second sub-initializing line Vref12 extends along the second direction y1, the first sub-initializing line Vref11 and the second sub-initializing line Vref12 are electrically connected, and the first sub-initializing line Vref11 and the second sub-initializing line Vref12 are located in different metal layers.
Specifically, in this embodiment, the first initializing line Vref1 includes a first sub-initializing line Vref11 and a second sub-initializing line Vref12, where the first sub-initializing line Vref11 and the second sub-initializing line Vref12 are located in different metal layers, and can be connected through a via. At least part of the first sub-initialization line Vref11 extends along the first direction x1, at least part of the second sub-initialization line Vref12 extends along the second direction y1, the first sub-initialization line Vref11 and the second sub-initialization line Vref12 are connected with each other to form a grid-shaped first initialization line Vref1, and the impedance of the first initialization line Vref1 is ensured to be smaller. In an alternative embodiment of the present invention, the first sub-initialization line Vref11 extends along the first direction x1 and the second sub-initialization line Vref12 extends along the second direction y1. In another alternative embodiment of the present invention, the extending direction of the whole first sub-initialization line Vref11 is the first direction x1. In yet another alternative embodiment of the present invention, the extending direction of the second sub-initialization line Vref12 as a whole is the second direction y1.
Optionally, the first sub-initialization line Vref11 is located in the second metal layer M2; because the second metal layer M2 has fewer signal lines, the first sub-initialization line Vref11 is disposed in the second metal layer M2, so that the wiring density of other metal layers can be reduced, and the wiring density in each metal layer is relatively uniform.
Optionally, the second sub-initialization line Vref12 and the second sub-power line VSS2 are located in the same metal layer. Specifically, the extending directions of the second sub-initializing line Vref12 and the second sub-power line VSS2 are the same, so that the second sub-initializing line Vref12 and the second sub-power line VSS2 are disposed on the same metal layer, so that the second sub-initializing line Vref12 and the second sub-power line VSS2 are not connected, and insulation of the second sub-initializing line Vref12 and the second sub-power line VSS2 is easier to realize.
On the basis of the above technical solution, optionally, the second initializing line Vref2 includes a third sub-initializing line Vref21 and a fourth sub-initializing line Vref22, the third sub-initializing line Vref21 extends along the first direction x1, the fourth sub-initializing line Vref22 extends along the second direction y1, the third sub-initializing line Vref21 and the fourth sub-initializing line Vref22 are electrically connected, and the third sub-initializing line Vref21 and the fourth sub-initializing line Vref22 are located in different metal layers.
Specifically, in this embodiment, the setting of the second initializing line Vref2 includes a third sub-initializing line Vref21 and a fourth sub-initializing line Vref22, where the third sub-initializing line Vref21 and the fourth sub-initializing line Vref22 are located in different metal layers, and can be connected by a via. At least part of the third sub-initialization line Vref21 extends along the first direction x1, at least part of the fourth sub-initialization line Vref22 extends along the second direction y1, the third sub-initialization line Vref21 and the fourth sub-initialization line Vref22 are connected with each other to form a second initialization line Vref2 in a grid shape, and the impedance of the second initialization line Vref2 is ensured to be smaller. In an alternative embodiment of the present invention, the third sub-initialization line Vref21 extends along the first direction x1, and the fourth sub-initialization line Vref22 extends along the second direction y1. In another alternative embodiment of the present invention, the extending direction of the third sub-initialization line Vref21 is the first direction x1. In yet another alternative embodiment of the present invention, the extending direction of the fourth sub-initialization line Vref22 as a whole is the second direction y1.
Optionally, the third sub-initialization line Vref21 is located in the second metal layer M2; since the second metal layer M2 has fewer signal lines, the third sub-initialization line Vref21 is disposed in the second metal layer M2, so that the wiring density of other metal layers can be reduced, and the wiring density in each metal layer is uniform.
Optionally, the fourth sub-initialization line Vref22 and the second sub-power line VSS2 are located in the same metal layer. Specifically, the extending direction of the fourth sub-initializing line Vref22 is the same as that of the second sub-power line VSS2, so that the fourth sub-initializing line Vref22 and the second sub-power line VSS2 are disposed in the same metal layer, so that the fourth sub-initializing line Vref22 and the second sub-power line VSS2 are not connected, and insulation of the fourth sub-initializing line Vref22 and the second sub-power line VSS2 is easier to realize.
Fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 5, optionally, the display panel further includes a plurality of column units 400, the column units 400 include a first column unit 410 and a second column unit 420, the first column unit 410 and the second column unit 420 each include two columns of pixel circuits, and the first column unit 410 and the second column unit 420 are alternately arranged; each first column unit 410 is correspondingly connected with a second sub-initialization line Vref12 and a fourth sub-initialization line Vref22; two second sub power lines VSS2 are disposed in each of the second column units 420.
Specifically, since the second sub-initialization line Vref12, the fourth sub-initialization line Vref22 and the second sub-power line VSS2 are located in the same metal layer, and the first power line VSS, the first initialization line Vref1 and the second initialization line Vref2 are all in a grid structure, the density of the second sub-power line VSS2 can be properly reduced, two second sub-power lines VSS2 can be correspondingly arranged in the second column unit 420, and the first column unit 410 is correspondingly connected to one second sub-initialization line Vref12 and one fourth sub-initialization line Vref22. The first column subunits and the second column subunits are alternately arranged, so that the setting density of the second sub-initialization line Vref12, the fourth sub-initialization line Vref22 and the second sub-power line VSS2 is uniform, and the voltage drop is uniform when signals are transmitted, thereby being beneficial to further improving the display uniformity.
Based on the above technical solution, optionally, the relative position of one of the second sub power lines VSS2 connected to the second column unit 420 in the second column unit 420 is the same as the relative position of the second sub initialization line Vref12 connected to the first column unit 410 in the first column unit 410; the relative position of the other second sub power line VSS2 connected to the second column unit 420 in the second column unit 420 is the same as the relative position of the fourth sub initialization line Vref22 connected to the first column unit 410 in the first column unit 410.
With continued reference to fig. 5 to 8, in the above technical solution, optionally, in the first column unit 410 and the second column unit 420, the first initializing transistor T4 and the second initializing transistor T7 in one pixel circuit are mirror-arranged with the first initializing transistor T4 and the second initializing transistor T7 in the other pixel circuit, which are located in two pixel circuits in the same row; therefore, on one hand, layout space can be saved, and pixel density can be improved; on the other hand, the overlapping area of the conducting structure connected with the first initializing transistor T4 and the data line can be reduced, and the overlapping area of the conducting structure connected with the second initializing transistor T7 and the data line can be reduced, so that the load on the data line is reduced, and the display quality is improved.
Optionally, the first initializing transistor T4 and the second initializing transistor T7 in one pixel circuit are arranged in a mirror image manner, and the first initializing transistor T4 and the second initializing transistor T7 in the other pixel circuit are arranged between the two first initializing transistors T4; by the arrangement, two second initializing transistors T7 can be connected through one fourth sub-initializing line Vref22, the number of the fourth sub-initializing lines Vref22 is reduced, and the wiring density is reduced.
On the basis of the above technical solution, optionally, in the first column unit 410, the fourth sub-initialization line Vref22 is located between two columns of pixel circuits; by doing so, the connection of the fourth sub-initialization line Vref22 to the two second initialization transistors T7 can be made more convenient.
Alternatively, in the first column unit 410, the second sub-initialization line Vref12 is located at one side of the two columns of pixel circuits, and illustratively, as shown in fig. 5, the second sub-initialization line Vref12 is located at the right side of the two columns of pixel circuits.
With continued reference to fig. 3 and 5, on the basis of the above technical solution, the first sub-initialization lines Vref11 and the third sub-initialization lines Vref21 are alternately arranged along the second direction y 1; each first sub-initializing line Vref11 is correspondingly connected to a plurality of first initializing connection sections 510, the first initializing connection sections 510 are located in the third metal layer M3, and the first initializing connection sections 510 are also located in two first initializing transistors T4 in the same row; the first initializing connection portion 510 may be configured to connect the first sub-initializing line Vref11 to the first initializing transistor T4 in the pixel circuit.
Optionally, the first initializing connection portion 510 connects two first initializing transistors T4 in the pixel circuits located in the same row in the adjacent first column unit 410 and second column initializing unit; in the column unit 400, the first initializing transistor T4 and the second initializing transistor T7 in one pixel circuit are arranged in a mirror image manner, and the first initializing transistor T4 and the second initializing transistor T7 in the other pixel circuit are located between the two first initializing transistors T4, so that the first initializing transistors T4 in the first column unit 410 and the second column unit 420 are located at opposite outer positions, the first initializing connection portion 510 is connected with the two first initializing transistors T4 in the adjacent first column unit 410 and the pixel circuit in the same row in the second column unit 420, and connection with the two first initializing transistors T4 can be achieved through the first initializing connection portion 510 with a smaller area, which is beneficial to saving layout space of a display panel and improving pixel circuit density.
On the basis of the above technical solution, referring to fig. 8, optionally, the orthographic projection of the first initializing connection portion 510 on the substrate overlaps with the second sub-initializing line Vref12 or the second sub-power line VSS2, the first initializing connection portion 510 is electrically connected to the second sub-initializing line Vref12 through a via hole, and the first initializing connection portion 510 is insulated from the second sub-power line VSS 2.
With continued reference to fig. 5 to 8, alternatively, the first sub-initialization lines Vref11 and the third sub-initialization lines Vref21 are alternately arranged along the second direction y 1; each third sub-initialization line Vref21 is further correspondingly connected to a plurality of second initialization connection parts 520, the second initialization connection parts 520 are located in the third metal layer M3, and the second initialization connection parts 520 are further connected to second initialization transistors T7 in two pixel circuits located in the same row; the second initializing connection portion 520 may be configured to connect the third sub-initializing line Vref21 to the second initializing transistor T7 in the pixel circuit.
Optionally, the second initializing connection portion 520 connects two second initializing transistors T7 in the pixel circuits located in the same row in the adjacent first column unit 410; in this way, the connection with the two second initializing transistors T7 can be realized through the second initializing connection portion 520 with a smaller area, which is beneficial to saving layout space of the display panel and improving pixel circuit density.
Optionally, the orthographic projection of the second initialization connection portion 520 on the substrate overlaps with the fourth sub-initialization line Vref22 or the second sub-power line VSS2, and the second initialization connection portion 520 is electrically connected to the fourth sub-initialization line Vref22 through a via; the second initialization connection 520 is insulated from the second sub power line VSS 2.
With continued reference to fig. 4-8, optionally, the display panel further includes a plurality of first Scan lines Scan1 and second Scan lines Scan2, and the first Scan lines Scan1 are electrically connected to the first initializing transistor T4 and the second initializing transistor T7; the pixel circuit further includes a data writing transistor T2, the data writing transistor T2 being configured to write a data signal to the gate of the driving transistor T1 according to a signal on the second Scan line Scan 2; along the second direction y1, the first Scan line Scan1 is located between the first sub-initialization line Vref11 and the third sub-initialization line Vref21, and the second Scan line Scan2 is located at a side of the third sub-initialization line Vref21 away from the first sub-initialization line Vref 11; the first sub power line VSS1 is located at a side of the first sub initialization line Vref11 away from the third sub initialization line Vref 21; in the second direction y1, the first initialization connection portion 510 and the second initialization connection portion 520 are located between the first sub power line VSS1 and the second Scan line Scan 2.
Specifically, in the related art, a conductive structure connected to the second power line VDD is disposed at the position of the third sub-initialization line Vref21, in this embodiment, the layout space is not increased by setting the position of the conductive structure to the third sub-initialization line Vref21, and a grid structure of the second initialization line Vref2 can be implemented, so that a higher pixel density can be ensured on the basis of implementing a smaller resistance of the second initialization line Vref 2.
With continued reference to fig. 4-8, the pixel circuit further includes a compensation transistor T3, a first light emission control transistor T5, and a second light emission control transistor T6. The gate of the compensation transistor T3 is electrically connected to the second Scan line Scan2, and the gates of the first and second light emission control transistors T5 and T6 are connected to the light emission control signal line EM extending in the first direction x 1.
On the basis of the above technical solution, optionally, a connection via (the first via 10 in fig. 8) between the first initializing connection portion 510 and the second sub-initializing line Vref12, a connection via (the second via 20 in fig. 8) between the second initializing connection portion 520 and the fourth sub-initializing line Vref22, and a connection via (the third via 30 in fig. 8) between the first sub-initializing line and the adjacent third sub-initializing line Vref 21; the connection lines of the connection via holes of the first initialization connection part 510 and the second sub initialization line Vref12, the connection via holes of the second initialization connection part 520 and the fourth sub initialization line Vref24, and the connection via holes of the first power line connection part 501 and the second sub power line VSS2, which are located between the same first sub initialization line Vref11 and the same third sub initialization line Vref21, are straight lines extending in the first direction x 1; therefore, the mask plate for preparing the via hole has simpler structure, simpler process and easy realization.
It should be noted that, in fig. 5 to 8, the third sub-initialization line Vref21 is shown as an example below the first Scan line Scan1, and the first sub-initialization line Vref11 is shown as being above the first Scan line Scan 1; in other alternative embodiments of the present invention, the positions of the first sub-initialization line Vref11 and the third sub-initialization line Vref21 may be exchanged, and accordingly, the third sub-initialization line Vref21 may be located above the first Scan line Scan1, and the first sub-initialization line Vref11 is located below the first Scan line Scan1, where the third sub-initialization line Vref21 has the same structure as the first sub-initialization line Vref11 in fig. 5, the first sub-initialization line Vref11 has the same structure as the third sub-initialization line Vref21 in fig. 5, and accordingly, the positions of the first initialization connection portion 510 and the second initialization connection portion 520 may be adaptively adjusted.
With continued reference to fig. 3 to fig. 5, the driving circuit layer 100 may further include a data line, where the metal layer where the data line is located is on a side of the metal layer where the first power line VSS is located, which is close to the light emitting device. The pixel circuit further includes a data writing transistor T2, the data writing transistor T2 is electrically connected to the data line, and when the data writing transistor T2 is turned on, a data voltage is written to the gate of the driving transistor T1. Optionally, the driving circuit layer further includes a fifth metal layer M5, the fifth metal layer M5 is located on a side of the fourth metal layer M4 near the light emitting device, and the data line is located on the fifth metal layer M5.
Optionally, each column of pixel circuits is correspondingly connected to two Data lines (for example, the first Data line Data1 and the second Data line Data2 in fig. 3 and 5), and the pixel circuits in the odd rows are different from the Data lines connected to the pixel circuits in the even rows; therefore, the load on the data line can be reduced, and the display quality is further improved.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A display panel comprising a display area, the display panel further comprising:
the driving circuit layer comprises a first power line, a second power line and a plurality of pixel circuits, wherein the first power line is at least partially positioned in the display area, the second power line is at least partially positioned in the display area and is electrically connected with the pixel circuits, and driving current generated by the pixel circuits is related to voltage transmitted by the second power line;
The light-emitting devices are located on the driving circuit layer and arranged in the display area, the light-emitting devices comprise first electrodes, light-emitting layers and second electrodes which are arranged in a stacked mode, the first power lines are electrically connected with the second electrodes, and the first power lines are in grid shapes.
2. The display panel of claim 1, wherein the first power line comprises a first sub power line and a second sub power line, the first sub power line and the second sub power line being electrically connected; at least a portion of the first sub power line extends in a first direction, at least a portion of the second sub power line extends in a second direction, and the first direction and the second direction intersect; the driving circuit layer comprises a plurality of metal layers which are laminated on one side of the substrate; wherein the first sub power line and the second sub power line are located in different ones of the metal layers;
preferably, the driving circuit layer at least includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer which are sequentially stacked from one side of the substrate; one of the first sub power line and the second sub power line is positioned on the third metal layer, and the other is positioned on the fourth metal layer;
Preferably, each first sub-power line is correspondingly connected with a plurality of first power line connection parts, the first power line connection parts are located on the third metal layer, orthographic projection of the first power line connection parts on the substrate of the display panel is overlapped with the second sub-power lines, and the second sub-power lines are connected with the first power line connection parts through holes;
preferably, the output end of the pixel circuit is electrically connected with the first electrode of at least one light emitting device, and the pixel circuit comprises at least two thin film transistors and at least one capacitor; the grid electrode of the thin film transistor is positioned on the first metal layer, one polar plate of the capacitor is positioned on the first metal layer, the other polar plate of the capacitor is positioned on the second metal layer, and the source electrode and the drain electrode of the thin film transistor are positioned on the third metal layer;
preferably, the materials of the metal layers where the first sub power line and the second sub power line are located are titanium-aluminum-titanium;
preferably, the material of the second metal layer is molybdenum.
3. The display panel according to claim 2, wherein the second power supply line is in a grid shape;
Preferably, the second power line includes a third sub power line and a fourth sub power line, at least part of the third sub power line extends along a first direction, at least part of the fourth sub power line extends along a second direction, the third sub power line and the fourth sub power line are electrically connected, and the third sub power line and the fourth sub power line are located in different metal layers;
preferably, one of the third sub power line and the fourth sub power line is located at the third metal layer, and the other is located at the fourth metal layer;
preferably, each third sub-power line is correspondingly connected with a plurality of second power line connection parts, the second power line connection parts are located on the third metal layer, orthographic projection of the second power line connection parts on the substrate of the display panel is overlapped with the fourth sub-power lines, and the fourth sub-power lines are connected with the second power line connection parts through holes;
preferably, the pixel circuit array is arranged, the row direction of the pixel circuit array is the first direction, the column direction of the pixel circuit array is the second direction, and one polar plate of the capacitor in the pixel circuit in the same row is connected with each other and is connected to the third sub-power line or the fourth sub-power line;
Preferably, the materials of the metal layers where the third sub-power line and the fourth sub-power line are located are titanium-aluminum-titanium.
4. The display panel according to claim 2, wherein the pixel circuit includes a driving transistor, a first initializing transistor for initializing a gate of the driving transistor, and a second initializing transistor for initializing a first electrode of the light emitting device; the display panel further comprises a first initialization line and a second initialization line, wherein the first initialization line is electrically connected with the first initialization transistor, and the second initialization line is electrically connected with the second initialization transistor; the first initialization line is in a grid shape and/or the second initialization line is in a grid shape;
preferably, the first initializing line includes a first sub-initializing line and a second sub-initializing line, the first sub-initializing line extends along the first direction, the second sub-initializing line extends along the second direction, the first sub-initializing line and the second sub-initializing line are electrically connected, and the first sub-initializing line and the second sub-initializing line are located in different metal layers;
Preferably, the first sub-initialization line is located in the second metal layer;
preferably, the second sub-initializing line and the second sub-power line are located on the same metal layer;
preferably, the second initializing line includes a third sub-initializing line and a fourth sub-initializing line, the third sub-initializing line extends along the first direction, the fourth sub-initializing line extends along the second direction, the third sub-initializing line and the fourth sub-initializing line are electrically connected, and the third sub-initializing line and the fourth sub-initializing line are located in different metal layers;
preferably, the third sub-initialization line is located in the second metal layer;
preferably, the fourth sub-initializing line and the second sub-power line are located at the same metal layer.
5. The display panel according to claim 4, further comprising a plurality of column units including a first column unit and a second column unit each including two columns of the pixel circuits, the first column unit and the second column unit being alternately arranged;
each first column unit is correspondingly connected with one second sub-initialization line and one fourth sub-initialization line; each second column unit is correspondingly provided with two second sub power lines;
Preferably, the relative position of one of the second sub power lines connected to the second column unit in the second column unit is the same as the relative position of the second sub initialization line connected to the first column unit in the first column unit; the relative position of the other second sub power line connected with the second column unit in the second column unit is the same as the relative position of the fourth sub initialization line connected with the first column unit in the first column unit.
6. The display panel according to claim 5, wherein the first initializing transistor and the second initializing transistor in one of the pixel circuits are mirror-image arranged with the first initializing transistor and the second initializing transistor in the other pixel circuit in two pixel circuits located in the same row in the first column unit and the second column unit;
preferably, the first initializing transistor and the second initializing transistor in one pixel circuit and the first initializing transistor and the second initializing transistor in the other pixel circuit are arranged in a mirror image mode, and the two second initializing transistors are located between the two first initializing transistors;
Preferably, in the first column unit, the fourth sub-initialization line is located between two columns of the pixel circuits;
preferably, in the first column unit, the second sub-initialization line is located at one side of the two columns of the pixel circuits.
7. The display panel according to claim 6, wherein the first sub-initialization lines and the third sub-initialization lines are alternately arranged along the second direction;
each first sub-initialization line is correspondingly connected with a plurality of first initialization connecting parts, the first initialization connecting parts are positioned on the third metal layer, and the first initialization connecting parts are positioned on two first initialization transistors in the same row;
preferably, the first initializing connection portion connects two first initializing transistors in the pixel circuits located in the same row in the adjacent first column unit and second column initializing unit;
preferably, the orthographic projection of the first initialization connection portion on the substrate overlaps with the second sub-initialization line or the second sub-power line, the first initialization connection portion is electrically connected with the second sub-initialization line through a via hole, and the first initialization connection portion is arranged in an insulating manner with the second sub-power line.
8. The display panel according to claim 6, wherein the first sub-initialization lines and the third sub-initialization lines are alternately arranged along the second direction;
each third sub-initialization line is correspondingly connected with a plurality of second initialization connecting parts, the second initialization connecting parts are positioned on the third metal layer, and the second initialization connecting parts are also connected with second initialization transistors positioned in two pixel circuits of the same row;
preferably, the second initializing connection portion connects two second initializing transistors in the pixel circuits located in the same row in the adjacent first column units;
preferably, the orthographic projection of the second initialization connection part on the substrate overlaps with the fourth sub-initialization line or the second sub-power line, and the second initialization connection part is electrically connected with the fourth sub-initialization line through a via hole; the second initialization connection portion is arranged in an insulating manner with the second sub power line.
9. The display panel according to claim 7 or 8, further comprising a plurality of first scan lines and second scan lines, wherein the first scan lines are electrically connected to the first initialization transistors and the second initialization transistors; the pixel circuit further includes a data writing transistor writing a data signal to a gate of the driving transistor according to a signal on the second scanning line;
Along the second direction, the first scanning line is located between the first sub-initialization line and a third sub-initialization line, and the second scanning line is located at one side of the third sub-initialization line away from the first sub-initialization line;
the first sub power line is positioned at one side of the first sub initialization line far away from the third sub initialization line;
along the second direction, a first initialization connecting part and a second initialization connecting part are positioned between the first sub power line and the second scanning line;
preferably, the connection via hole of the first initialization connection part and the second sub-initialization line, the connection via hole of the second initialization connection part and the fourth sub-initialization line, and the connection via hole of the first power line connection part and the second sub-power line are located between the first sub-initialization line and the adjacent third sub-initialization line; and connecting lines of the first initialization connecting part and the second sub-initialization line, the second initialization connecting part and the fourth sub-initialization line and the connecting through holes of the first power line connecting part and the second sub-power line are straight lines extending along the first direction.
10. The display panel according to claim 1, wherein the driving circuit layer further comprises a data line, and the metal layer on which the data line is located is on a side of the metal layer on which the first power line is located, which is close to the light emitting device;
preferably, each column of pixel circuits is correspondingly connected with two data lines, and the pixel circuits in the odd rows and the pixel circuits in the even rows are connected with different data lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311862057.8A CN117715469A (en) | 2023-12-29 | 2023-12-29 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311862057.8A CN117715469A (en) | 2023-12-29 | 2023-12-29 | Display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117715469A true CN117715469A (en) | 2024-03-15 |
Family
ID=90149879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311862057.8A Pending CN117715469A (en) | 2023-12-29 | 2023-12-29 | Display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117715469A (en) |
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2023
- 2023-12-29 CN CN202311862057.8A patent/CN117715469A/en active Pending
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