CN117715460A

CN117715460A - Display panel, preparation method thereof and display device

Info

Publication number: CN117715460A
Application number: CN202211014726.1A
Authority: CN
Inventors: 张娟; 孙孟娜; 闫华杰; 王鹏; 焦志强
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-08-23
Filing date: 2022-08-23
Publication date: 2024-03-15

Abstract

A display panel, a preparation method and a display device are provided, wherein the display panel comprises: the display panel comprises a first substrate, at least one first sub-pixel and at least one second sub-pixel, wherein the light emitting directions of the first sub-pixel and the second sub-pixel are opposite, the display panel further comprises an insulating layer provided with at least one pixel opening, the first sub-pixel comprises a first light emitting layer arranged on one side of the insulating layer close to the first substrate, the second sub-pixel comprises a second light emitting layer arranged on one side of the insulating layer far away from the first substrate, the second light emitting layer is arranged in the pixel opening, and the orthographic projection of the first light emitting layer on the first substrate is at least partially positioned outside the orthographic projection of the pixel opening on the first substrate. According to the display panel provided by the embodiment of the disclosure, the light-emitting layer is arranged in the area outside the pixel opening, so that the opening ratio can be increased, and in addition, the independent sub-pixels with different light emitting directions are arranged, so that double-sided independent display can be realized.

Description

Display panel, preparation method thereof and display device

Technical Field

Embodiments of the present disclosure relate to, but not limited to, display technologies, and in particular, to a display panel, a method for manufacturing the same, and a display device.

Background

With the development of diversification of display products, devices with double-sided display functions are becoming more and more popular due to their multi-functional interactivity and good user experience.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display panel, a preparation method thereof and a display device, and double-sided display is realized.

The embodiment of the disclosure provides a display panel, comprising: the display panel comprises a first substrate, at least one first sub-pixel and at least one second sub-pixel, wherein the light emitting direction of the first sub-pixel is a first direction, the light emitting direction of the second sub-pixel is a second direction, the first direction and the second direction are opposite directions, the display panel further comprises an insulating layer provided with at least one pixel opening, the first sub-pixel comprises a first light emitting layer arranged on one side of the insulating layer close to the first substrate, the second sub-pixel comprises a second light emitting layer arranged on one side of the insulating layer far away from the first substrate, the second light emitting layer is arranged in the pixel opening, and the front projection of the first light emitting layer on the first substrate is at least partially positioned outside the front projection of the pixel opening on the first substrate.

In an exemplary embodiment, the first subpixel includes an organic light emitting transistor and the second subpixel includes an organic light emitting transistor.

In an exemplary embodiment, the second subpixel further includes: and a second gate electrode arranged between the insulating layer and the second light emitting layer, a second gate insulating layer arranged on one side of the second gate electrode away from the first substrate, a second source electrode arranged between the second gate insulating layer and the second light emitting layer, a second drain electrode arranged on one side of the second light emitting layer away from the first substrate, and a front projection of the second gate electrode overlapping with a front projection of a bottom wall of the pixel opening on a plane parallel to the first substrate.

In an exemplary embodiment, the first subpixel further includes: the first grid electrode is arranged on one side, far away from the first substrate, of the insulating layer, the first source electrode is arranged between the insulating layer and the first light-emitting layer, the first drain electrode is arranged on one side, close to the first substrate, of the first light-emitting layer, and the orthographic projection of the first grid electrode on the first substrate is at least partially positioned outside the orthographic projection of the pixel opening on the first substrate.

In an exemplary embodiment, the first gate and the second gate are disposed in the same layer.

In an exemplary embodiment, a maximum distance between a surface of the insulating layer away from the first substrate side and the first substrate is greater than a distance between a surface of the second drain electrode away from the first substrate side and the first substrate.

In an exemplary embodiment, the dielectric constant of the insulating layer is 50 nanofarads per square centimeter to 60 nanofarads per square centimeter.

In an exemplary embodiment, the sidewall of the pixel opening forms an angle of 30 degrees to 45 degrees with the first substrate.

In an exemplary embodiment, the insulating layer has a thickness of 180 nm to 800 nm in a direction perpendicular to the first substrate.

An embodiment of the present disclosure provides a display device including the display panel according to any one of the embodiments.

The embodiment of the disclosure provides a method for preparing a display panel, the display panel includes at least one first sub-pixel and at least one second sub-pixel, the light emitting direction of the first sub-pixel is a first direction, the light emitting direction of the second sub-pixel is a second direction, and the first direction and the second direction are opposite directions, the method for preparing the display panel includes:

Forming a first sub-pixel on a first substrate; the first sub-pixel includes a first light emitting layer;

forming an insulating layer on one side of the first light-emitting layer far away from the first substrate, wherein the insulating layer is provided with at least one pixel opening, and the orthographic projection of the first light-emitting layer on the first substrate is at least partially positioned outside the orthographic projection of the pixel opening on the first substrate;

and forming a second sub-pixel on one side of the insulating layer far away from the first substrate, wherein the second sub-pixel comprises a second light-emitting layer, and the second light-emitting layer is arranged in the pixel opening.

The embodiment of the disclosure comprises a display panel, a preparation method thereof and a display device, wherein the display panel comprises: the display panel comprises a first substrate, at least one first sub-pixel and at least one second sub-pixel, wherein the light emitting direction of the first sub-pixel is a first direction, the light emitting direction of the second sub-pixel is a second direction, the first direction and the second direction are opposite directions, the display panel further comprises an insulating layer provided with at least one pixel opening, the first sub-pixel comprises a first light emitting layer arranged on one side of the insulating layer close to the first substrate, the second sub-pixel comprises a second light emitting layer arranged on one side of the insulating layer far away from the first substrate, the second light emitting layer is arranged in the pixel opening, and the front projection of the first light emitting layer on the first substrate is at least partially positioned outside the front projection of the pixel opening on the first substrate. According to the display panel provided by the embodiment of the disclosure, the light-emitting layer is arranged in the area outside the pixel opening, so that the opening ratio can be increased, and in addition, the independent sub-pixels with different light emitting directions are arranged, so that double-sided independent display can be realized.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities particularly pointed out in the specification and the appended drawings.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, and not constitute a limitation of the technical aspects.

FIG. 1 is a schematic diagram of a display panel according to an exemplary embodiment;

FIG. 2 is a schematic view of a display panel according to another exemplary embodiment;

fig. 3 is a schematic diagram of an exemplary embodiment of a first drain layer formed to a first source layer;

fig. 4 is a schematic diagram of a first drain layer to first source layer patterned according to an exemplary embodiment;

fig. 5 is a schematic view of a first gate insulating layer formed according to an exemplary embodiment;

FIG. 6 is a schematic illustration of an exemplary embodiment after deposition of a third metal film;

Fig. 7 is a schematic diagram of an exemplary embodiment after forming a first gate and a second gate;

fig. 8 is a schematic diagram of a second gate insulating layer formed to a second drain electrode according to an exemplary embodiment;

FIG. 9 is a schematic diagram of an exemplary embodiment of a package layer formed;

FIG. 10 is a schematic diagram of a first color film layer according to an exemplary embodiment;

FIG. 11 is a schematic diagram of a color conversion layer formed according to an exemplary embodiment;

fig. 12 is a flowchart of a method for manufacturing a display panel according to an exemplary embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments of the present disclosure and features in the embodiments may be arbitrarily combined with each other without collision.

The steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

In the drawings, the size of each constituent element, the thickness of a layer, or a region may be exaggerated for clarity. Accordingly, embodiments of the present disclosure are not necessarily limited to this size, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or the numerical values shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present disclosure are provided to avoid intermixing of constituent elements, and do not denote any order, quantity, or importance.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the disclosure, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode, and the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In this disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and thus, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In this disclosure, "film" and "layer" may be interchanged. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The phrase "a and B co-layer arrangement" in this disclosure means that a and B are formed simultaneously by the same patterning process. By "the orthographic projection of B is within the range of the orthographic projection of A" it is meant that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

The first type of dual-sided display device employs a simple alignment or bonding process of two OLED devices. The preparation cost and the thickness of the device are greatly increased, and the requirements of the future display on lightness and thinness are not facilitated; the second type of double-sided display device adopts the miniaturization requirements of reducing the display aperture ratio and increasing the circuit to meet the simple and single display function of the shop window, greatly increases the size requirement on the TFT and increases the preparation cost; the third type of double-sided display device is used for realizing double-sided transparency of the display device, and the two sides display the same picture, so that the application range is reduced.

The embodiment of the disclosure provides a display panel, comprising: the display panel comprises an insulating layer provided with at least one pixel opening, the first sub-pixel comprises a first luminescent layer, the second sub-pixel comprises a second luminescent layer, the second luminescent layer is arranged in the pixel opening, and the orthographic projection of the first luminescent layer on the first substrate is at least partially positioned outside the orthographic projection of the pixel opening on the first substrate.

According to the display panel provided by the embodiment of the disclosure, the light-emitting layer is arranged in the area outside the pixel opening, so that the opening ratio can be increased, and in addition, the independent sub-pixels with different light emitting directions are arranged, so that double-sided independent display can be realized.

An Organic Light-Emitting transistor (OLET) is a device integrating the switching function of an Organic field-effect transistor (OFET) and the electroluminescent function of an Organic Light-Emitting Diode (OLED). The OLET device has the advantages of simple structure, mature preparation process, light weight, flexibility, stretchability and easy microminiaturization, and becomes one of the development trends of future display technologies. The working principle of the OLET device is as follows: the gate voltage controls the area and the light emission intensity of the light emitting region while controlling the source-drain current of a portion of the thin film transistor (Thin Film Transistor, TFT). In an exemplary embodiment, a double-sided display may be implemented using OLET.

As shown in fig. 1, the embodiment of the disclosure provides a display panel, which includes at least one first sub-pixel P1 and at least one second sub-pixel P2 disposed on a first substrate 100, where a light emitting direction of the first sub-pixel P1 is a first direction X, a light emitting direction of the second sub-pixel P2 is a second direction Y, the first direction X and the second direction Y are opposite directions, the display panel further includes an insulating layer 14 disposed with at least one pixel opening K1, the first sub-pixel P1 includes a first light emitting layer 122 disposed on a side of the insulating layer 14 near the first substrate 100, the second sub-pixel P2 includes a second light emitting layer 243 disposed on a side of the insulating layer 14 far from the first substrate 100, the second light emitting layer 243 is disposed in the pixel opening K1, and a front projection of the first light emitting layer 122 on the first substrate 100 is at least partially located outside the front projection of the pixel opening K1 on the first substrate 100.

In an exemplary embodiment, the first subpixel P1 includes an organic light emitting transistor, and the second subpixel P2 includes an organic light emitting transistor.

In an exemplary embodiment, the first subpixel P1 may include a bottom-emitting organic light emitting transistor, and the second subpixel P2 may include a top-emitting organic light emitting transistor.

In an exemplary embodiment, the bottom emission organic light emitting transistor may include: the drain electrode, the electron transport layer, the light emitting layer, the hole transport layer, the source electrode, the gate insulating layer and the gate electrode which are sequentially arranged can further comprise: an active layer disposed between the source and hole transport layers. The drain electrode, the electron transmission layer, the light-emitting layer, the hole transmission layer and the source electrode form a light-emitting structure, the electron transmission layer, the light-emitting layer and the hole transmission layer are used as active layers, the drain electrode, the source electrode, the active layers and the grid electrode form a thin film transistor structure, when the voltage difference between the grid electrode and the source electrode exceeds the threshold value of the starting voltage of the thin film transistor structure, current flows from the drain electrode to the source electrode, the current intensity is controlled by the driving voltage of the drain electrode, the light-emitting layer emits light, the light-emitting intensity is influenced by the current intensity, and the larger the current intensity is, the larger the light-emitting intensity is. Top emission is similar and will not be described again.

In an exemplary embodiment, the top-emission organic light emitting transistor may include: the device comprises a grid electrode, a grid insulating layer, a source electrode, a hole transmission layer, a light-emitting layer, an electron transmission layer and a drain electrode which are sequentially arranged; may further include: an active layer disposed between the source and hole transport layers.

In an exemplary embodiment, as shown in fig. 1, the second subpixel P2 may further include: a second gate electrode 21 disposed between the insulating layer 14 and the second light emitting layer 243, a second gate insulating layer 22 disposed at a side of the second gate electrode 21 remote from the first substrate 100, a second source electrode 23 disposed between the second gate insulating layer 22 and the second light emitting layer 243, and a second drain electrode 25 disposed at a side of the second light emitting layer 243 remote from the first substrate 100. On a plane parallel to the first substrate 100, there is an overlap of the orthographic projection of the second gate electrode 21 with the orthographic projection of the bottom wall of the pixel opening K1. The second light emitting layer 243 is a part of the second light emitting functional layer 24 disposed between the second source electrode 23 and the second drain electrode 25. The second light emitting functional layer 24 may include: the second active layer 241, the second hole transport layer 243, the second light emitting layer 243, and the second electron transport layer 244 are sequentially disposed on the side of the second source electrode 23 away from the first substrate 100. The second active layer 241 may buffer current between the second source electrode 23 and the second drain electrode 25. In an exemplary embodiment, the second active layer 241 may not be provided.

In an exemplary embodiment, the second gate insulating layer 22, the second source electrode 23, the second light emitting function layer 24, and the second drain electrode 25 may be disposed within the pixel opening K1. That is, the orthographic projection of the second gate insulating layer 22, the second source electrode 23, the second light emitting functional layer 24, and the second drain electrode 25 on the first substrate 100 is located within the orthographic projection of the pixel opening K1 on the first substrate 100.

In an exemplary embodiment, the first subpixel P1 may further include: the first gate electrode 15 is disposed on a side of the insulating layer 14 away from the first substrate 100, the first source electrode 13 is disposed between the insulating layer 14 and the first light emitting layer 122, the first drain electrode 11 is disposed on a side of the first light emitting layer 122 close to the first substrate 100, and the orthographic projection of the first gate electrode 15 on the first substrate 100 is at least partially located outside the orthographic projection of the pixel opening K1 on the first substrate 100. The first light emitting layer 122 is a portion of the first light emitting functional layer 12 disposed between the first source electrode 13 and the first drain electrode 11. The first light emitting functional layer 12 may include: the first electron transport layer 121, the first light emitting layer 122, the first hole transport layer 123 and the first active layer 124 are sequentially disposed on a side of the first drain electrode 11 remote from the first substrate 100. The first active layer 124 may buffer current between the first source electrode 13 and the first drain electrode 11. In an exemplary embodiment, the first active layer 124 may not be provided.

In an exemplary embodiment, the first gate electrode 15 may be connected to a first scan signal line (providing a first scan signal), the first drain electrode 11 may be connected to a first data signal line (providing a first data signal), and the first source electrode 13 may be connected to the power signal line VSS. The second gate electrode 21 may be connected to a second scan control signal line; the second drain electrode 25 may be connected to a second data signal line, and the second electrode 23 may be connected to a power signal line VSS.

In the scheme provided in this embodiment, the insulating layer 14 is multiplexed to be the first gate insulating layer of the first sub-pixel P1, that is, the insulating layer 14 is used as both the pixel defining layer and the first gate insulating layer, so that the non-pixel opening area can be fully utilized, the effective display area can be enlarged, and the opening ratio can be enlarged.

In an exemplary embodiment, the orthographic projections of the first source electrode 13, the first light emitting functional layer 12, and the first drain electrode 11 on the first substrate 100 are at least partially located outside the orthographic projection of the pixel opening K1.

In an exemplary embodiment, the first and second sub-pixels P1 and P2 may be disposed at intervals on a plane parallel to the first substrate 100. However, the embodiment of the present disclosure is not limited thereto, and one second subpixel P2 may be disposed after a plurality of first subpixels P1 are disposed, or one first subpixel may be disposed after a plurality of second subpixels P2 are disposed, as needed.

In an exemplary embodiment, the first source electrode 13, the first light emitting function layer 12, and the first drain electrode 11 of the adjacent first sub-pixel P1 are separated by an insulating layer 14.

In an exemplary embodiment, the first gate electrode 15 and the second gate electrode 21 may be disposed in the same layer. The embodiments of the present disclosure are not limited thereto and the first gate electrode 15 and the second gate electrode 21 may be disposed in different layers.

In an exemplary embodiment, a maximum distance between a surface of the insulating layer 14 away from the first substrate 100 and the first substrate 100 is greater than a distance between a surface of the second drain electrode 25 away from the first substrate 100 and the first substrate 100. In the present embodiment, when the first gate electrode 15 is disposed outside the pixel opening region, the first gate electrode 15 can be prevented from being connected to the second drain electrode 25 by disposing the thickness of the insulating layer 14.

In an exemplary embodiment, the insulating layer 14 is a high dielectric constant material. For example, a material having a relative dielectric constant of more than 3.9 may be used. In this embodiment, since the insulating layer 14 is used as the first gate insulating layer of the first sub-pixel and is used as the pixel defining layer, the thickness is larger than that of the conventional gate insulating layer, the larger the dielectric constant is, the thicker the film thickness can be, and when a material with a high dielectric constant is used, even the thicker gate insulating layer can play the same role as the thinner gate insulating layer, and the gate leakage current caused by tunneling can be reduced or eliminated due to the increased physical thickness, so that the problems caused by increasing the area and reducing the film thickness of the OLET light emitting unit are avoided.

In an exemplary embodiment, the dielectric constant K of the insulating layer 14 may be 50 to 60 nanofarads/square centimeter. Assume that SiO ₂ As the gate insulating layer, the film thickness is about 70 nanometers (nm), and in order to ensure the capacitance storage amount is equal, eot=3.9×t according to the formula _high-k /k _high-k It can be obtained that when the dielectric constant K is 55 nano-meter/square centimeter, the thickness of the gate insulating layer is 0.99um, i.e. when a material with a larger dielectric constant is used as the gate insulating layer, a larger thickness can be used, wherein EOT is the equivalent oxide thickness, and the capacitance value of the gate insulating layer is defined by comparing SiO2, i.e. the theoretical thickness when using pure SiO2 material, t _high-k K is the actual physical thickness of the gate insulating layer _high-k Is the relative dielectric constant of the gate insulating layer.

In an exemplary embodiment, the included angle between the sidewall of the pixel opening K1 and the first substrate 100 may be 30 degrees to 45 degrees.

In an exemplary embodiment, the thickness of the insulating layer 14 in a direction perpendicular to the first substrate 100 may be 180 nm to 800 nm. A film thickness of a conventional Pixel Definition Layer (PDL) is typically about 1 micrometer (um), and in this embodiment, a thinner film layer can be prepared as the pixel definition layer, and the thickness of the device can be reduced, so that the product is thinner and lighter.

Fig. 2 is a schematic view of a display panel according to another exemplary embodiment. In this embodiment, OLET is used as the light emitting device. As shown in fig. 2, the display panel provided in this embodiment includes: the first substrate 100, the first drain 11 disposed on the first side of the first substrate 100, the first light emitting function layer 12 disposed on the first drain 11 side far from the first substrate 100, the first source 13 disposed on the first light emitting function layer 12 side far from the first substrate 100, the first gate insulating layer 14 disposed on the first source 13 side far from the first substrate 100, the first gate insulating layer 14 is provided with at least one pixel opening K1, the first gate 15 and the second gate 21 disposed on the first gate insulating layer 14 side far from the first substrate 100, the second gate insulating layer 22 disposed on the second gate 21 side far from the first substrate 100, the second source 23 disposed on the second gate insulating layer side far from the first substrate 100, the second light emitting function layer 24 disposed on the second source 23 side far from the first substrate 100 within the first pixel opening K1, the second drain 24 disposed on the second light emitting function layer 24 side far from the first substrate 100, and the first drain 24 disposed on the first side far from the first substrate 30.

In an exemplary embodiment, the display panel may further include a second color film layer 26 disposed on a side of the encapsulation layer 30 remote from the first substrate 100, and the second color film layer 26 may include a second color filter layer 261 and a second black matrix 262. However, embodiments of the present disclosure are not limited thereto, and the display panel may not include the second color film layer 26.

In an exemplary embodiment, the display panel may further include a quantum dot color resist layer 17 disposed on the second side of the first substrate 100, and a second substrate 200 disposed on a side of the quantum dot color resist layer 17 remote from the first substrate 100. The quantum dot color resist layer 17 may include a quantum dot color resist 171 and a barrier wall 172 for defining the quantum dot color resist 171. The second side and the first side are opposite sides.

In an exemplary embodiment, the display panel may further include a first color film layer 16 disposed between the quantum dot color resist layer 17 and the second substrate 200, and the first color film layer 16 may include a first color filter layer 161 and a first black matrix 162. Embodiments of the present disclosure are not limited thereto and may not include the first color film layer 16.

The technical scheme of this embodiment is further described below through the manufacturing process of the display panel of this embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, photoresist stripping, etc., and is a well-known preparation process in the related art. The "photolithography process" in this embodiment includes coating a film layer, mask exposure and development, and is a well-known preparation process in the related art. The deposition may be performed by known processes such as sputtering, vapor deposition, chemical vapor deposition, etc., the coating may be performed by known coating processes, and the etching may be performed by known methods, which are not particularly limited herein. In the description of the present embodiment, it is to be understood that "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process or a photolithography process throughout the fabrication process. If the "film" is also subjected to a patterning process or a photolithography process during the entire fabrication process, it is referred to as a "film" before the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

In an exemplary embodiment, the manufacturing process of the display panel may include:

1) A first metal film 110, a first electron transport layer film 1201, a first light emitting layer film 1202, a first hole transport layer film 1203, a first active layer film 1204, and a second metal film 130 are sequentially deposited on the first substrate 100, as shown in fig. 3.

In an exemplary embodiment, the first substrate 100 may be a synthetic resin such as sapphire, rigid glass, polyimide (PI), polyethylene terephthalate (Polyethylene terephthalate, PET), PET/Polyethersulfone (PES) \polycarbonate (PC), or a silicon substrate, which is adjusted according to different usage scenarios and different application requirements.

In an exemplary embodiment, the material of the first metal film 110 includes, but is not limited to, at least one of: metals or metal alloys such as gold, silver, copper, aluminum, magnesium, and Indium-Zinc-Oxide (IZO), and the like.

In an exemplary embodiment, the first metal thin film may be a magnesium-silver alloy in consideration of work function, conductivity, and light transmittance of the metal electrode.

In an exemplary embodiment, the first metal film 110 may be deposited by evaporation.

In an exemplary embodiment, the thickness of the first metal thin film 110 may be about in a direction perpendicular to the first substrate 100Facilitating transmission of light emitted to the first metal film 110.

In an exemplary embodiment, the first electron transport layer film 1201, the first light emitting layer film 1202, the first hole transport layer film 1203, and the first active layer film 1204 may be deposited using vacuum evaporation.

In an exemplary embodiment, the second metal film 130 includes, but is not limited to, at least one of: metals or metal alloys such as gold, silver, copper, aluminum, magnesium, etc.

In an exemplary embodiment, the second metal film 130 may be gold.

In an exemplary embodiment, the thickness of the second metal film 130 along the direction perpendicular to the first substrate 100 is greater than or equal to 100nm to provide holes and reflected light, and increase the light output.

2) The first metal film 110, the first electron transport layer film 1201, the first light emitting layer film 1202, the first hole transport layer film 1203, the first active layer film 1204, and the second metal film 130 are patterned to form a plurality of divided first light emitting units including a first drain electrode 11, a first electron transport layer 121, a first light emitting layer 122, a first hole transport layer 123, a first active layer 124, and a first source electrode 13, as shown in fig. 4.

The first drain electrode 11, the first electron transport layer 121, the first light emitting layer 122, the first hole transport layer 123, and the first active layer 124 constitute a light emitting functional layer. The structure of the light emitting functional layer shown in fig. 4 is only an example. In another exemplary embodiment, the light emitting functional layer may increase or decrease the film layer as needed, for example, to increase efficiency of injecting electrons and holes into the first light emitting layer, at least one of the hole injecting layer and the electron injecting layer may be provided. For another example, to simplify the structure of the light emitting functional layer, the first electron transport layer 121 and the first hole transport layer 123 may be removed.

In an exemplary embodiment, the first light emitting layer 122 may emit blue light. In another exemplary embodiment, the first light emitting layer 122 may emit white light; alternatively, the different first light emitting layers 122 may emit the first color light, the second color light, the third color light, and so on, respectively. The first color light, the second color light, and the third color light are, for example, red light, green light, and blue light, respectively.

In an exemplary embodiment, patterning may be performed using reactive ion etching techniques, patterning (Photo pattern), ion implantation techniques, and the like.

3) On the first substrate 100 on which the foregoing pattern is formed, a first gate insulating film is deposited, and the first gate insulating film is patterned to form a first gate insulating layer 14, and the first gate insulating layer 14 is provided with at least one pixel opening K1, as shown in fig. 5. The front projection of the first light emitting layer 122 is at least partially located outside the front projection of the bottom wall of the pixel opening K1.

In an exemplary embodiment, the cross section of the pixel opening K1 may be an inverted trapezoid in a plane perpendicular to the first substrate 100.

In an exemplary embodiment, the cross section of the pixel opening K1 may be circular, square, hexagonal, etc. in a plane parallel to the first substrate 100.

In an exemplary embodiment, the first gate insulating film may be deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD) or atomic layer deposition (Atomic Layer Deposition, ALD). The thin film prepared by the ALD process has better compactness.

In an exemplary embodiment, the first gate insulating film may include, but is not limited to, at least one of: aluminum oxide (AL) ₂ O ₃ ) Silicon nitride (SiNx), silicon oxide (SiO) _x ). The first gate insulating film may be a material having a high dielectric constant, for example, a material having a relative dielectric constant of 3.9 or more.

In an exemplary implementation, the first gate insulating film may have a dielectric constant K value of 50 nanofarads per square centimeter (nF/cm) ² ) To 60nF/cm ² 。

In an exemplary embodiment, the first gate insulating film may be patterned using a Mo (molybdenum) etching process.

In an exemplary embodiment, the maximum thickness h of the first gate insulating layer 14 in a direction perpendicular to the first substrate 100 may be 1±10% um.

In an exemplary embodiment, the angle α between the sidewall of the pixel opening K1 and the first substrate 100 (also referred to as the gradient angle of the pixel opening K1) is about 30 ° to 45 °.

In this embodiment, the first gate insulating layer 14 functions as a Pixel Defining Layer (PDL) defining at least one pixel opening, in addition to the gate insulating layer. The reason why the film thickness of the conventional PDL is about 1um is that if the PDL is too thin, the via hole of the flat layer (PLN) cannot be well planarized, and in addition, too thin PDL film layer cannot be prepared (PDL is prepared by coating) due to the self-properties of the material used in the PDL. In this embodiment, no PLN via is provided, and CVD or ALD process may be used to prepare the first gate insulating layer, so that a thinner first gate insulating layer 14 may be prepared. In an exemplary embodiment, the maximum thickness h of the first gate insulating layer 14 along the direction perpendicular to the first substrate 100 may be 180nm to 800nm, i.e., the PDL film function may be implemented using a thinner film layer, so that the device thickness may be reduced.

In an exemplary embodiment, the thickness of the first gate insulating layer 14 along the direction perpendicular to the first substrate 100 may be greater than the thickness of the OLET device film to ensure that functional layers segments between pixels are isolated from each other. However, the embodiments of the present disclosure are not limited thereto, and when the thickness of the first gate insulating layer 14 along the direction perpendicular to the first substrate 100 is less than or equal to the thickness of the OLET device, an isolation layer may be provided to isolate the first gate electrode from the second drain electrode 25 and other film layers.

In an exemplary embodiment, the first gate insulating layer 14 may have a maximum thickness h in a direction perpendicular to the first substrate 100 of 220nm to 800nm, thereby being greater than an OLET device film thickness (about 210nm to 720 nm).

4) On the first substrate 100 formed with the foregoing pattern, a third metal thin film 150 is deposited as shown in fig. 6.

In an exemplary embodiment, the third metal film 150 may be at least one of: metals such as gold, silver, copper, aluminum, and magnesium, or alloy metals.

5) The third metal film 150 is patterned to form a first gate electrode 15 and a second gate electrode 21, as shown in fig. 7. The first gate 15 and the second gate 21 are disconnected. On a plane parallel to the first substrate 100, the orthographic projection of the second gate electrode 21 overlaps with the orthographic projection of the bottom wall of the pixel opening K1, and the orthographic projection of the first gate electrode 15 is at least partially located outside the orthographic projection of the pixel opening K1.

In an exemplary embodiment, the orthographic projection of the second gate 21 is located within the orthographic projection of the bottom wall of the pixel opening K1.

In an exemplary embodiment, the front projection of the first gate 15 is located outside the front projection of the pixel opening K1.

In an exemplary embodiment, the second metal thin film may be patterned using a Mo etching process.

6) Depositing a second gate insulating film in the pixel opening K1, and patterning the second gate insulating film to form a second gate insulating layer 22;

a fourth metal film, a second active layer film, a second hole transport layer film, a second light emitting layer film, a second electron transport layer film, and a fifth metal film are sequentially deposited in the pixel opening K1, and a second source electrode 23, a second active layer 241, a second hole transport layer 242, a second light emitting layer 243, a second electron transport layer 244, and a second drain electrode 25 are sequentially formed as shown in fig. 8. The second active layer 241, the second hole transport layer 242, the second light emitting layer 243, and the second electron transport layer 244 constitute the second light emitting functional layer 24.

In an exemplary embodiment, the second light emitting layer 243 may emit white light; alternatively, the different second light emitting layers 243 may emit the first color light, the second color light, and the third color light, respectively; alternatively, the second light emitting layer 243 may emit blue light, and so on.

In an exemplary embodiment, the second gate insulating layer 22 overlaps with the orthographic projection of the pixel opening K1.

In an exemplary embodiment, the orthographic projection of the second gate insulating layer 22 may be located within the orthographic projection of the pixel opening K1.

In an exemplary embodiment, a surface of the second drain electrode 25 away from the first substrate 100 is spaced from the first substrate 100 less than a surface of the first gate electrode 15 near the first substrate 100 is spaced from the first substrate 100.

7) On the substrate on which the foregoing pattern is formed, an encapsulation layer 30 is formed by depositing at least one of an inorganic material and a coating organic material, as shown in fig. 9. For example, the encapsulation layer 30 may be a laminate structure of inorganic material/organic material/inorganic material. In an exemplary embodiment, the encapsulation layer 30 may be prepared using silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiNxOy), or the like.

8) Forming a second color film layer 26 on the encapsulation layer 30, as shown in fig. 10;

the forming the second color film layer 26 on the encapsulation layer 30 includes: forming a second black matrix 262 spaced apart from the first substrate 100 on a side of the encapsulation layer 30;

a second color filter layer 261 is formed at a gap of the second black matrix 262, and the second color filter layer 261 may include a first color filter, a second color filter, and a third color filter. The first color filter only allows the first color light to pass through and filters out other color light; the second color filter only allows the second color light to pass through and filters out other color light; the third color filter allows only the third color light to pass therethrough, filtering out the other color light. The first color filter is, for example, a red filter, the second color filter is, for example, a green filter, and the third color filter is, for example, a blue filter.

9) Forming a color conversion layer on the second substrate 200;

the forming of the color conversion layer includes:

forming first black matrices 162 disposed at intervals on the second substrate 200;

a first color filter layer 161 is formed in the gap of the first black matrix 162, the second color filter layer 161 may include a first color filter, a second color filter, and a third color filter, and the first color filter layer 161 and the first black matrix 162 form the first color film layer 16. The color filter layer 161

Forming a retaining wall 172 for defining a quantum dot color resistance 171 on the side of the first color film layer 16 away from the second substrate 200; the retaining wall 172 corresponds to the first black matrix 162;

quantum dot color resistors 171 are formed in the defined areas of the barriers 172 as shown in fig. 11. The quantum dot color resistors 171 may include a first color quantum dot color resistor (which emits light of a first color when excited), a second color quantum dot color resistor (which emits light of a second color when excited), and a third color quantum dot color resistor (which emits light of a third color when excited, or emits light of a color consistent with that of the incident light); the third color quantum dot color resistance may be scattering particles, which do not color convert the incident light. For example, the blue light can be incident to the red quantum dot color resistor, the blue light can be incident to the green quantum dot color resistor, the green quantum dot color resistor can emit green light, the blue light can be incident to the scattering particle color resistor, and the scattering particle color resistor still emits blue light. The quantum dot color resist 171 and the retaining wall 172 form the quantum dot color resist layer 17.

10 The first substrate 100 and the second substrate 200 are subjected to alignment to form the display panel, as shown in fig. 2.

In an exemplary embodiment, an adhesive layer may be formed on a side of the first substrate 100 remote from the first drain electrode 11, or the first substrate 100 may be adhered to the quantum dot color resist layer after an adhesive layer is formed on a side of the quantum dot color resist layer 17 remote from the second substrate 100.

According to the structure and the preparation flow of the display panel, the display panel provided by the embodiment fully utilizes the non-pixel opening area, enlarges the effective display area, increases the opening ratio, can realize double-sided display and can display different pictures, and uses the OLET as a light-emitting device, so that the display panel has the advantages of light weight, flexibility, stretchability and low cost. In addition, the QD-OLET device has the advantages of high color gamut, wide viewing angle, and low cost. The display panel provided by the embodiment of the disclosure has the advantages of greatly reducing the thickness of the device, reducing the preparation cost of the device, simplifying the preparation process, and achieving the technical effects of double-sided display and capability of displaying different pictures. The preparation process of the embodiment of the disclosure can be realized by using the existing mature preparation equipment, has small improvement on the existing process, can be well compatible with the existing preparation process, and has the advantages of simple process realization, easy implementation, high production efficiency and low cost.

The display panel and the manufacturing process thereof provided in the embodiments of the present disclosure are merely exemplary, and in an exemplary embodiment, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs. For example, the second color film layer 26 may be removed; for another example, a quantum dot color resist layer is disposed between the second color film layer 26 and the encapsulation layer 30, where the first light emitting layer 122 may emit blue light, and so on.

In another exemplary embodiment, the first subpixel may be an OLET subpixel, an OLED subpixel, or an LED subpixel, and the second subpixel may be an OLET subpixel, an OLED subpixel, or an LED subpixel. That is, the combination of the first sub-pixel and the second sub-pixel may be a combination of olet+olet, olet+oled, oled+led olet+led, oled+oled, or the like, and the light emitting unit of one of the first sub-pixel and the second sub-pixel may be disposed in the pixel opening of the pixel defining layer, and the light emitting unit of the other sub-pixel may be disposed in the non-pixel opening region.

Fig. 12 is a flowchart of a method for manufacturing a display panel according to an exemplary embodiment. As shown in fig. 12, the present embodiment provides a method for manufacturing a display panel, where the display panel includes at least one first sub-pixel and at least one second sub-pixel, the light emitting direction of the first sub-pixel is a first direction, the light emitting direction of the second sub-pixel is a second direction, and the first direction and the second direction are opposite directions, and the method includes:

Step 1201, forming a first sub-pixel on a first substrate; the first sub-pixel comprises a first light-emitting layer and an insulating layer arranged on one side, far away from the first substrate, of the first light-emitting layer, wherein the insulating layer is provided with at least one pixel opening, and the orthographic projection of the first light-emitting layer on the first substrate is at least partially positioned outside the orthographic projection of the pixel opening on the first substrate;

in step 1202, a second sub-pixel is formed on a side of the insulating layer away from the first substrate, where the second sub-pixel includes a second light emitting layer, and the second light emitting layer is disposed in the pixel opening.

In an exemplary embodiment, the forming the first sub-pixel on the first substrate includes:

sequentially depositing a first metal film, a first light-emitting layer film and a second metal film on the first substrate, and patterning to form a first drain electrode, a first light-emitting layer and a first source electrode;

depositing a first gate insulating film on a first substrate on which the patterns are formed, and patterning to form an insulating layer, wherein the insulating layer is provided with at least one pixel opening;

and depositing a third metal film on the first substrate with the patterns, and patterning the first grid electrode of the first sub-pixel and the second grid electrode of the second sub-pixel.

In an exemplary embodiment, the forming the second sub-pixel on the insulating layer side away from the first substrate includes:

depositing a second gate insulating film in the pixel opening, and patterning the second gate insulating film to form a second gate insulating layer;

and sequentially evaporating a fourth metal film, a second light-emitting layer film and a fifth metal film in the pixel opening to form a second source electrode, a second light-emitting layer and a second drain electrode.

The embodiment of the disclosure also provides a display device, which comprises the display panel of the embodiment. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.

Claims

1. A display panel, comprising: the display panel comprises a first substrate, at least one first sub-pixel and at least one second sub-pixel, wherein the light emitting direction of the first sub-pixel is a first direction, the light emitting direction of the second sub-pixel is a second direction, the first direction and the second direction are opposite directions, the display panel further comprises an insulating layer provided with at least one pixel opening, the first sub-pixel comprises a first light emitting layer arranged on one side of the insulating layer close to the first substrate, the second sub-pixel comprises a second light emitting layer arranged on one side of the insulating layer far away from the first substrate, the second light emitting layer is arranged in the pixel opening, and the front projection of the first light emitting layer on the first substrate is at least partially positioned outside the front projection of the pixel opening on the first substrate.

2. The display panel of claim 1, wherein the first subpixel comprises an organic light emitting transistor and the second subpixel comprises an organic light emitting transistor.

3. The display panel of claim 1, wherein the second subpixel further comprises: and a second gate electrode arranged between the insulating layer and the second light emitting layer, a second gate insulating layer arranged on one side of the second gate electrode away from the first substrate, a second source electrode arranged between the second gate insulating layer and the second light emitting layer, a second drain electrode arranged on one side of the second light emitting layer away from the first substrate, and a front projection of the second gate electrode overlapping with a front projection of a bottom wall of the pixel opening on a plane parallel to the first substrate.

4. The display panel of claim 3, wherein the first subpixel further comprises: the first grid electrode is arranged on one side, far away from the first substrate, of the insulating layer, the first source electrode is arranged between the insulating layer and the first light-emitting layer, the first drain electrode is arranged on one side, close to the first substrate, of the first light-emitting layer, and the orthographic projection of the first grid electrode on the first substrate is at least partially positioned outside the orthographic projection of the pixel opening on the first substrate.

5. The display panel of claim 4, wherein the first gate and the second gate are disposed in the same layer.

6. The display panel according to claim 4, wherein a maximum distance between a surface of the insulating layer on a side away from the first substrate and the first substrate is greater than a distance between a surface of the second drain electrode on a side away from the first substrate and the first substrate.

7. The display panel according to any one of claims 1 to 6, wherein a dielectric constant of the insulating layer is 50 nano-farads/square centimeter to 60 nano-farads/square centimeter.

8. The display panel of any one of claims 1 to 6, wherein the sidewall of the pixel opening forms an angle of 30 degrees to 45 degrees with the first substrate.

9. The display panel according to any one of claims 1 to 6, wherein a thickness of the insulating layer in a direction perpendicular to the first substrate is 180 nm to 800 nm.

10. A display device comprising the display panel according to any one of claims 1 to 9.

11. The preparation method of the display panel is characterized in that the display panel comprises at least one first sub-pixel and at least one second sub-pixel, the light emergent direction of the first sub-pixel is a first direction, the light emergent direction of the second sub-pixel is a second direction, and the first direction and the second direction are opposite directions, and the preparation method comprises the following steps:

forming a first sub-pixel on a first substrate; the first sub-pixel comprises a first light-emitting layer and an insulating layer arranged on one side of the first light-emitting layer away from the first substrate; the insulation layer is provided with at least one pixel opening, and the orthographic projection of the first light-emitting layer on the first substrate is at least partially positioned outside the orthographic projection of the pixel opening on the first substrate;