CN117712028A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN117712028A CN117712028A CN202211102389.1A CN202211102389A CN117712028A CN 117712028 A CN117712028 A CN 117712028A CN 202211102389 A CN202211102389 A CN 202211102389A CN 117712028 A CN117712028 A CN 117712028A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 99
- 230000004888 barrier function Effects 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000007769 metal material Substances 0.000 claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- 238000000137 annealing Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 352
- 239000000463 material Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 36
- 229910017052 cobalt Inorganic materials 0.000 claims description 21
- 239000010941 cobalt Substances 0.000 claims description 21
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 21
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 18
- 229910021389 graphene Inorganic materials 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 15
- 229910052715 tantalum Inorganic materials 0.000 claims description 15
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- 238000011049 filling Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 125000004429 atom Chemical group 0.000 description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 24
- 230000002093 peripheral effect Effects 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 16
- 238000006243 chemical reaction Methods 0.000 description 14
- 238000003746 solid phase reaction Methods 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000012071 phase Substances 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910004523 TaCo Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000010671 solid-state reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Abstract
The application relates to a semiconductor structure and a preparation method thereof, wherein the preparation method of a semiconductor comprises the following steps: providing a substrate, and forming a semiconductor contact layer on the substrate; forming a diffusion barrier layer on the semiconductor contact layer; forming a metal material layer on the diffusion barrier layer, wherein the metal material layer contains metal atoms; annealing treatment is carried out so that metal atoms diffuse into the semiconductor contact layer through the diffusion barrier layer and react with the metal atoms to generate a contact structure; the ratio of the thickness of the diffusion barrier layer to the thickness of the metal material layer is a preset ratio. The embodiment of the application can effectively improve the film thickness uniformity of the contact structure.
Description
Technical Field
The present disclosure relates to semiconductor technology, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
In semiconductor device structures, metal silicides are typically used as contact structures to reduce the contact resistance between the semiconductor and the metal. Currently, metal silicide is formed by depositing metal directly on silicon and then interdiffusing metal atoms with silicon atoms by a rapid thermal annealing technique.
However, the metal silicide formed in the above manner and its easy thickness are not uniform, thereby affecting the device performance.
Disclosure of Invention
Based on the above, the embodiment of the application provides a semiconductor structure and a preparation method thereof, so as to improve the film thickness uniformity of a contact structure.
A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming a semiconductor contact layer on the substrate;
forming a diffusion barrier layer on the semiconductor contact layer;
forming a metal material layer on the diffusion barrier layer, wherein the metal material layer contains metal atoms;
annealing treatment is carried out so that the metal atoms diffuse into the semiconductor contact layer through the diffusion barrier layer and react with the diffusion barrier layer to generate a contact structure;
wherein the ratio of the thickness of the diffusion barrier layer to the thickness of the metal material layer is a preset ratio.
In one embodiment, the diffusion barrier layer has a melting point that is higher than the melting point of the metal material layer.
In one embodiment, the diffusion barrier layer comprises graphene and/or tantalum and the metal material layer comprises cobalt.
In one embodiment, the preset ratio is greater than or equal to 1:10.
in one embodiment, the preset ratio is less than or equal to 1:7.
in one embodiment, the forming a semiconductor contact layer on the substrate includes:
forming an interconnection contact hole on the substrate;
filling a semiconductor contact material layer in the interconnection contact hole;
and carrying out back etching on the semiconductor contact material layer at the top of the interconnection contact hole, and forming the semiconductor contact layer by the remained semiconductor contact material layer.
In one embodiment, the forming a diffusion barrier layer on the semiconductor contact layer includes:
and depositing a diffusion barrier material in the interconnection contact hole to form the diffusion barrier layer on the side wall of the interconnection contact hole and the surface of the semiconductor contact layer.
In one embodiment, the etching is performed on the semiconductor contact material layer at the top of the interconnection contact hole, and at the same time, etching is performed on the top hole wall of the interconnection contact hole so as to enlarge the aperture of the interconnection contact hole, and after the etching is performed on the semiconductor contact material layer at the top of the interconnection contact hole, the surface of the formed semiconductor contact layer is concave or convex;
after the contact structure is generated, the method further comprises:
and forming a metal filling layer on the surface of the contact structure.
In one embodiment, the material of the semiconductor contact layer comprises silicon, the material of the metal material layer comprises cobalt,
the annealing treatment comprises the following steps:
heating the substrate and a film layer formed on the substrate to a first preset temperature, wherein the first preset temperature is 400-450 ℃;
maintaining the first preset time at a first preset temperature, wherein the first preset time is 1-2 h.
In one of the embodiments of the present invention,
the heating the substrate to a first preset temperature is preceded by:
heating the substrate and the film layer formed on the substrate to a second preset temperature, wherein the second preset temperature is 250-350 ℃;
maintaining the second preset time at a second preset temperature for 10s to 20s;
the heating the substrate and the film layer formed thereon to a first preset temperature includes:
and heating the substrate and the film layer formed on the substrate from a second preset temperature to the first preset temperature.
In one embodiment, after the metal material layer is formed on the diffusion barrier layer, before the annealing treatment, the method further includes:
and forming a protective layer on the metal material layer.
In one embodiment, the protective layer comprises a titanium nitride layer.
In one embodiment, the protective layer has a thickness of 5nm to 10nm.
In one embodiment, after the annealing treatment, the method further comprises:
and removing the protective layer, the unreacted metal material layer and the diffusion barrier layer.
In one embodiment, the surface of the semiconductor contact layer has a concave-convex structure.
A semiconductor structure, comprising:
a substrate including a semiconductor contact layer;
a contact structure formed on the semiconductor contact layer according to any one of the methods described above.
According to the preparation method of the semiconductor structure, before the metal material layer is formed, the diffusion barrier layer is formed first, and the ratio of the thickness of the diffusion barrier layer to the thickness of the metal material layer is controlled to be a preset ratio, so that the movement speed of metal atoms diffused to each position in the semiconductor contact layer tends to be consistent in the annealing process. The rate of the solid phase reaction is mainly affected by the diffusion of the reaction phase, so that the reaction rate of the semiconductor contact layer and the metal atoms diffused to each position in the semiconductor contact layer tends to be consistent, and a contact structure with uniform thickness can be formed.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment;
FIG. 3 is a schematic illustration of a diffusion barrier layer formed on a substrate as provided in one embodiment;
FIG. 4 is a schematic illustration of a diffusion barrier layer formed on a substrate as provided in another embodiment;
FIGS. 5-9 are schematic cross-sectional views of structures during various steps in forming contact structures within interconnect contact holes in one embodiment;
FIG. 10 is a schematic diagram of an annealing temperature profile in one embodiment.
Reference numerals illustrate:
100-substrate, 110-semiconductor contact layer, 100 a-interconnection contact hole, 200 diffusion barrier layer, 300-metal material layer, 400-contact structure, 500-bit line structure, 600-dielectric layer, 700-protective layer, 10-first polysilicon, 20-second polysilicon.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Meanwhile, embodiments of the present application should not be limited to a specific shape of a region shown in the drawings of the specification, but include a deviation of shape due to, for example, a manufacturing technique.
In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, including the following steps:
step S11, please refer to fig. 3 and fig. 5, a substrate 100 is provided, and a semiconductor contact layer 110 is formed on the substrate 100;
step S12, please refer to fig. 6, a diffusion barrier layer 200 is formed on the semiconductor contact layer 110;
step S13, referring to fig. 7, a metal material layer 300 is formed on the diffusion barrier layer 200, wherein the metal material layer 300 contains metal atoms;
in step S15, referring to fig. 8, an annealing process is performed to diffuse metal atoms into the semiconductor contact layer 110 through the diffusion barrier layer 200 and react with the metal atoms, so as to form a contact structure 400.
Wherein, the ratio of the thickness of the diffusion barrier layer 200 to the thickness of the metal material layer is a predetermined ratio.
In step S11, the base 100 may specifically include a semiconductor substrate. The semiconductor substrate is provided with an array region and a peripheral circuit region. The array region is used to form a memory array. The peripheral circuit region is used for forming a peripheral circuit. The peripheral circuitry may control the memory array. Transistors may be included in both the memory array and the peripheral circuitry.
The base 100 may also include structures (including array region structures, peripheral circuit region structures, and the like) formed in or over the semiconductor substrate. The semiconductor substrate includes, but is not limited to, a silicon substrate. It may also be a germanium substrate, or a silicon germanium substrate, for example.
Specifically, a shallow trench isolation structure (Shallow Trench Isolation, STI for short) may be formed in the semiconductor substrate, and the shallow trench isolation structure may isolate a plurality of Active areas (AA for short) arranged at intervals in the substrate.
The active region may include a P-type active region or an N-type active region. The P-type active region may form an N-type transistor (e.g., NMOS), and the P-type active region may be formed by implanting N-type ions to form source and drain regions of the N-type transistor. The N-type active region may form a P-type transistor (e.g., PMOS), and the N-type active region may be formed by implanting P-type ions to form source and drain regions of the P-type transistor. The array region and the peripheral circuit region may each form a transistor.
In the array region, referring to fig. 3, the source region and the drain region of the transistor may be respectively connected to the first polysilicon 10 in the capacitor contact hole and the second polysilicon 20 in the bit line contact hole. In the peripheral circuit region, referring to fig. 4, contact holes may be formed on the source and drain regions of the transistor.
The semiconductor contact layer 110 may be a film layer for conducting connection formed based on a heavily doped semiconductor material.
By way of example, the semiconductor contact layer 110 may be part of a semiconductor substrate, such as a source region and/or a drain region of a transistor formed within the semiconductor substrate (see fig. 4). Alternatively, the semiconductor contact layer 110 may be a polysilicon layer (e.g., the first polysilicon 10 and/or the second polysilicon 20 in fig. 3) formed on the semiconductor substrate, or the like.
In step S12, referring to fig. 6, the diffusion barrier layer 200 plays a role of diffusion barrier in the process of diffusing metal atoms in the metal material layer 300 into the semiconductor contact layer 110, so as to reduce the number of metal atoms entering the semiconductor contact layer at the same time. As an example, the thickness of the diffusion barrier layer 200 may be set to 1nm to 3nm.
In particular, the diffusion barrier layer 200 is tightly structured, thereby having a diffusion barrier effect. On the other hand, the reaction temperature of the diffusion barrier layer 200 and the metal material layer 300 is greater than the reaction temperature of the metal material layer 300 and the semiconductor contact layer 110, so that the diffusion barrier layer 200 does not react at the same time and keeps the performance stable when the metal material layer 300 and the semiconductor contact layer 110 are annealed to generate the contact structure 400.
As an example, the diffusion barrier layer 200 may include graphene and/or tantalum. Graphene (Graphene) is an ideal two-dimensional crystal formed by hexagonal close packing of single-layer carbon atoms. The diffusion barrier layer 200 may include one or more layers of graphene so that metal atoms may be well diffusion blocked such that the movement speeds of metal atoms through the graphene layers tend to be uniform. Tantalum is also relatively compact in structure, so that it also provides a good diffusion barrier for metal atoms. Meanwhile, the temperature at which graphene and/or tantalum react with the metal material layer 300 is relatively high (e.g., graphene reacts with cobalt at 800 ℃ to generate CoC, and tantalum reacts with cobalt at 1620 ℃ to generate TaCo), so that it is not easy to react at the time of annealing.
In step S13, referring to fig. 7, the metal material layer 300 may include a metal material such as cobalt (Co), nickel (Ni), titanium (Ti), etc. As an example, the thickness of the metal material layer 300 may be set to 10nm to 15nm.
In step S15, referring to fig. 8, the annealing temperature is determined according to the reaction temperature between the metal atoms in the metal material layer 300 and the semiconductor contact layer 110. During the annealing process, the metal atoms in the metal material layer 300 diffuse into the semiconductor contact layer 110 through the diffusion barrier layer, so that the semiconductor contact layer 110 reacts with the metal atoms to form the contact structure 400.
In this embodiment, before the metal material layer 300 is formed, the diffusion barrier layer 200 is formed first, and the ratio of the thickness of the diffusion barrier layer 200 to the thickness of the metal material layer 300 is controlled to be a preset ratio, so that the movement speed of the metal atoms diffused to each position in the semiconductor contact layer 110 in the annealing process can be made to be consistent. The rate of the solid phase reaction is mainly affected by the diffusion of the reaction phase, so that the reaction rate of the semiconductor contact layer 110 and the metal atoms diffused into each position therein tends to be uniform, and thus the contact structure 400 having a uniform thickness can be formed.
It is understood that "the movement speeds of the metal atoms diffused to the positions in the semiconductor contact layer 110 tend to be uniform" herein may mean that the movement speeds of the metal atoms diffused to the positions in the semiconductor contact layer 110 are not much different and are within the same speed range.
The "preset ratio" is herein a ratio at which the thickness uniformity requirement of the contact structure 400 can be achieved.
In one embodiment, the diffusion barrier layer 200 may be provided with a melting point higher than that of the metal material layer 300.
At this time, by selecting a material film layer having a higher melting point than the metal material layer 300 as the barrier diffusion layer 200, diffusion of metal atoms in the metal material layer 300 in the barrier diffusion layer 200 can be more favorably promoted.
In one embodiment, the preset ratio is 1 or more: 10, i.e., the ratio of the thickness of the diffusion barrier layer to the thickness of the metal material layer 300 is 1 or more: 10.
when the ratio of the thickness of the diffusion barrier layer 200 to the thickness of the metal material layer 300 is less than 1: at 10, the diffusion barrier 200 is thinner. At this time, the diffusion barrier layer 200 has poor diffusion blocking effect, so that the uniformity of the movement speed of the metal atoms diffused to each position in the semiconductor contact layer 110 is poor, and thus the uniformity of the film thickness of the finally formed contact structure 400 is poor.
Therefore, the present embodiment sets the ratio of the thicknesses of the metal material layers 300 to 1 or more: 10, the uniformity of the film thickness of the contact structure 400 can be effectively ensured.
In one embodiment, the preset ratio is 1 or more: 10 and less than or equal to 1:7.
when the ratio of the thickness of the diffusion barrier layer 200 to the thickness of the metal material layer 300 is greater than 1: at 7, the diffusion barrier 200 is thicker. At this time, the diffusion barrier effect of the diffusion barrier layer 200 is strong, and it may occur that the semiconductor contact layer 110 and the metal atoms diffused therein should have a slow rate, so that the thickness of the contact structure 400 formed at the annealing time is small and does not reach the desired thickness.
Therefore, the present embodiment can ensure that the thickness of the contact structure 400 easily reaches the desired thickness while ensuring the uniformity of the film thickness of the contact structure 400.
In one embodiment, step S11 includes:
step S111, forming an interconnection contact hole on the substrate 100;
step S112, filling the semiconductor contact material layer in the interconnection contact hole;
in step S113, the semiconductor contact material layer on top of the interconnection contact hole is etched back, and the remaining semiconductor contact material layer forms the semiconductor contact layer 110.
In step S111, the interconnection contact hole may be, for example, a capacitor contact hole or a bit line contact hole.
Specifically, referring to fig. 5 and fig. 3, the interconnection contact hole may be a capacitor contact hole. In performing the fabrication of the memory device array region, after the formation of the bit line structures 500, a capacitive contact hole may be formed between the bit line structures 500.
Alternatively, the interconnect contact hole may be a bit line contact hole. In performing the fabrication of the memory device array region, bit line contact holes need to be formed in the formation of the bit line structure 500.
In step S112, the semiconductor contact material layer may be, for example, a polysilicon material layer. The layer of semiconductor contact material may be filled in the interconnect contact holes by deposition or the like,
in step S113, the semiconductor contact layer 110 may be, for example, the first polysilicon 10 partially filled in the capacitor contact hole.
After the first polysilicon 10 is partially filled in the capacitor contact hole, a metal may be formed on the first polysilicon 10, thereby electrically connecting the transistor drain region (or source region) and the capacitor structure in the memory cell. At this time, the semiconductor contact layer 110 may be the first polysilicon 10 filled in the capacitor contact hole.
Alternatively, the semiconductor contact layer 110 may be, for example, the second polysilicon 20 partially filled in the bit line contact hole.
The second polysilicon 20 is filled in the bit line contact hole to electrically connect the source region (or drain region) of the transistor in the memory cell. Thereafter, a bit line metal may be formed on the second polysilicon 20 within the bit line contact hole.
In one embodiment, step S113 etches the top hole wall of the interconnect contact hole to enlarge the interconnect contact hole aperture while etching back the semiconductor contact material layer on top of the interconnect contact hole.
At this time, the interconnection contact hole may be, for example, a capacitor contact hole. After the top hole wall of the capacitor contact hole is etched, the top hole diameter is larger than the hole diameter of the bottom of the filled semiconductor contact layer 110 (the first polysilicon 10).
And after the back etching is carried out on the semiconductor contact material layer at the top of the interconnection contact hole, the surface of the formed semiconductor contact layer is concave or convex.
Specifically, as an example, when the semiconductor contact material layer on top of the interconnection contact hole is etched back, the ratio of gases in the etching gas may be adjusted to form the semiconductor contact layer 110 having a concave or convex surface.
For example, when the semiconductor contact material layer is a polysilicon material layer, the etching gas may be C 2 F 6 And CH (CH) 2 F 2 Is a mixed gas of (a) and (b). By adjusting CH 2 F 2 The gas content of (2) may control the surface topography of the semiconductor contact layer 110 formed after etching.
Alternatively, as another example, the semiconductor contact layer 110 may be subjected to an angled ion implantation process prior to back etching the semiconductor contact material layer on top of the interconnect contact hole, thereby doping the semiconductor contact material layer near the hole wall. The doped semiconductor contact material layer will etch faster, thereby forming a surface-raised semiconductor contact layer 110.
Meanwhile, in an embodiment, after step S16, it may further include:
in step S17, a metal filling layer is formed on the surface of the contact structure 400.
Specifically, the metal fill layer may fill up interconnect contact holes (e.g., capacitor contact holes).
In this embodiment, since the surface of the semiconductor contact layer 110 is convex or concave, the surface of the contact structure 400 formed on the surface layer of the semiconductor contact layer 110 is convex or concave, so that the contact area between the contact structure 400 and the metal filling layer can be effectively increased, and the contact resistance between the contact structure and the metal filling layer can be reduced.
In other embodiments, the semiconductor contact layer 110 and the interconnect contact hole may take other forms. For example, referring to fig. 4, the semiconductor contact layer 110 may be a source region and/or a drain region of a peripheral circuit transistor. The interconnect contact hole 100a may extend from above the semiconductor contact layer 110 (i.e., the source and/or drain regions of the peripheral circuit transistor) to the semiconductor contact layer 110. At this time, the semiconductor contact layer 110 may be located under the interconnection contact hole 100 a.
In particular, referring to fig. 4, in a memory device peripheral circuit, peripheral circuit transistors are covered by a dielectric layer 600. Dielectric layer 600 may include multiple layers of different or the same materials formed in multiple process steps. Meanwhile, an interconnection contact hole may be formed in the dielectric layer 600. The interconnect contact hole penetrates to the semiconductor contact layer 110. The interconnect contact holes may be filled with metal conductive plugs so that the source and/or drain regions of the peripheral circuit transistors may be electrically connected to conductive traces on dielectric layer 600.
Referring to fig. 6, when the semiconductor contact layer 110 is located in the interconnect contact hole 100a, a diffusion barrier layer 200 may be formed on the sidewalls of the remaining portion of the interconnect contact hole 100a and the surface of the semiconductor contact layer 110. Referring to fig. 4, when the semiconductor contact layer 110 is located under the interconnection contact hole 100a, a diffusion barrier layer 200 may be formed on the entire sidewall of the interconnection contact hole 100a and the exposed surface of the semiconductor contact layer 110.
In one embodiment, step S12 includes:
a diffusion barrier material is deposited within the interconnect contact hole to form a diffusion barrier layer on sidewalls of the interconnect contact hole and on a surface of the semiconductor contact layer.
At this time, the diffusion barrier layer 200 is formed on the side wall of the interconnection contact hole 100a and the surface of the semiconductor contact layer 110 at the same time, so that the diffusion barrier layer 200 can cover the bottom surface and the side surface of the metal material layer 300 formed later. At this time, the metal atoms in the metal material layer 300 can be prevented from entering the semiconductor contact layer 110 from the side, so that the concentration of the metal atoms on both sides of the semiconductor contact layer 110 is high, and the uniformity of the film thickness of the formed contact structure 400 is prevented.
In one embodiment, the diffusion barrier layer 200 is formed by atomic layer deposition or chemical vapor deposition.
The film layer formed by the atomic layer deposition mode or the chemical vapor deposition mode has good coverage.
In order to ensure that metal atoms in the metal material layer 300 can still pass through the diffusion barrier layer 200 to react with the semiconductor contact layer 110 after being diffusion-blocked by the diffusion barrier layer 200, the thickness of the diffusion barrier layer 200 should not be too thick.
At this time, the diffusion barrier layer 200 is formed by atomic layer deposition or chemical vapor deposition, so that the diffusion barrier layer 200 with a smaller thickness can be ensured to well cover the semiconductor contact layer 110, thereby playing a good role in diffusion barrier. Therefore, the present embodiment can further ensure uniformity of the contact structure 400 on the surface of the semiconductor contact layer 110.
After that, as an example, the metal material layer 300 may be formed by physical vapor deposition (e.g., magnetron sputtering). The metal material layer 300 is formed on the upper surface of the diffusion barrier 200 by physical vapor deposition, but hardly forms the sidewall.
Of course, the metal material layer 300 may be formed by other methods, such as electroplating. At this time, the metal material layer 300 is formed on the upper surface and the sidewall of the diffusion barrier layer 200.
In one embodiment, the material of the semiconductor contact layer comprises silicon and the material of the metal material layer comprises cobalt.
Referring to fig. 10, step S15 performs an annealing process, including:
step S153, heating the substrate 100 and the film layer formed thereon to a first preset temperature, wherein the first preset temperature is 400-450 ℃;
step S154, maintaining the first preset time at the first preset temperature, wherein the first preset time is 1h to 2h.
In step S153, the substrate 100 and the film layer (including the diffusion barrier layer 200 and the metal material layer 300) formed thereon are heated together at a first predetermined temperature.
Meanwhile, since the diffusion barrier layer 200 is formed before the metal material layer 300 is formed. The diffusion barrier layer 200 plays a role of diffusion barrier in the process of diffusing metal atoms in the metal material layer 300 into the semiconductor contact layer 110, and reduces the number of metal atoms entering the semiconductor contact layer at the same time, thereby effectively reducing the effective concentration Δh of the solid phase reaction.
In the solid phase reaction system, the gibbs free energy Δg is directly related to the effective concentration Δh of the solid phase reaction. Specifically, the following formula:
△G＝△H-T△S；
wherein Δs is negligible in the solid state reaction of the ordered system.
Thus, a decrease in the effective concentration Δh of the solid phase reaction may result in a decrease in the gibbs free energy Δg. Thus, the temperature required for the reaction to form the final phase can be effectively reduced.
In the conventional case of direct contact reaction of silicon with cobalt, annealing at around 700 ℃ is required to produce the final phase CoSi with low resistance 2 . In the present embodiment, however, the effective concentration Δh of the solid phase reaction is reduced due to the arrangement of the diffusion barrier layer 200, so that the temperature required for the reaction to form the final phase can be effectively reduced.
Therefore, the first preset temperature is set here to 400 ℃ to 450 ℃ lower than the conventional reaction temperature. At this time, it is possible to effectively prevent degradation of structural performance (in the memory array and/or in the peripheral circuits) that has been formed previously on the substrate 100 due to the high annealing temperature during formation of the contact structure 400.
Meanwhile, when the material in the semiconductor contact layer 110 includes silicon, the contact structure includes metal silicide. At this time, the relatively low annealing temperature may effectively inhibit silicon in the semiconductor contact layer 110 from diffusing through the diffusion barrier layer 200 to the metal material layer 300.
In the metal silicide reaction, metal atoms and silicon atoms are inter-diffused. The diffusion rate of silicon is greater than the diffusion rate of metal atoms. Further, the diffusion speed of silicon atoms at each position in the semiconductor contact layer 110 is different. The diffusion barrier layer 200 in the embodiment of the present application also has the effect of inhibiting the diffusion speed of silicon, so that silicon atoms react with metal atoms at a relatively uniform speed to generate cobalt silicide with a lower resistance value.
In step S154, since the diffusion barrier 200 is disposed to reduce the effective concentration Δh of the solid phase reaction, and the first predetermined temperature is lower than the conventional reaction temperature, the reaction rate of the semiconductor contact layer 110 with the metal atoms in the metal material layer 300 diffused therein is low.
Accordingly, the annealing is performed at the first preset temperature for 1 to 2 hours, so that it is effectively ensured that a sufficiently thick contact structure 400 is obtained.
Of course, in other embodiments, the first preset temperature and the corresponding first preset time may also be different. For example, the first preset temperature may be set to a temperature of about 700 ℃. At this time, the corresponding first preset time may be set relatively short. Alternatively, the first preset temperature may be set between 450 ℃ and 700 ℃, and so on.
In one embodiment, referring to fig. 10, before step S153, the method may further include:
step S151, heating the substrate 100 and the film layer formed thereon to a second preset temperature, wherein the second preset temperature is 250 ℃ to 350 ℃;
step S152, maintaining the second preset time at the second preset temperature for 10S to 20S.
In step S151, the substrate 100 and the film layer (including the diffusion barrier layer 200 and the metal material layer 300) formed thereon are heated together at a second predetermined temperature.
Here, the second preset temperature (250 to 350 ℃) is lower than the first preset temperature (400 to 450 ℃) so as to form a temperature gradient with the first preset temperature. As an example, the second preset temperature may be 300 ℃.
In step S152, the substrate 100 is maintained at the second preset temperature for 10S to 20S, so that the stress on the substrate can be released before the annealing occurs to the solid phase reaction.
Meanwhile, in step S153, the substrate and the film layer formed thereon may be heated from a second preset temperature (250 to 350 ℃) to a first preset temperature (400 to 450 ℃).
In other embodiments, the annealing process may be performed without performing step S151 and step S152, and the substrate 100 and the film layer (including the diffusion barrier layer 200 and the metal material layer 300) formed thereon may be directly heated at the first preset temperature and maintained at the first preset temperature for the first preset time.
In one embodiment, referring to fig. 2, before the annealing treatment in step S15, the method further includes:
in step S14, a passivation layer 700 is formed on the metal material layer 300, please refer to fig. 7.
The protective layer 700 may include, but is not limited to, a titanium nitride layer. The protective layer 700 may effectively prevent the metal material layer 300 from being oxidized, so that sufficient metal atoms may be provided to react with the semiconductor contact layer 110.
As an example, the thickness of the protective layer 700 may be 5nm to 10nm.
Meanwhile, the protection layer 700 may also be formed by physical vapor deposition (e.g. magnetron sputtering). When the physical vapor deposition is used, the passivation layer 700 is formed on the upper surface of the metal material layer 300, but hardly forms on the sidewall. Of course, the protective layer 700 may be formed by chemical vapor deposition, which is not limited thereto. When the protective layer 700 is formed by chemical vapor deposition, it may be formed on the upper surface of the metal material layer 300 while being formed on the sidewalls of the interconnection contact hole 100a or on the related structures (e.g., the protective barrier 200) on the sidewalls of the interconnection contact hole 100 a.
In one embodiment, referring to fig. 9, after the annealing treatment in step S15, the method further includes:
in step S16, the protection layer 700, the unreacted metal material layer 300 and the diffusion barrier layer 200 are removed.
Specifically, the protective layer 700, the diffusion barrier layer 200, and the unreacted metal material layer 300 may be removed by wet etching or the like.
After removing the removal protection layer 700, the diffusion barrier layer 200, the unreacted metal material layer 300, etc., the contact structure 400 formed under the diffusion barrier layer 200 is exposed. A subsequent process may form a metal layer on the contact structure 400. The metal layer is electrically connected to the semiconductor contact layer 110 through the contact structure 400, thereby effectively reducing the resistance therebetween.
In one embodiment, the semiconductor contact layer 110 has a surface with a concave-convex structure. The relief structure may comprise a concave-down structure and/or a convex-up structure.
Specifically, for example, the surface of the semiconductor contact layer 110 may be recessed downward, thereby forming a recessed structure. Alternatively, the surface of the semiconductor contact layer 110 may be raised upward to form a raised structure. Alternatively, the surface of the semiconductor contact layer 110 may be formed into a zigzag or wavy shape by forming a concave structure and a convex structure.
At this time, by providing the surface of the semiconductor contact layer 110 with a concave-convex structure, the contact structure 400 having a concave-convex structure can be formed on the surface of the semiconductor contact layer 110. The concave-convex surface of the contact structure 400 can effectively increase the contact area, thereby effectively reducing the contact resistance.
In one embodiment, a method for fabricating a semiconductor structure is provided, comprising:
step S21, providing a substrate 100, wherein the substrate 100 comprises a capacitor contact hole, and the inside of the capacitor contact hole is partially filled with first polysilicon 10;
step S22, forming a graphene layer and/or a tantalum layer on the surface of the first polysilicon in the capacitor contact hole and the side wall of the capacitor contact hole by a chemical vapor deposition mode or an atomic layer deposition mode;
step S23, forming a cobalt layer on the surface of the graphene layer and/or the tantalum layer;
step S24, forming a titanium nitride layer on the surface of the cobalt layer;
step S251, heating the substrate 100 and the film layer formed thereon to a second preset temperature, wherein the second preset temperature is 250 ℃ to 350 ℃;
step S252, maintaining the second preset time at the second preset temperature, wherein the second preset time is 10S to 20S;
step S253, heating the substrate 100 and the film layer formed thereon from a second preset temperature to a first preset temperature, wherein the first preset temperature is 400 ℃ to 450 ℃;
step S254, maintaining the first preset time at the first preset temperature for 1 to 2 hours to form a cobalt disilicide layer;
and S26, removing the titanium nitride layer, the unreacted cobalt layer and the graphene layer and/or the tantalum layer.
In one embodiment, a method for fabricating a semiconductor structure is provided, comprising:
step S31, providing a substrate 100, wherein the substrate 100 comprises a bit line contact hole, and the inside of the bit line contact hole is partially filled with a second polysilicon 20;
step S32, forming a graphene layer and/or a tantalum layer on the surface of the second polysilicon 20 in the bit line contact hole and the side wall of the capacitor contact hole by a chemical vapor deposition mode or an atomic layer deposition mode;
step S33, forming a cobalt layer on the surface of the graphene layer and/or the tantalum layer;
step S34, forming a titanium nitride layer on the surface of the cobalt layer;
step S351, heating the substrate 100 and the film layer formed thereon to a second preset temperature, wherein the second preset temperature is 250 ℃ to 350 ℃;
step S352, maintaining the second preset time at the second preset temperature, wherein the second preset time is 10S to 20S;
step S353, heating the substrate 100 and the film layer formed thereon from a second preset temperature to a first preset temperature, wherein the first preset temperature is 400 ℃ to 450 ℃;
step S354, maintaining the first preset time at the first preset temperature for 1 to 2 hours to form a cobalt disilicide layer;
and step S36, removing the titanium nitride layer, the unreacted cobalt layer and the graphene layer and/or the tantalum layer.
In one embodiment, a method for fabricating a semiconductor structure is provided, comprising:
step S41, providing a base 100, wherein the base 100 comprises a silicon substrate, a transistor is formed on the basis of the silicon substrate, a source region and a drain region of the transistor are formed by heavily doping the silicon substrate, and interconnection contact holes are formed on the source region and the drain region of the transistor;
step S42, forming a graphene layer and/or a tantalum layer on the side wall of the interconnection contact hole and the surfaces of the source region and the drain region exposed by the interconnection contact hole by a chemical vapor deposition mode or an atomic layer deposition mode;
step S43, forming a cobalt layer on the surface of the graphene layer and/or the tantalum layer;
step S44, forming a titanium nitride layer on the surface of the cobalt layer;
step S451, heating the substrate 100 and the film layer formed thereon to a second preset temperature, wherein the second preset temperature is 250 ℃ to 350 ℃;
step S452, maintaining the second preset time at the second preset temperature, wherein the second preset time is 10S to 20S;
step S453, heating the substrate 100 and the film layer formed thereon from a second preset temperature to a first preset temperature, wherein the first preset temperature is 400-450 ℃;
step S454, maintaining the first preset time at the first preset temperature for 1-2 h to form a cobalt disilicide layer;
and step S46, removing the titanium nitride layer, the unreacted cobalt layer and the graphene layer and/or the tantalum layer.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, a semiconductor structure is also provided, the semiconductor structure including a substrate 100 and a contact structure 400. The substrate 100 includes a semiconductor contact layer 110. The contact structure 400 is formed on the semiconductor contact layer 110 according to any of the methods described above.
The base 100 may specifically comprise a semiconductor substrate. The semiconductor substrate is provided with an array region and a peripheral circuit region. The array region is used to form a memory array. The peripheral circuit region is used for forming a peripheral circuit. The peripheral circuitry may control the memory array. The memory array may include transistors in peripheral circuits.
The base 100 may also include structures (including array region structures, peripheral circuit region structures, and the like) formed in or over the semiconductor substrate. The semiconductor substrate includes, but is not limited to, a silicon substrate. It may also be a germanium substrate, or a silicon germanium substrate, for example.
Specifically, a shallow trench isolation structure (Shallow Trench Isolation, STI for short) may be formed in the semiconductor substrate, and the shallow trench isolation structure may isolate a plurality of Active areas (AA for short) arranged at intervals in the substrate.
The active region may include a P-type active region or an N-type active region. The P-type active region may form an N-type transistor (e.g., NMOS), and the P-type active region may be formed by implanting N-type ions to form source and drain regions of the N-type transistor. The N-type active region may form a P-type transistor (e.g., PMOS), and the N-type active region may be formed by implanting P-type ions to form source and drain regions of the P-type transistor. The array region and the peripheral circuit region may each form a transistor.
The source region and the drain region of the transistor of the array region may be respectively connected to the second polysilicon in the bit line contact hole and the first polysilicon in the capacitor contact hole. Conductive contact holes may be formed on the source and drain regions of the transistors of the peripheral circuit region.
The semiconductor contact layer 110 may be a film layer for conducting connection formed based on a heavily doped semiconductor material.
By way of example, the semiconductor contact layer 110 may be part of a semiconductor substrate, such as a source region and/or a drain region of a transistor formed within the semiconductor substrate. Alternatively, the semiconductor contact layer 110 may be a polysilicon layer or the like formed on the semiconductor substrate.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (13)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming a semiconductor contact layer on the substrate;
forming a diffusion barrier layer on the semiconductor contact layer;
forming a metal material layer on the diffusion barrier layer, wherein the metal material layer contains metal atoms;
annealing treatment is carried out so that the metal atoms diffuse into the semiconductor contact layer through the diffusion barrier layer and react with the diffusion barrier layer to generate a contact structure;
wherein the ratio of the thickness of the diffusion barrier layer to the thickness of the metal material layer is a preset ratio.
2. The method of claim 1, wherein the diffusion barrier layer has a melting point higher than a melting point of the metal material layer.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein the diffusion barrier layer comprises graphene and/or tantalum and the metal material layer comprises cobalt.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein the predetermined ratio is 1 or more: 10 and less than or equal to 1:7.
5. the method of manufacturing a semiconductor structure as claimed in claim 1, wherein,
the forming a semiconductor contact layer on the substrate includes:
forming an interconnection contact hole on the substrate;
filling a semiconductor contact material layer in the interconnection contact hole;
and carrying out back etching on the semiconductor contact material layer at the top of the interconnection contact hole, and forming the semiconductor contact layer by the remained semiconductor contact material layer.
6. The method of claim 5, wherein forming a diffusion barrier layer on the semiconductor contact layer comprises:
and depositing a diffusion barrier material in the interconnection contact hole to form the diffusion barrier layer on the side wall of the interconnection contact hole and the surface of the semiconductor contact layer.
7. The method for manufacturing a semiconductor structure according to claim 5, wherein the etching is performed on the semiconductor contact material layer on top of the interconnection contact hole, and simultaneously etching is performed on a top hole wall of the interconnection contact hole to enlarge the aperture of the interconnection contact hole, and after the etching is performed on the semiconductor contact material layer on top of the interconnection contact hole, the surface of the formed semiconductor contact layer is concave or convex;
after the contact structure is generated, the method further comprises:
and forming a metal filling layer on the surface of the contact structure.
8. The method of any of claims 1-7, wherein the semiconductor contact layer material comprises silicon, and wherein the annealing comprises:
heating the substrate and a film layer formed on the substrate to a first preset temperature, wherein the first preset temperature is 400-450 ℃;
maintaining the first preset time at a first preset temperature, wherein the first preset time is 1-2 h.
9. The method of manufacturing a semiconductor structure as claimed in claim 8, wherein,
the heating the substrate to a first preset temperature is preceded by:
heating the substrate and the film layer formed on the substrate to a second preset temperature, wherein the second preset temperature is 250-350 ℃;
maintaining the second preset time at a second preset temperature for 10s to 20s;
the heating the substrate and the film layer formed thereon to a first preset temperature includes:
and heating the substrate and the film layer formed on the substrate from a second preset temperature to the first preset temperature.
10. The method of any one of claims 1-7, further comprising, after forming a metal material layer on the diffusion barrier layer, prior to annealing:
and forming a protective layer on the metal material layer.
11. The method of claim 10, wherein the protective layer comprises a titanium nitride layer, and wherein the protective layer has a thickness of 5nm to 10nm.
12. The method of fabricating a semiconductor structure of claim 10, further comprising, after the annealing:
and removing the protective layer, the unreacted metal material layer and the diffusion barrier layer.
13. A semiconductor structure, comprising:
a substrate;
a semiconductor contact layer on the substrate;
a contact structure formed on the semiconductor contact layer according to the method of any one of claims 1-12.
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| CN202211102389.1A CN117712028A (en) | 2022-09-09 | 2022-09-09 | Semiconductor structure and preparation method thereof |
| PCT/CN2022/124313 WO2024050914A1 (en) | 2022-09-09 | 2022-10-10 | Semiconductor structure and preparation method therefor |
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| US6468900B1 (en) * | 2000-12-06 | 2002-10-22 | Advanced Micro Devices, Inc. | Dual layer nickel deposition using a cobalt barrier to reduce surface roughness at silicide/junction interface |
| US8531033B2 (en) * | 2009-09-07 | 2013-09-10 | Advanced Interconnect Materials, Llc | Contact plug structure, semiconductor device, and method for forming contact plug |
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