CN117709264A - Channel allocation method and device - Google Patents
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Abstract
The invention discloses a channel allocation method and a device, which relate to the technical field of data communication and solve the problem that connection lines between FPGAs in the prior art are unreasonably allocated; the method comprises the following steps: initializing the number of connecting lines among FPGAs in user design, determining first time delays of all signals, and calculating first time division multiplexing ratios of all signals according to the first time delays; respectively utilizing the first time delay of each signal to obtain an allocation result; determining the signals transmitted in the same direction as a group by using the distribution result, and determining the maximum time division multiplexing ratio of each group; updating the first time division multiplexing ratio of each signal in the same group by using the maximum time division multiplexing ratio, and updating the corresponding first time delay according to the updated first time division multiplexing ratio; cycling the steps until the cycle times are equal to a set first threshold value, and outputting an allocation result; under the condition of determining the calculated amount, the time division multiplexing ratio is balanced, so that the signal transmission is fast based on meeting the criticality.
Description
Technical Field
The present invention relates to the field of data communications technologies, and in particular, to a channel allocation method and apparatus.
Background
In order to perform functional verification on a user design, the design has to be divided into a plurality of parts, each part is distributed to each logic array in a verification system to operate respectively, verification systems formed by a plurality of logic arrays are connected and communicated through interconnection lines, and the interconnection lines transmit signals among the logic arrays, so that compared with internal circuits of the logic arrays, the time delay is much larger. However, the interconnection resources between the logic arrays are very limited, and the number of signals to be transmitted between the logic arrays is often far greater than the number of interconnection lines, so that a TDM (time division multiplexing) mode is required to enable a plurality of signals to share one interconnection line and be transmitted in turn in different time slices. The signal will obtain extra delay through the TDM module, the higher the time division multiplexing proportion, the larger the delay amount, the delay size of a signal has a fixed formula correlation with the TDM type and the time division multiplexing proportion used by the signal.
The system for prototype verification has a fixed networking structure, i.e. the connection relationship between the logic arrays presents a certain topology, the user designed circuits allocated in different logic arrays may have communication signals, the path of the signals from the driving node to the load node in the networking is called routing path, the process of finding the path is called routing, the channel allocation method herein is based on the routing process having ended, i.e. any pair of two logic arrays with interconnection lines connected, the signals between them being clear.
The method in the prior art is to calculate the TDM Ratio aiming at the local part of a pair of logic arrays, namely only consider the TDM Ratio of the signals when passing through a pair of logic arrays, and the delay condition of each signal on the whole routing path cannot be accurately estimated from the global angle, so that the Ratio distribution is unreasonable;
the existing method adopts an average method to calculate the TDM Ratio of all signals, namely the total number of signals divided by the total number of interconnecting wires, and the method is too extensive, namely each signal is considered as equivalent, the time sequence difference of each signal is ignored, namely some insignificant signals can tolerate larger delay, and some insignificant signals cannot tolerate.
Disclosure of Invention
The invention solves the problem that the distribution of connecting lines between FPGAs is unreasonable because the analysis of signal time delay cannot be carried out from the global angle in the prior art by providing the channel distribution method and the channel distribution device, and realizes that the time delay of signals is considered from the global angle under the condition of determining the calculated quantity, so that the time division multiplexing ratio is balanced, and the signals are transmitted quickly on the basis of meeting the criticality.
In a first aspect, the present invention provides a method of channel allocation, the method comprising:
initializing the number of connecting lines between FPGA in user design, determining first time delay of each signal, and calculating first time division multiplexing ratio corresponding to each signal according to the first time delay;
distributing connecting lines among a plurality of FPGAs on the transmission paths of the signals by using the first time delay of the signals respectively to obtain a distribution result;
determining the signals transmitted in the same direction as a group by utilizing the distribution result, and determining the maximum time division multiplexing ratio of each group of signals according to the grouping result;
updating the first time division multiplexing ratio of each signal in the same group by using the maximum time division multiplexing ratio, and updating the corresponding first time delay according to the updated first time division multiplexing ratio;
and cycling the steps until the cycling times are equal to a set first threshold value, and outputting the distribution result.
With reference to the first aspect, in one possible implementation manner, the determining a first delay of each signal specifically includes:
determining a driving node and a load node of each signal;
and determining the number of the FPGAs between the driving node and the load node as a first time delay.
With reference to the first aspect, in one possible implementation manner, before updating the first time division multiplexing ratio of each signal in the same group with the maximum time division multiplexing ratio, the method further includes:
checking validity of the updated first time division multiplexing ratio;
if the updated first time division multiplexing ratio is legal, updating the first time division multiplexing ratio of each signal in the same group;
if the updated first time division multiplexing ratio is illegal, calculating the first time division multiplexing ratio of each signal in the same group, and uniformly adjusting the first time division multiplexing ratio of each signal.
With reference to the first aspect, in a possible implementation manner, the updating, with the maximum time division multiplexing ratio, a first time division multiplexing ratio of each signal in the same group includes:
calculating a second time division multiplexing ratio of each signal in the same group according to the maximum time division multiplexing ratio;
rounding the second time division multiplexing ratio to obtain a rounded second time division multiplexing ratio;
and updating the first time division multiplexing ratio of each signal in the same group according to the second time division multiplexing ratio.
With reference to the first aspect, in one possible implementation manner, the specific calculation formula for obtaining the allocation result is expressed as:
wire X ＝Wire_Sum-wire Y
wherein wire is Y Representing the number of connecting lines from the first FPGA to the second FPGA between the two FPGAs; wire (wire) X Representing the number of connecting lines from the second FPGA to the first FPGA between the two FPGAs; signal_Sum represents the number of all signals between two FPGAs; signal_Y represents the Signal from the second FPGA to the first FPGA between the two FPGAs; delay_sum i A representation; delay_sum j A representation; wire Sum represents the total number of connection lines between two FPGAs.
With reference to the first aspect, in one possible implementation manner, the updating, with the maximum time division multiplexing ratio, a first time division multiplexing ratio of each signal in the same group is specifically expressed as:
wherein tdmratioiold represents the first time division multiplexing ratio obtained in the previous cycle; delay_sum_y_max represents the maximum first Delay in the homodromous signal; delay_sum_y_i represents the same direction signal.
With reference to the first aspect, in one possible implementation manner, the updating, by using the maximum time division multiplexing ratio, a first time division multiplexing ratio of each signal in the same group, and updating, according to the updated first time division multiplexing ratio, a corresponding first delay, further includes:
and updating the first time division multiplexing ratio of the first signal in the same group by using the maximum time division multiplexing ratio, and updating the first time division multiplexing ratio of the second signal in the same group according to the first time division multiplexing ratio until the first time division multiplexing ratio of each information in the same group is updated.
In a second aspect, the present invention provides an apparatus for channel allocation, the apparatus comprising:
the initialization module is used for initializing the number of connecting wires between the FPGA in the user design, determining the first time delay of each signal, and calculating the first time division multiplexing ratio corresponding to each signal according to the first time delay;
the distribution module is used for distributing connecting wires among the plurality of FPGAs on the transmission paths of the signals by utilizing the first time delay of the signals respectively to obtain a distribution result;
the comparison module is used for determining the signals transmitted in the same direction as a group by utilizing the distribution result and determining the maximum time division multiplexing ratio of each group of signals according to the grouping result;
the updating module is used for updating the first time division multiplexing ratio of each signal in the same group by utilizing the maximum time division multiplexing ratio and updating the corresponding first time delay according to the updated first time division multiplexing ratio;
and the output module is used for cycling the steps until the cycle times are equal to a set first threshold value and outputting the distribution result.
In a third aspect, the present invention provides a server for channel allocation, the server comprising a memory and a processor;
the memory is used for storing computer executable instructions;
the processor is configured to execute the computer-executable instructions to implement a method of channel allocation.
In a fourth aspect, the present invention provides a computer-readable storage medium having executable instructions that when executed by a computer enable a method of channel allocation.
One or more technical schemes provided by the invention have at least the following technical effects or advantages:
(1) According to the updating and iteration of each round, under the condition that the number of connecting lines is fixed, the time division multiplexing ratio of each signal between two adjacent FPGA on the transmission path is basically the same, so that the overall transmission rate of the signal is quickened, and the time division multiplexing ratio can be adjusted according to the time sequence criticality difference;
(2) From the global point of view, the delay condition of each signal on the distribution path is estimated, so that the time division multiplexing ratio is more reasonable;
(3) The iteration process is controllable, and the debugging flexibility is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments of the present invention or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart illustrating steps of a method for channel allocation according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a serial real-time update Delay_Sum according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The number of signals passing between any pair of FPGAs with physical connection in the networking of the verification system, the directions of the signals and the number of signals in different directions are determined, and TDMs which can be used between the FPGAs are determined. Therefore, it is needless to say that a certain pair of FPGAs is Fx and Fy, the total number of signals between them is signal_sum, the number of directions from Fx to Fy is signal_y, and the number of directions from Fy to Fx is signal_x, and it is easy to see: signal_sum=signal_x+signal_y, and the total number of physical links between the pair of FPGAs is wire_num.
The output result of channel allocation will be how many wires are used for wire_y from X to Y between any pair of FPGAs with physical connection, and how many wires are used for wire_x from Y to X, so as to calculate the time division multiplexing ratio of each signal between Fx and Fy.
The present invention provides a channel allocation method, as shown in fig. 1, which includes the following steps S101 to S105.
S101, initializing the number of connecting lines among FPGAs in user design, determining first time delays of all signals, and calculating first time division multiplexing ratios corresponding to all signals according to the first time delays.
Specifically, in step S101, a first delay of each signal is determined, specifically including the following steps.
(1) The drive node and load node of each signal are determined.
(2) And determining the number of the FPGAs between the driving node and the load node as a first time delay.
The first channel allocation result is initialized, the hop number of each signal in the verification system, that is, the number of FPGAs required to pass from the driving node to the load node is calculated, and the hop number is taken as an initial Delay value.
This Delay is a relative concept that does not necessarily represent the actual length of time at any time, and the Delay value of one signal will be compared with the Delay value of the other signal during the next iteration (Delay is the Delay of the signal, which is related to the length of the signal path, whether it crosses the FPGA, and how much combinational logic it passes). The TDM Ratio of each other is determined according to the actual wire number.
Therefore Delay is a relative concept, so in the initialization process, hop is also possible as the initial Delay, because the true Delay time length is not available without channel allocation. Meanwhile, the TDM Ratio of each signal passing between corresponding FPGAs is:
s102, distributing connecting lines among a plurality of FPGAs on the transmission paths of the signals by using the first time delay of the signals respectively to obtain a distribution result.
Specifically, a specific calculation formula for obtaining the allocation result is expressed as:
wire X ＝Wire_Sum-wire Y
wherein wire is Y Representing the number of connecting lines from the first FPGA to the second FPGA between the two FPGAs; wire (wire) X Representing the number of connecting lines from the second FPGA to the first FPGA between the two FPGAs; signal_Sum represents the number of all signals between two FPGAs; signal_Y represents the Signal from the second FPGA to the first FPGA between the two FPGAs; delay_sum i A representation; delay_sum j A representation; wire Sum represents the total number of connection lines between two FPGAs.
Illustratively, delay_sum, of each signal according to the previous round, represents the total Delay of the signal from the drive node to the load node. And carrying out channel allocation on each FPGA pair with physical connection. And calculating connecting lines in the front two directions from the second FPGA to the first FPGA according to the formula. The number of channel assignments is proportional to the Sum of the Delay Sum of the same-direction signals in the Sum of the Delay Sum of the two-direction signals. The purpose of this is to split the wire into two directions according to the total delay of the signal, the greater the total delay, the more wires it will be to say it will need to reduce the average delay of the individual signals.
Illustratively, in step S102, the first delay is used to allocate the connection between the two FPGAs, instead of allocating the connection between the two FPGAs using the degree of timing.
The delay_sum is changed into a time sequence critical degree, because the requirement of the setup time is more important and common in the scene of the cross-FPGA signal, the time sequence critical degree is related to the setup time allowance setup_slice of the signal, the process of allocating connection lines is actually to measure the requirement degree of one signal for a channel, and the emergency degree is also called urgent level, and when the setup_slice is smaller than other signals, the emergency degree is higher, and the setup_slice can be negative. The higher the degree of urgency the smaller its TDM Ratio will be allocated, since the greater the TDM Ratio the greater the delay created.
S103, determining the signals transmitted in the same direction as a group by using the distribution result, and determining the maximum time division multiplexing ratio of each group of signals according to the grouping result.
For example, for signal_y signals in one direction, each Signal is numbered i, i e [1, signal_y ], each Signal has a delay_sum_y_i, and the largest delay_sum_y_max is taken.
S104, updating the first time division multiplexing ratio of each signal in the same group by using the maximum time division multiplexing ratio, and updating the corresponding first time delay according to the updated first time division multiplexing ratio.
Specifically, in step S104, the method further includes: and updating the first time division multiplexing ratio of the first signal in the same group by using the maximum time division multiplexing ratio, and updating the first time division multiplexing ratio of the second signal in the same group according to the first time division multiplexing ratio until the first time division multiplexing ratio of each information in the same group is updated.
Specifically, in step S104, the first time division multiplexing ratio of each signal in the same group is updated by using the maximum time division multiplexing ratio, specifically expressed as:
wherein tdmratioiold represents the first time division multiplexing ratio obtained in the previous cycle; delay_sum_y_max represents the maximum first Delay in the homodromous signal; delay_sum_y_i represents the same direction signal.
Specifically, in step S104, the first time division multiplexing ratio of each signal in the same group is updated with the maximum time division multiplexing ratio, including the following steps S1041 to S1043.
S1041, calculating a second time division multiplexing ratio of each signal in the same group according to the maximum time division multiplexing ratio.
S1042, rounding the second time division multiplexing ratio to obtain a rounded second time division multiplexing ratio.
And S1043, updating the first time division multiplexing ratio of each signal in the same group according to the second time division multiplexing ratio.
Specifically, in step S1041, after obtaining the second time division multiplexing ratio, it includes:
(1) The validity of the second time division multiplexing ratio is checked.
(2) If the second time division multiplexing ratio is legal, the first time division multiplexing ratio of each signal in the same group is updated.
(3) If the second time division multiplexing ratio is illegal, calculating the first time division multiplexing ratio of each signal in the same group, and uniformly adjusting the first time division multiplexing ratio of each signal.
Illustratively, after obtaining a New TDM Ratio New for each signal, the TDM Ratio New is checked for validity. TDM Ratio New is a relative quantity, that is to say, used in comparison between the individual signals, and is not an absolute quantity that is completely legal. Therefore, the number of wires required under the existing TDM Ratio New setting is calculated:
further, if wire_need_y is greater than actual wire_y, the tdm_ratio of each signal needs to be adjusted up by the same Ratio. The specific up-regulation ratio is expressed as:
for example, the tdmrationnew of each signal is incrementally changed, that is, TDM Ratio new=tdm_ratio+min_step, and min_step is determined according to TDM ip, so that wire_new_y is equal to or less than actual wire_y.
S105, cycling the steps until the cycle times are equal to the set first threshold value, and outputting the distribution result.
Illustratively, the delay_sum of each signal is updated according to the calculation formulas of TDM and Delay, and then the next iteration is performed until a specified max Delay requirement or a specified number of iterations is reached. After the iteration is completed, a rounding operation needs to be performed on the TDM Ratio, and because the TDM Ratio in the iteration process may be a decimal, the method may be to round the TDM Ratio to a legal Ratio value, where the legal Ratio value is generally a specified multiple of a certain positive integer. And then, calculating whether the Wire New exceeds the real Wire quantity according to a formula, if so, increasing the Ratio to a higher legal Ratio, and reducing the Wire demand.
In another embodiment provided by the present invention, in the steps S101 to S105, the signal delay_sum is kept constant throughout the current iteration, so as to allocate channels in parallel in each FPGA pair, which is fast, but affects the accuracy, and is prone to overregulation. In this embodiment, after step S102, delay_sum is updated, and the updated delay_sum is used as input of other FPGA cross during channel allocation in this round of iteration.
For example, as shown in fig. 2, if a signal needs to cross 3 FPGA cross times to arrive, if each FPGA cross is based on the original total Delay d_sum_o, if d_sum_o is relatively small, the existing method will increase Delay in each FPGA cross, so that the adjustment is excessive, and after this round of iteration, d_sum is too large.
The improvement method is that the parallel is changed into serial, and the delay_sum is updated immediately after the channel of each FPGA cross is distributed on the signal path, and is used as the input of other FPGA cross in the channel distribution in the iteration of the round.
The invention provides a channel distribution device, which comprises: the device comprises an initialization module, an allocation module, a comparison module, an updating module and an output module.
The initialization module is used for initializing the number of connecting wires between the FPGA in the user design, determining the first time delay of each signal, and calculating the first time division multiplexing ratio corresponding to each signal according to the first time delay.
The distribution module is used for distributing connecting lines among the plurality of FPGAs on the transmission paths of the signals by utilizing the first time delay of the signals respectively to obtain distribution results.
And the comparison module is used for determining the signals transmitted in the same direction as a group by utilizing the distribution result and determining the maximum time division multiplexing ratio of each group of signals according to the grouping result.
And the updating module is used for updating the first time division multiplexing ratio of each signal in the same group by utilizing the maximum time division multiplexing ratio and updating the corresponding first time delay according to the updated first time division multiplexing ratio.
And the output module is used for cycling the steps until the cycle times are equal to the set first threshold value and outputting the distribution result.
The apparatus or module set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. For convenience of description, the above devices are described as being functionally divided into various modules, respectively. The functions of the various modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention. Of course, a module that implements a certain function may be implemented by a plurality of sub-modules or a combination of sub-units.
The methods, apparatus or modules described in this invention may be implemented in computer readable program code means and the controller may be implemented in any suitable way, for example, the controller may take the form of a microprocessor or processor and a computer readable medium storing computer readable program code (e.g. software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (english: application Specific Integrated Circuit; abbreviated: ASIC), programmable logic controller and embedded microcontroller, examples of the controller including but not limited to the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller can be regarded as a hardware component, and means for implementing various functions included therein can also be regarded as a structure within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.
Some of the modules of the apparatus of the present invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The invention provides a server for channel allocation, which comprises a memory and a processor; the memory is used for storing computer executable instructions; the processor is configured to execute computer-executable instructions to implement a method of channel allocation.
The invention provides a computer readable storage medium, which has executable instructions, and the method for allocating channels can be realized when the computer executes the executable instructions.
The storage medium includes, but is not limited to, a random access Memory (English: random Access Memory; RAM), a Read-Only Memory (ROM), a Cache Memory (English: cache), a Hard Disk (English: hard Disk Drive; HDD), or a Memory Card (English: memory Card). The memory may be used to store computer program instructions.
Although the invention provides method operational steps as described in the examples or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive labor. The order of steps recited in the present embodiment is only one way of performing the steps in a plurality of steps, and does not represent a unique order of execution. When implemented by an actual device or client product, the method of the present embodiment or the accompanying drawings may be performed sequentially or in parallel (e.g., in a parallel processor or a multithreaded environment).
From the above description of embodiments, it will be apparent to those skilled in the art that the present invention may be implemented in software plus necessary hardware. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product or may be embodied in the implementation of data migration. The computer software product may be stored on a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., comprising instructions for causing a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to perform the methods described in the various embodiments or portions of the embodiments of the invention.
In this specification, each embodiment is described in a progressive manner, and the same or similar parts of each embodiment are referred to each other, and each embodiment is mainly described as a difference from other embodiments. All or portions of the present invention are operational with numerous general purpose or special purpose computer system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the present invention; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A method of channel allocation, comprising:
initializing the number of connecting lines between FPGA in user design, determining first time delay of each signal, and calculating first time division multiplexing ratio corresponding to each signal according to the first time delay;
distributing connecting lines among a plurality of FPGAs on the transmission paths of the signals by using the first time delay of the signals respectively to obtain a distribution result;
determining the signals transmitted in the same direction as a group by utilizing the distribution result, and determining the maximum time division multiplexing ratio of each group of signals according to the grouping result;
updating the first time division multiplexing ratio of each signal in the same group by using the maximum time division multiplexing ratio, and updating the corresponding first time delay according to the updated first time division multiplexing ratio;
and cycling the steps until the cycling times are equal to a set first threshold value, and outputting the distribution result.
2. The method of channel allocation according to claim 1, wherein said determining the first delay of each signal comprises:
determining a driving node and a load node of each signal;
and determining the number of the FPGAs between the driving node and the load node as a first time delay.
3. The method of channel allocation according to claim 1, further comprising, prior to updating the first time division multiplexing ratio of each signal within the same group with the maximum time division multiplexing ratio:
checking validity of the updated first time division multiplexing ratio;
if the updated first time division multiplexing ratio is legal, updating the first time division multiplexing ratio of each signal in the same group;
if the updated first time division multiplexing ratio is illegal, calculating the first time division multiplexing ratio of each signal in the same group, and uniformly adjusting the first time division multiplexing ratio of each signal.
4. The method of channel allocation according to claim 1, wherein said updating a first time division multiplexing ratio of each signal in the same group using said maximum time division multiplexing ratio comprises:
calculating a second time division multiplexing ratio of each signal in the same group according to the maximum time division multiplexing ratio;
rounding the second time division multiplexing ratio to obtain a rounded second time division multiplexing ratio;
and updating the first time division multiplexing ratio of each signal in the same group according to the second time division multiplexing ratio.
5. The method for allocating channels according to claim 1, wherein the specific calculation formula for obtaining the allocation result is expressed as:
wire X ＝Wire_Sum-wire Y
wherein wire is Y Representing the number of connecting lines from the first FPGA to the second FPGA between the two FPGAs; wire (wire) X Representing the number of connecting lines from the second FPGA to the first FPGA between the two FPGAs; signal_Sum represents the number of all signals between two FPGAs; signal_Y represents the Signal from the second FPGA to the first FPGA between the two FPGAs; delay_sum i A representation; delay_sum j A representation; wire Sum represents the total number of connection lines between two FPGAs.
6. The method of channel allocation according to claim 1, wherein said updating the first time division multiplexing ratio of each signal in the same group using said maximum time division multiplexing ratio is formulated as:
wherein TDM ratio represents the first time division multiplexing ratio obtained in the previous cycle; delay_sum_y_max represents the maximum first Delay in the homodromous signal; delay_sum_y_i represents the same direction signal.
7. The method of channel allocation according to claim 1, wherein said updating a first time division multiplexing ratio of each signal in the same group using said maximum time division multiplexing ratio and updating a corresponding first time delay according to said updated first time division multiplexing ratio, further comprises:
and updating the first time division multiplexing ratio of the first signal in the same group by using the maximum time division multiplexing ratio, and updating the first time division multiplexing ratio of the second signal in the same group according to the first time division multiplexing ratio until the first time division multiplexing ratio of each information in the same group is updated.
8. An apparatus for channel allocation, comprising:
the initialization module is used for initializing the number of connecting wires between the FPGA in the user design, determining the first time delay of each signal, and calculating the first time division multiplexing ratio corresponding to each signal according to the first time delay;
the distribution module is used for distributing connecting wires among the plurality of FPGAs on the transmission paths of the signals by utilizing the first time delay of the signals respectively to obtain a distribution result;
the comparison module is used for determining the signals transmitted in the same direction as a group by utilizing the distribution result and determining the maximum time division multiplexing ratio of each group of signals according to the grouping result;
the updating module is used for updating the first time division multiplexing ratio of each signal in the same group by utilizing the maximum time division multiplexing ratio and updating the corresponding first time delay according to the updated first time division multiplexing ratio;
and the output module is used for cycling the steps until the cycle times are equal to a set first threshold value and outputting the distribution result.
9. A server for channel allocation, comprising a memory and a processor;
the memory is used for storing computer executable instructions;
the processor is configured to execute the computer-executable instructions to implement the method of channel allocation of any of claims 1-7.
10. A computer readable storage medium having executable instructions that when executed by a computer enable the method of channel allocation according to any one of claims 1 to 7.
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