CN117709263A - Chip prototype verification method, device, equipment and medium - Google Patents
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Abstract
The application discloses a chip prototype verification method, device, equipment and medium, which are applied to a HAPS prototype verification platform and relate to the technical field of chip verification, and comprise the following steps: modifying the design code of the chip to be verified to adapt to the HAPS prototype verification platform, and setting the constraint corresponding to each design step; determining a key index corresponding to each design step and a preset condition which needs to be met by each key index; executing each design step according to the execution sequence, and judging whether the key index meets the preset condition after executing each design step; if not, the design codes or constraints are adjusted by using a target optimization strategy, iterative optimization is performed until the key indexes meet preset conditions, and if so, the next design step is executed according to the execution sequence. The method and the device judge whether the key indexes meet the preset conditions, and adjust and iterate and optimize based on the optimization strategy when the key indexes do not meet the preset conditions, so that the efficiency and the accuracy of chip prototype verification are improved.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a method, an apparatus, a device, and a medium for chip prototype verification.
Background
With the increasing complexity of large scale integrated circuit designs, chip verification faces significant challenges in terms of capital and time. Early developers want to verify whether the chip design meets the preset, only wait for extremely lengthy simulation results, or wait for streaming results, which once the results are not as expected, whether again simulated or secondary streaming, would incur extremely high costs.
FPGA (Field Programmable Gate Array ) prototype verification verifies the functionality of an ASIC (Application Specific Integrated Circuit )/SoC (System on Chip) by migrating RTL (Register Transfer Level, register transfer level circuit) to the FPGA.
At present, the design of ASICs becomes larger and more complex, a single-chip FPGA cannot meet the prototype verification requirement, and multiple pieces of FPGAs are verified. The HAPS prototype verification platform is a high-performance and high-capacity FPGA-based prototype verification board specially provided for ASIC/SOC designers, the advanced segmentation technology in the industry fully considers the challenges of subsequent FPGA layout and wiring, more convenience is provided for the designers, and development efficiency is improved.
When chip prototype verification is performed through the HAPS prototype verification platform, the segmentation (Partition) of the first stage is a process of continuously trying and iterating continuously to obtain an optimal result, and the Synthesis (Synthesis) of the first stage is also an important factor affecting design performance, so how to improve the success rate and efficiency of the first stage of prototype verification is a problem to be solved in the art.
Disclosure of Invention
In view of the above, the present invention aims to provide a method, an apparatus, a device and a medium for chip prototype verification, which can improve accuracy and efficiency of a first stage of chip prototype verification, and the specific scheme is as follows:
in a first aspect, the present application discloses a chip prototype verification method, applied to a HAPS prototype verification platform, including:
modifying the design code of the chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and setting constraints corresponding to each design step of a target verification stage;
determining target key indexes corresponding to each design step and preset conditions to be met by each target key index;
executing each design step according to the execution sequence, and judging whether the target key index corresponding to each design step meets the preset condition after each design step is executed;
And if the target key index does not meet the preset condition, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step, and performing iterative optimization until the target key index meets the preset condition, and if the target key index meets the preset condition, executing the next design step according to the execution sequence.
Optionally, after each design step is performed, determining whether the target key indicator corresponding to the design step meets the preset condition includes:
after each design step is executed, a corresponding execution report is obtained;
analyzing the execution report, and judging whether the target key index corresponding to the design step meets the preset condition according to an analysis result.
Optionally, the target key indicator includes a resource utilization rate of each piece of field programmable gate array in the field programmable gate array system, a clock crossing number between each piece of field programmable gate array, a high-speed time division multiplexing function ratio, a number of non-wiring networks of each piece of field programmable gate array, a number of through networks of each piece of field programmable gate array, a number of multi-hop paths between each piece of field programmable gate array, an estimated system clock frequency, and a number of unconverted gating clocks.
Optionally, the designing step sequentially includes: design pre-segmentation, design segmentation, field programmable gate array system layout wiring, field programmable gate array system generation and design synthesis.
Optionally, after each design step is performed, determining whether the target key indicator corresponding to the design step meets the preset condition includes:
after the design pre-segmentation is executed, judging whether the resource utilization rate of the field programmable gate array is smaller than a preset resource utilization rate threshold value;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the resource utilization rate of the field programmable gate array is not smaller than the preset resource utilization rate threshold, adjusting the design code by utilizing a target optimization strategy corresponding to the design pre-segmentation.
Optionally, after each design step is performed, determining whether the target key indicator corresponding to the design step meets the preset condition includes:
After the design segmentation is performed, judging whether the resource utilization rate of the field programmable gate array is smaller than the preset resource utilization rate threshold value, whether clock crossing does not exist among all the field programmable gate arrays, whether the current high-speed time division multiplexing function ratio is the smallest high-speed time division multiplexing function ratio in all the high-speed time division multiplexing function ratios, whether no wiring-disabled network exists among all the field programmable gate arrays, and whether the number of the through networks of all the field programmable gate arrays is not larger than the preset through network number threshold value;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the resource utilization rate of the field programmable gate array is not less than the preset resource utilization rate threshold, clock crossing exists among all the field programmable gate arrays, the current high-speed time division multiplexing function ratio is not the smallest high-speed time division multiplexing function ratio in all the current high-speed time division multiplexing function ratios, and the number of the non-wiring networks or the through networks of all the field programmable gate arrays is not greater than the preset through network number threshold, adjusting the design codes or the constraint by utilizing a target optimization strategy corresponding to the design segmentation.
Optionally, after each design step is performed, determining whether the target key indicator corresponding to the design step meets the preset condition includes:
after the field programmable gate array system layout wiring is executed, judging whether the current high-speed time division multiplexing function ratio is the smallest high-speed time division multiplexing function ratio in all the high-speed time division multiplexing function ratios, whether the number of multi-hop paths among all the field programmable gate arrays is not more than a preset multi-hop path number threshold value and whether no wiring incapable network exists in all the field programmable gate arrays;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the current high-speed time division multiplexing function ratio is not the smallest high-speed time division multiplexing function ratio in all the high-speed time division multiplexing function ratios, the number of multi-hop paths among the field programmable gate arrays is larger than the preset multi-hop path number threshold value or a wiring-incapable network exists in the field programmable gate arrays, adjusting the constraint by utilizing a target optimization strategy corresponding to the layout and the wiring of the field programmable gate array system.
Optionally, after each design step is performed, determining whether the target key indicator corresponding to the design step meets the preset condition includes:
after the field programmable gate array system is generated, judging whether the estimated system clock frequency is smaller than a preset system clock frequency or not;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the estimated system clock frequency is not smaller than the preset system clock frequency, adjusting the constraint by utilizing a target optimization strategy corresponding to the generation of the field programmable gate array system.
Optionally, after each design step is performed, determining whether the target key indicator corresponding to the design step meets the preset condition includes:
after the design synthesis is executed, judging whether the number of unconverted gating clocks is smaller than a preset gating clock number threshold;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
And if the number of unconverted gating clocks is not smaller than the preset gating clock number threshold, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design synthesis.
In a second aspect, the present application discloses a chip prototype verification apparatus, applied to a HAPS prototype verification platform, including:
the initialization module is used for modifying the design code of the chip to be verified, so that the modified design code is matched with the HAPS prototype verification platform, and constraints corresponding to all design steps of the target verification stage are set;
the index determining module is used for determining target key indexes corresponding to each design step and preset conditions which are required to be met by each target key index;
the condition judging module is used for executing each design step according to the execution sequence, and judging whether the target key index corresponding to each design step meets the preset condition after each design step is executed;
and the iterative optimization module is used for adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step if the target key index does not meet the preset condition, performing iterative optimization until the target key index meets the preset condition, and executing the next design step according to the execution sequence if the target key index meets the preset condition.
In a third aspect, the present application discloses an electronic device comprising:
a memory for storing a computer program;
and a processor for executing the computer program to implement the chip prototype verification method disclosed previously.
In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the chip prototype verification method disclosed previously.
Therefore, the application provides a chip prototype verification method, which is applied to a HAPS prototype verification platform and comprises the following steps: modifying the design code of the chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and setting constraints corresponding to each design step of a target verification stage; determining target key indexes corresponding to each design step and preset conditions to be met by each target key index; executing each design step according to the execution sequence, and judging whether the target key index corresponding to each design step meets the preset condition after each design step is executed; and if the target key index does not meet the preset condition, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step, and performing iterative optimization until the target key index meets the preset condition, and if the target key index meets the preset condition, executing the next design step according to the execution sequence. In summary, the present application first determines target key indexes corresponding to each design step in a target verification stage and preset conditions to be met by each target key index, further, the present application executes each design step according to an execution sequence, and after each design step is executed, determines whether the target key index corresponding to the design step meets the preset conditions, if not, adjusts the design code or the constraint by using a target optimization strategy corresponding to the design step, and performs iterative optimization until the target key index meets the preset conditions, thereby improving efficiency and accuracy of chip prototype verification.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for chip prototype verification disclosed in the present application;
FIG. 2 is a flow chart of a design of a HAPS prototype verification platform;
FIG. 3 is a flowchart of a specific chip prototype verification method disclosed in the present application;
fig. 4 is a schematic structural diagram of a chip prototype verification apparatus disclosed in the present application;
fig. 5 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
When chip prototype verification is performed through the HAPS prototype verification platform, the segmentation in the first stage is a process of continuously trying and iterating to obtain an optimal result, and the integration in the first stage is also an important factor affecting design performance.
Therefore, the embodiment of the application provides a chip prototype verification scheme which can improve the accuracy and efficiency of the first stage of chip prototype verification.
The embodiment of the application discloses a chip prototype verification method, which is shown in fig. 1 and comprises the following steps:
step S11: modifying the design code of the chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and setting constraints corresponding to each design step of the target verification stage.
It should be noted that prototype verification includes three main stages, the first stage completing the segmentation and synthesis of the project according to the constraints of the developer in the EDA (Electronic design automation ) development suite of the prototype verification respective vendor, the second stage completing the Implementation (Implementation) in the vivado (design suite), and the third stage generating the download file and the related adaptation file.
The design flow of the HAPS prototype verification platform is shown in fig. 2, and mainly includes eleven design steps and their related constraints, wherein the prototype verification first stage work described above includes steps (1) - (9), and the main work performed by each step is as follows:
(1) input and diagnostic compilations (Diagnostic Compile) of the register transfer level circuit design RTL are prepared to exclude all analytical errors, analyze errors in the report design file and feed back to the designer. When the register transmission stage circuit design is free, the complete design compiling is continued.
(2) Debugging and design compilation are mainly completed, and the corresponding constraints of this part are monitoring constraints (Instrumentation Constraints) and compiling constraints Compiler Constraints (IDC).
(3) And (4) Pre-segmentation and segmentation of the design are mainly completed, and constraint files required for the two steps are a time sequence constraint file (Timing Constraints, FDC), a HAPS platform configuration file (Target System Spec, TSS), such as a clock source, an external daughter board type and position, and partition constraint (Partition Constraints, PCF).
(5) And (6) completing system placement and routing and system generation, the portion corresponding constraint being a system generation constraint (System route Constraints).
(7) (8) and (9) mapping the logic design to a particular FPGA chip, preparing relevant files for subsequent placement and routing in the vivado integrated development environment.
Sum to beTool run P&R（vivado P&R) and platform adaptation (generation. Bin&Platform adapt）。
Aiming at the problems of multiple iteration times, frequent manual intervention, long time consumption and the like in the first stage, the method and the device can improve the prototype verification efficiency of the HAPS platform, and specifically, the method and the device modify the design code of the chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and constraints corresponding to all design steps of the target verification stage are set.
It will be appreciated that the various design steps include design pre-segmentation, design segmentation, field programmable gate array system placement and routing, field programmable gate array system generation, and design synthesis.
Step S12: and determining target key indexes corresponding to each design step and preset conditions to be met by each target key index.
In this embodiment, the target key indicator includes a resource utilization (routing) of each piece of field programmable gate array in a field programmable gate array system, a clock crossing number (cut clocks) between each piece of field programmable gate array, a high-speed time division multiplexing function ratio (HSTDM ratio), a non-wired network number (unpurved nets) of each piece of field programmable gate array, a through network number (fed through nets) of each piece of field programmable gate array, a multi-hop path number (multi-hop net) between each piece of field programmable gate array, an estimated system clock frequency (Estimated Frequency), and an unconverted gate clock number (Gated clock num).
In some embodiments, for a first stage of design success, the target key metrics must meet the following conditions: the resource utilization rate of each FPGA used in the design is below 65%; there is no number of clock crossings; a small number of pass-through networks; a small number of multi-hop paths; a minimal interconnection network; reasonable system clock frequency; a minimum number of unconverted gating clocks, etc.
Step S13: and executing the design steps according to the execution sequence, and judging whether the target key indexes corresponding to the design steps meet the preset conditions after each design step is executed.
In this embodiment, after each design step is performed, a corresponding execution report is obtained, the execution report is analyzed, and then whether the target key index corresponding to the design step meets the preset condition is determined according to the analysis result.
Step S14: and if the target key index does not meet the preset condition, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step, and performing iterative optimization until the target key index meets the preset condition, and if the target key index meets the preset condition, executing the next design step according to the execution sequence.
In a specific embodiment, after the design pre-segmentation is performed, judging whether the resource utilization rate of the field programmable gate array is smaller than a preset resource utilization rate threshold; correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including: and if the resource utilization rate of the field programmable gate array is not smaller than the preset resource utilization rate threshold, adjusting the design code by utilizing a target optimization strategy corresponding to the design pre-segmentation.
In a second specific embodiment, after the design splitting is performed, judging whether the resource utilization rate of the field programmable gate array is smaller than the preset resource utilization rate threshold, whether clock crossing does not exist among the field programmable gate arrays, whether the current high-speed time division multiplexing function ratio is the smallest high-speed time division multiplexing function ratio among all the high-speed time division multiplexing function ratios, whether no non-wired network exists among the field programmable gate arrays, and whether the number of through networks of the field programmable gate arrays is not greater than a preset through network number threshold; correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including: and if the resource utilization rate of the field programmable gate array is not less than the preset resource utilization rate threshold, clock crossing exists among all the field programmable gate arrays, the current high-speed time division multiplexing function ratio is not the smallest high-speed time division multiplexing function ratio in all the current high-speed time division multiplexing function ratios, and the number of the non-wiring networks or the through networks of all the field programmable gate arrays is not greater than the preset through network number threshold, adjusting the design codes or the constraint by utilizing a target optimization strategy corresponding to the design segmentation.
In a third specific embodiment, after the performing of the layout and the wiring of the field programmable gate array system, determining whether the current high-speed time division multiplexing function ratio is the smallest high-speed time division multiplexing function ratio among all the high-speed time division multiplexing function ratios, whether the number of multi-hop paths between the field programmable gate arrays is not greater than a preset multi-hop path number threshold, and whether no non-wired network exists in the field programmable gate arrays; correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including: and if the current high-speed time division multiplexing function ratio is not the smallest high-speed time division multiplexing function ratio in all the high-speed time division multiplexing function ratios, the number of multi-hop paths among the field programmable gate arrays is larger than the preset multi-hop path number threshold value or a wiring-incapable network exists in the field programmable gate arrays, adjusting the constraint by utilizing a target optimization strategy corresponding to the layout and the wiring of the field programmable gate array system.
In a fourth specific embodiment, after the field programmable gate array system is generated, determining whether the estimated system clock frequency is less than a preset system clock frequency; correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including: and if the estimated system clock frequency is not smaller than the preset system clock frequency, adjusting the constraint by utilizing a target optimization strategy corresponding to the generation of the field programmable gate array system.
In a fifth specific embodiment, after the design synthesis is performed, determining whether the number of unconverted gating clocks is smaller than a preset gating clock number threshold; correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including: and if the number of unconverted gating clocks is not smaller than the preset gating clock number threshold, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design synthesis.
In summary, for several target key indexes in the first stage of HAPS prototype verification, the method and the device check whether the target key indexes meet corresponding thresholds and are scientific and reasonable, and automatically give out a more reasonable optimization strategy when a certain key index is not met, so that the efficiency and the accuracy of chip prototype verification are improved.
Therefore, the application provides a chip prototype verification method, which is applied to a HAPS prototype verification platform and comprises the following steps: modifying the design code of the chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and setting constraints corresponding to each design step of a target verification stage; determining target key indexes corresponding to each design step and preset conditions to be met by each target key index; executing each design step according to the execution sequence, and judging whether the target key index corresponding to each design step meets the preset condition after each design step is executed; and if the target key index does not meet the preset condition, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step, and performing iterative optimization until the target key index meets the preset condition, and if the target key index meets the preset condition, executing the next design step according to the execution sequence. In summary, the present application first determines target key indexes corresponding to each design step in a target verification stage and preset conditions to be met by each target key index, further, the present application executes each design step according to an execution sequence, and after each design step is executed, determines whether the target key index corresponding to the design step meets the preset conditions, if not, adjusts the design code or the constraint by using a target optimization strategy corresponding to the design step, and performs iterative optimization until the target key index meets the preset conditions, thereby improving efficiency and accuracy of chip prototype verification.
The chip prototype verification method described in this application is described below by way of one specific example, and as shown in figure 3,
(1) The method is controlled to be automatically executed according to a set flow to finish the modification of the design codes of the chip to be verified, and comprises the steps of replacing a clock generator and a RAM (random access memory ) module, cutting a useless module, processing a gating clock and the like, and setting the constraint of each design step in a HAPS prototype verification platform;
(2) Setting the pre-segmentation area prediction enabling to be 1, then executing a pre-segmentation design step, carrying out preliminary statistics on the resource utilization rate of each FPGA, and carrying out the next operation when the resource utilization rate of each FPGA is less than 65%, otherwise informing a designer of modifying design codes or increasing the number of FPGA chips;
(3) If the utilization rate of each FPGA resource in the pre-segmentation is less than 65%, setting the pre-estimated enabling of the segmented area to be 1, then executing the segmentation step, and judging whether the following conditions are met after the segmentation step is executed: each piece of FPGA resource utilization rate is less than 65%, 0 clock crossing number, current high-speed time division multiplexing function ratio is the minimum high-speed time division multiplexing function ratio in all high-speed time division multiplexing function ratios, 0 unable wiring network number, and through network number is less than or equal to 10, further, if any condition is not met, for example, if resource utilization rate is more than or equal to 65%, design codes are modified, if clock crossing number is not 0, clock networks of HAPS platforms in constraint are modified or design codes are modified, if current high-speed time division multiplexing function ratio is not the minimum high-speed time division multiplexing function ratio in all high-speed time division multiplexing function ratios, HAPS platform configuration files (update auto_tss_control and abstract_tss) in constraint are updated, if unable wiring network number is not 0, network wiring is optimized preferentially (Optimization Priority-nets optimizing constraint is enabled), if through network number is more than 10, network wiring is optimized preferentially, and HAPS platform configuration files in constraint are updated simultaneously.
(4) If the conditions are met, executing system layout wiring, and judging whether the following conditions are met: the current high-speed time division multiplexing function ratio is the minimum high-speed time division multiplexing function ratio in all high-speed time division multiplexing function ratios, the number of multi-hop paths is less than or equal to 3, and 0 cannot route the network number, further, if any condition is not satisfied, for example, if the current high-speed time division multiplexing function ratio is not the minimum high-speed time division multiplexing function ratio in all high-speed time division multiplexing function ratios, the HAPS platform configuration file in the constraint is updated, if the number of multi-hop paths is more than 3, the multi-hop paths are preferentially processed (Optimization Priority-multi-hop net optimization constraint is enabled), and if the number of the network cannot route is not 0, the HAPS platform configuration file in the constraint is updated.
(5) If the conditions are satisfied, the system generation is executed, whether the estimated clock frequency (Estimated Frequency) is smaller than the design system clock frequency (Requested Frequency) is judged, and if not, the design system clock frequency is reduced.
(6) If the estimated clock frequency is less than the design system clock frequency, performing synthesis, judging whether the number of the gating clocks which are not converted at the current f is less than 10, if not, preferentially converting the gating clocks (enabling fix_protected_and_generated_clocks optimization constraint) or modifying the design codes.
(7) If the number of unconverted gating clocks is less than 10, a second phase is performed.
In summary, the present application realizes an automated flow control method for improving the efficiency of HAPS prototype verification, in each stage of design implementation, by analyzing the implementation report of the design, it is determined whether the target key index in the corresponding stage meets the condition, and when the key index in a certain step does not meet the optimal condition, a more reasonable optimization strategy is automatically given and iterative optimization is performed, so that the accuracy of HAPS prototype verification implementation is improved, the efficiency of prototype verification is also improved, and the time input of prototype verification personnel is reduced.
Correspondingly, the embodiment of the application also discloses a chip prototype verification device, as shown in fig. 4, which comprises:
an initialization module 11, configured to modify a design code of a chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and set constraints corresponding to each design step in a target verification stage;
an index determining module 12, configured to determine a target key index corresponding to each of the design steps and a preset condition that needs to be satisfied by each of the target key indexes;
A condition judgment module 13, configured to execute the design steps in an execution order, and judge whether the target key index corresponding to the design step satisfies the preset condition after each design step is executed;
and the iterative optimization module 14 is configured to adjust the design code or the constraint by using a target optimization strategy corresponding to the design step if the target key index does not meet the preset condition, and perform iterative optimization until the target key index meets the preset condition, and execute the next design step according to the execution sequence if the target key index meets the preset condition.
The more specific working process of each module may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.
Therefore, the application provides a chip prototype verification method, which is applied to a HAPS prototype verification platform and comprises the following steps: modifying the design code of the chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and setting constraints corresponding to each design step of a target verification stage; determining target key indexes corresponding to each design step and preset conditions to be met by each target key index; executing each design step according to the execution sequence, and judging whether the target key index corresponding to each design step meets the preset condition after each design step is executed; and if the target key index does not meet the preset condition, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step, and performing iterative optimization until the target key index meets the preset condition, and if the target key index meets the preset condition, executing the next design step according to the execution sequence. In summary, the present application first determines target key indexes corresponding to each design step in a target verification stage and preset conditions to be met by each target key index, further, the present application executes each design step according to an execution sequence, and after each design step is executed, determines whether the target key index corresponding to the design step meets the preset conditions, if not, adjusts the design code or the constraint by using a target optimization strategy corresponding to the design step, and performs iterative optimization until the target key index meets the preset conditions, thereby improving efficiency and accuracy of chip prototype verification.
Further, the embodiment of the application also provides electronic equipment. Fig. 5 is a block diagram of an electronic device 20, according to an exemplary embodiment, and the contents of the diagram should not be construed as limiting the scope of use of the present application in any way.
Fig. 5 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. Wherein the memory 22 is used for storing a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the chip prototype verification method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.
In this embodiment, the power supply 26 is used to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 24 is used for obtaining external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application needs, which is not limited herein.
The memory 22 may be a read-only memory, a random access memory, a magnetic disk, an optical disk, or the like, and the resources stored thereon may include the computer program 221, which may be stored in a temporary or permanent manner. The computer program 221 may further include a computer program for performing other specific tasks in addition to the computer program for performing the chip prototype verification method performed by the electronic device 20 disclosed in any of the foregoing embodiments.
Further, the embodiment of the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the chip prototype verification method disclosed previously.
For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this application, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments refer to the devices disclosed in the embodiments, so that the description is relatively simple because it corresponds to the method disclosed in the embodiments, and the relevant parts refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing has described in detail a method, apparatus, device, and storage medium for chip prototype verification provided in the present application, and specific examples have been applied herein to illustrate the principles and embodiments of the present application, where the foregoing examples are provided to assist in understanding the method and core idea of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (12)
1. The chip prototype verification method is characterized by being applied to a HAPS prototype verification platform and comprising the following steps of:
modifying the design code of the chip to be verified, so that the modified design code is adapted to the HAPS prototype verification platform, and setting constraints corresponding to each design step of a target verification stage;
determining target key indexes corresponding to each design step and preset conditions to be met by each target key index;
executing each design step according to the execution sequence, and judging whether the target key index corresponding to each design step meets the preset condition after each design step is executed;
And if the target key index does not meet the preset condition, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step, and performing iterative optimization until the target key index meets the preset condition, and if the target key index meets the preset condition, executing the next design step according to the execution sequence.
2. The chip prototype-verification method according to claim 1, wherein said determining whether the target key index corresponding to the design step satisfies the preset condition after each of the design steps is performed, comprises:
after each design step is executed, a corresponding execution report is obtained;
analyzing the execution report, and judging whether the target key index corresponding to the design step meets the preset condition according to an analysis result.
3. The chip prototype verification method according to claim 1 or 2, wherein the target key indicator includes a resource utilization of each piece of field programmable gate array in a field programmable gate array system, a number of clock crossings between each piece of field programmable gate array, a high-speed time division multiplexing function ratio, a number of non-wired networks of each piece of field programmable gate array, a number of through networks of each piece of field programmable gate array, a number of multi-hop paths between each piece of field programmable gate array, an estimated system clock frequency, and a number of unconverted gating clocks.
4. The chip prototype-verification method as claimed in claim 3, wherein said designing step sequentially comprises: design pre-segmentation, design segmentation, field programmable gate array system layout wiring, field programmable gate array system generation and design synthesis.
5. The chip prototype-verification method according to claim 4, wherein said determining whether the target key index corresponding to the design step satisfies the preset condition after each of the design steps is performed, comprises:
after the design pre-segmentation is executed, judging whether the resource utilization rate of the field programmable gate array is smaller than a preset resource utilization rate threshold value;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the resource utilization rate of the field programmable gate array is not smaller than the preset resource utilization rate threshold, adjusting the design code by utilizing a target optimization strategy corresponding to the design pre-segmentation.
6. The chip prototype-verification method according to claim 5, wherein said determining whether the target key index corresponding to the design step satisfies the preset condition after each of the design steps is performed, comprises:
After the design segmentation is performed, judging whether the resource utilization rate of the field programmable gate array is smaller than the preset resource utilization rate threshold value, whether clock crossing does not exist among all the field programmable gate arrays, whether the current high-speed time division multiplexing function ratio is the smallest high-speed time division multiplexing function ratio in all the high-speed time division multiplexing function ratios, whether no wiring-disabled network exists among all the field programmable gate arrays, and whether the number of the through networks of all the field programmable gate arrays is not larger than the preset through network number threshold value;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the resource utilization rate of the field programmable gate array is not less than the preset resource utilization rate threshold, clock crossing exists among all the field programmable gate arrays, the current high-speed time division multiplexing function ratio is not the smallest high-speed time division multiplexing function ratio in all the current high-speed time division multiplexing function ratios, and the number of the non-wiring networks or the through networks of all the field programmable gate arrays is not greater than the preset through network number threshold, adjusting the design codes or the constraint by utilizing a target optimization strategy corresponding to the design segmentation.
7. The chip prototype-verification method according to claim 5, wherein said determining whether the target key index corresponding to the design step satisfies the preset condition after each of the design steps is performed, comprises:
after the field programmable gate array system layout wiring is executed, judging whether the current high-speed time division multiplexing function ratio is the smallest high-speed time division multiplexing function ratio in all the high-speed time division multiplexing function ratios, whether the number of multi-hop paths among all the field programmable gate arrays is not more than a preset multi-hop path number threshold value and whether no wiring incapable network exists in all the field programmable gate arrays;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the current high-speed time division multiplexing function ratio is not the smallest high-speed time division multiplexing function ratio in all the high-speed time division multiplexing function ratios, the number of multi-hop paths among the field programmable gate arrays is larger than the preset multi-hop path number threshold value or a wiring-incapable network exists in the field programmable gate arrays, adjusting the constraint by utilizing a target optimization strategy corresponding to the layout and the wiring of the field programmable gate array system.
8. The chip prototype-verification method according to claim 5, wherein said determining whether the target key index corresponding to the design step satisfies the preset condition after each of the design steps is performed, comprises:
after the field programmable gate array system is generated, judging whether the estimated system clock frequency is smaller than a preset system clock frequency or not;
correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the estimated system clock frequency is not smaller than the preset system clock frequency, adjusting the constraint by utilizing a target optimization strategy corresponding to the generation of the field programmable gate array system.
9. The chip prototype-verification method according to claim 5, wherein said determining whether the target key index corresponding to the design step satisfies the preset condition after each of the design steps is performed, comprises:
after the design synthesis is executed, judging whether the number of unconverted gating clocks is smaller than a preset gating clock number threshold;
Correspondingly, if the target key index does not meet the preset condition, adjusting the design code or the constraint by using a target optimization strategy corresponding to the design step, including:
and if the number of unconverted gating clocks is not smaller than the preset gating clock number threshold, adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design synthesis.
10. A chip prototype-verification apparatus, for use in a HAPS prototype-verification platform, comprising:
the initialization module is used for modifying the design code of the chip to be verified, so that the modified design code is matched with the HAPS prototype verification platform, and constraints corresponding to all design steps of the target verification stage are set;
the index determining module is used for determining target key indexes corresponding to each design step and preset conditions which are required to be met by each target key index;
the condition judging module is used for executing each design step according to the execution sequence, and judging whether the target key index corresponding to each design step meets the preset condition after each design step is executed;
And the iterative optimization module is used for adjusting the design code or the constraint by utilizing a target optimization strategy corresponding to the design step if the target key index does not meet the preset condition, performing iterative optimization until the target key index meets the preset condition, and executing the next design step according to the execution sequence if the target key index meets the preset condition.
11. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the chip prototype verification method as claimed in any one of claims 1 to 9.
12. A computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the chip prototype verification method as claimed in any one of claims 1 to 9.
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