CN117708549B - Chip sorting optimization method, system and storage medium - Google Patents

Chip sorting optimization method, system and storage medium Download PDF

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CN117708549B
CN117708549B CN202410161781.6A CN202410161781A CN117708549B CN 117708549 B CN117708549 B CN 117708549B CN 202410161781 A CN202410161781 A CN 202410161781A CN 117708549 B CN117708549 B CN 117708549B
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张文浩
杨佳琦
史曼云
顾凯文
嵇浚哲
方绍伟
张贵阳
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Changshu Institute of Technology
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Abstract

The invention discloses a chip sorting optimization method, a system and a storage medium, wherein the sorting optimization method comprises the following steps: establishing a target optimization function of chip sorting; randomly dividing the currently solved chip sorting path into a plurality of blocks, generating full permutation and combination of the blocks, comprehensively considering the operation efficiency and the solving efficiency, and calculating an objective function value for each new path combination; and selecting the optimal combination from the iterated combinations as the current optimal solution path. Through analysis of elements in the chip sorting process, an objective optimization function of chip sorting is established, and on the basis, through improvement of an simulated annealing algorithm, an optimized mathematical model and a method for chip sorting are provided, and the safety of the chip sorting process is emphasized while the sorting path optimization is considered, so that the purposes of improving the chip sorting speed and reducing the energy consumption are achieved.

Description

Chip sorting optimization method, system and storage medium
Technical Field
The invention belongs to the technical field of chip manufacturing, and relates to a chip sorting optimization method, a chip sorting optimization system and a storage medium.
Background
The chip is used as a highly precise electronic component, the production process is very complex, and the chip is extremely fragile. Along with the continuous development of the production and manufacturing technology, the complexity of the chip is continuously increased, the characteristic size is smaller and smaller, the assembly density is higher and higher, and the requirements on the processes of the production, the manufacture, the encapsulation and the like of the chip are further improved. The chip sorting is a process of automatically sorting chips with the same grade and the same type on the disc on the membrane according to the photoelectric parameters of the chips measured by the detector and the classification standard. The chip is used as a highly precise electronic component, the chip is extremely sensitive to external acting force, and meanwhile, a disc can contain a large number of chips, and the chip sorter needs to carry out a large number of operations such as moving, picking up and the like, so that the sorting strategy and the action mechanism of the chip sorter are optimized through a certain method, the actions between the sorter and the disc of the chip can be reduced to the greatest extent, the possibility of damaging the chip is reduced, the sorting efficiency of the chip is improved, and meanwhile, the energy consumption and the abrasion of the sorter can be reduced, so that the production cost of the chip is reduced.
The simulated annealing algorithm is derived from a physical solid annealing principle, in the physical annealing process, when the temperature of the solid is high, the internal energy is large, particles in the solid are in a disordered motion state, when the temperature is slowly reduced, the internal energy of the solid is reduced, the motion of the particles tends to be orderly, if the temperature is slowly reduced, the particles can keep an equilibrium state at each temperature, and finally, when the solid is at normal temperature, the internal energy is minimum, and the particles are most stable. The simulated annealing algorithm starts from the initial temperature, and the solution of the objective function tends to be stable along with the temperature decrease, but the stable solution may be a locally optimal solution, so when reaching a poor solution, the algorithm receives a difference solution with a certain probability, and thus the locally optimal solution is jumped out to find a globally optimal solution of the objective function.
Disclosure of Invention
The invention aims to provide a chip sorting optimization method, a system and a storage medium, which are used for establishing a target optimization function of chip sorting, and providing an optimized mathematical model and a method for chip sorting through improving an simulated annealing algorithm.
The technical solution for realizing the purpose of the invention is as follows:
A chip sorting optimization method, comprising the steps of:
s01: establishing a target optimization function of chip sorting;
S02: randomly dividing the currently solved chip sorting path into a plurality of blocks, generating full permutation and combination of the blocks, comprehensively considering the operation efficiency and the solving efficiency, and calculating an objective function value for each new path combination;
S03: and selecting the optimal combination from the iterated combinations as the current optimal solution path.
In a preferred technical scheme, in the step S01, an objective optimization function for chip sorting is established according to the total movement time of the mechanical arm and the balance parameters of the wafer disc：
To normalize the total time parameter of the mechanical arm movement,/>To normalize the wafer balance parameters,/>、/>Coefficients, respectively.
In a preferred technical scheme, the normalized mechanical arm motion total time parameter：
Wherein,For the time taken for the robotic arm to move from the initial position to the first target chip,/>For the index of the chip,To move the chip to the target storage position/>Time of use,/>To move to the next chip/>Time of use,/>To continuously move the chips until the chips on the wafer are all sorted, the time for the chips to return to the initial position,/>, is usedFor the total number of chips,/>To maximize time consumption of sorting chips,/>Is the average moving speed of the mechanical arm,/>For chip/>Distance from the target storage location.
In a preferred technical scheme, the normalized wafer balance parameterThe calculation formula of (2) is as follows:
wherein, For the total number of chips,/>The radius of the wafer disc is the radius of the chip wafer disc, and the center point coordinate of the wafer disc isChip/>Is/>。
In a preferred embodiment, the step S02 includes:
S21: calculating an objective function value of the current path;
S22: randomly dividing the currently solved chip sorting path into m blocks, regarding each block as a whole, and generating full-permutation combination of the m blocks;
s23: calculating objective function values for each new path ，/>Is an algorithm iteration number;
S24: and judging whether the difference between the objective function value of the new path and the objective function value of the current path is smaller than 0, if so, calculating the probability to select whether to accept the new path, and if not, setting the new path as the current path.
In a preferred embodiment, the formula for calculating the probability in step S24 is:
wherein, For algorithm iteration ordinal,/>Is the difference of the objective function after two adjacent iterations,/>As a function of temperature decay.
In a preferred technical scheme, the step S21 further includes setting an initial temperature of the simulated annealing algorithmTemperature decay function/>，/>Is an algorithm iteration ordinal.
The invention also discloses a chip sorting optimization system, which comprises:
the target optimization function construction module is used for establishing a target optimization function for chip sorting;
The iterative optimization module randomly divides the currently solved chip sorting path into a plurality of blocks, generates full permutation and combination of the blocks, comprehensively considers the operation efficiency and the solving efficiency, and calculates an objective function value for each new path combination;
And the optimal solution path planning module is used for selecting an optimal combination from all the combinations after iteration is completed as a current optimal solution path.
In a preferred technical scheme, the objective optimization function construction module establishes an objective optimization function for chip sorting according to the total movement time of the mechanical arm and the wafer balance parameters：
To normalize the total time parameter of the mechanical arm movement,/>To normalize the wafer balance parameters,/>、/>Coefficients, respectively.
The invention also discloses a computer storage medium, on which a computer program is stored, which when executed implements the chip sorting optimization method described above.
Compared with the prior art, the invention has the remarkable advantages that:
Aiming at the chip sorting problem, a target optimization function of chip sorting is established through analysis of elements in the chip sorting process, and an optimized mathematical model and a method of chip sorting are provided on the basis through improvement of an simulated annealing algorithm. The method has the advantages that the optimization of the sorting path is considered, meanwhile, the safety of the chip sorting process is emphasized, so that the purposes of improving the chip sorting speed and reducing the energy consumption are achieved, the possible damage probability in the chip sorting process is reduced, the chip sorting efficiency and quality can be effectively improved, the chip production cost is reduced, and the method has wide application market space and economic value.
Drawings
FIG. 1 is a flow chart of a chip sort optimization method of the preferred embodiment;
FIG. 2 is a schematic diagram of die distribution and sorting on a wafer;
FIG. 3 is a schematic diagram illustrating deformation caused by stress imbalance of a disk;
FIG. 4 is a schematic diagram of a chip sort move sequence;
FIG. 5 is a flow chart of a modified simulated annealing algorithm;
FIG. 6 is a graph comparing the effect of the modified simulated annealing algorithm with that of the conventional simulated annealing algorithm.
Detailed Description
The principle of the invention is as follows: through analysis of elements in the chip sorting process, an objective optimization function of chip sorting is established, and on the basis, through improvement of an simulated annealing algorithm, an optimized mathematical model and a method for chip sorting are provided, and the safety of the chip sorting process is emphasized while the sorting path optimization is considered, so that the purposes of improving the chip sorting speed and reducing the energy consumption are achieved.
Example 1:
As shown in fig. 1, a chip sorting optimization method includes the following steps:
s01: establishing a target optimization function of chip sorting;
S02: randomly dividing the currently solved chip sorting path into a plurality of blocks, generating full permutation and combination of the blocks, comprehensively considering the operation efficiency and the solving efficiency, and calculating an objective function value for each new path combination;
S03: and selecting the optimal combination from the iterated combinations as the current optimal solution path.
In a preferred embodiment, in step S01, a target optimization function for chip sorting is established according to the total motion time of the mechanical arm and the wafer balance parameters：
To normalize the total time parameter of the mechanical arm movement,/>To normalize the wafer balance parameters,/>、/>Coefficients, respectively.
In a preferred embodiment, the total time of arm motion parameter is normalized：
Wherein,For the time taken for the robotic arm to move from the initial position to the first target chip,/>For the index of the chip,To move the chip to the target storage position/>Time of use,/>To move to the next chip/>Time of use,/>To continuously move the chips until the chips on the wafer are all sorted, the time for the chips to return to the initial position,/>, is usedFor the total number of chips,/>To maximize time consumption of sorting chips,/>Is the average moving speed of the mechanical arm,/>For chip/>Distance from the target storage location.
In a preferred embodiment, wafer balance parameters are normalizedThe calculation formula of (2) is as follows:
wherein, For the total number of chips,/>The radius of the wafer disc is the radius of the chip wafer disc, and the center point coordinate of the wafer disc isChip/>Is/>。
In a preferred embodiment, step S02 includes:
S21: calculating an objective function value of the current path;
S22: randomly dividing the currently solved chip sorting path into m blocks, regarding each block as a whole, and generating full-permutation combination of the m blocks;
s23: calculating objective function values for each new path ，/>Is an algorithm iteration number;
S24: and judging whether the difference between the objective function value of the new path and the objective function value of the current path is smaller than 0, if so, calculating the probability to select whether to accept the new path, and if not, setting the new path as the current path.
In a preferred embodiment, the formula for calculating the probability in step S24 is:
wherein, For algorithm iteration ordinal,/>Is the difference of the objective function after two adjacent iterations,/>As a function of temperature decay.
In a preferred embodiment, step S21 further comprises setting an initial temperature of the simulated annealing algorithmTemperature decay function/>，/>Is an algorithm iteration ordinal.
In another embodiment, a computer storage medium has a computer program stored thereon, which when executed implements the chip sort optimization method described above. The above detection method is adopted, and will not be described here.
In yet another embodiment, a chip sort optimization system includes:
the target optimization function construction module is used for establishing a target optimization function for chip sorting;
The iterative optimization module randomly divides the currently solved chip sorting path into a plurality of blocks, generates full permutation and combination of the blocks, comprehensively considers the operation efficiency and the solving efficiency, and calculates an objective function value for each new path combination;
And the optimal solution path planning module is used for selecting an optimal combination from all the combinations after iteration is completed as a current optimal solution path.
Specifically, the following describes the workflow of the chip sorting optimization system by taking a preferred embodiment as an example:
Step one: and establishing a target optimization function of the chip sorting process.
There are typically hundreds of chips to be sorted on a wafer, and after the wafer is cut, the chips are sorted, and after electrical detection, defect detection and the like, the chips with the same types and similar quality are sorted, picked and stored according to the types according to the detection result, as shown in fig. 2. In order to improve the sorting efficiency of the chips and simultaneously minimize the damage to the chips in the sorting process, the following factors need to be considered:
1. and the time required for the chip sorting mechanical arm to move. The longer the arm moves, the more time is required and the production energy consumption increases. Meanwhile, the chip is generally thinner and fragile, so that the moving distance of the chip sorting process is reduced, and the possibility of damage to the chip caused by the chip transfer mechanical device can be reduced. Secondly, the chip size is smaller, and the possibility of influencing the chip due to the vibration of the mechanical arm, the air flow and the like is increased due to the longer moving distance; in addition, if the distance between the two adjacent chips is larger, the coordinate error accumulation of the chip sorting mechanism in the motion process can be caused, and the small chip size has high requirement on the picking precision, so that the sorting error caused by the error accumulation is easy to occur, and even the chip is damaged.
2. The wafer disks are unbalanced due to the removal of the chips, which results in deformation of the disks. Because the wafer disc has the characteristics of thin thickness and large brittleness, the wafer disc deforms due to different stress of each area in the sorting process, so that the wafer disc is damaged, as shown in fig. 3.
Based on the analysis of chip sorting, the invention establishes the objective optimization function of the chip sorting process as shown in formula (4), whereinOptimizing the function for the goal,/>To normalize the total time parameter of the mechanical arm movement,/>To normalize the wafer balance parameters,/>、/>Coefficients, respectively.
（4）
Setting a chip on the wafer discThe target storage position is/>Wherein/>For the category obtained after the chip is detected,/>Is an index of the chip. For chip movement on one wafer disc, it can be divided into 4 processes:
① Firstly, the mechanical arm moves to a first target chip from an initial position, the time is that ; ② The chip is then moved to the target storage location/>The time taken is/>; ③ Then move to the next chip/>The time is; ④ And repeatedly carrying out ②③ until all the chips on the wafer disc are sorted, and finally recovering the chips to the initial position for/>, wherein the time isAs shown in fig. 4. Therefore, the total time parameter/>, of the mechanical arm movement is normalizedThe calculation of (2) is shown in the formula (5):
（5）
wherein, For the total number of chips,/>To maximize time consumption of sorting chips,/>Is the average moving speed of the mechanical arm,/>For chip/>Distance from the target storage location. For formula (5), wherein/>、/>And/>Is fixed/>The total movement time of the mechanical arm is optimized because the chip sorting path is changed, and the total movement time of the mechanical arm is optimized mainly by optimizing the chip sorting path。
The wafer disc is deformed due to unbalance caused by the removal of the chips, and the situation needs to keep balance in all directions of the disc as much as possible in the process of sorting the chips. Set the center point coordinate of the wafer disc asChip/>Is/>Normalized wafer disc balance parameter/>The calculation of (2) is shown as a formula (6), wherein/>For the total number of chips,/>Is the radius of the chip wafer disc.
（6）
Step two: chip sort optimization based on improved simulated annealing algorithm.
According to the analysis in the first step, chip sorting optimization can be abstracted into a path planning problem, and the solution space is all feasible paths in the chip sorting process, so that the optimal solution is found. Because the number of chips on each wafer disc is hundreds, the size of the solution space is huge, the optimal solution in the solution space is difficult to directly find, an intelligent optimization algorithm is needed for calculation, and the improved simulated annealing algorithm is used for completing path planning of chip decomposition.
According to the principle of the simulated annealing algorithm, a chip decomposition coding mode is firstly set. The invention encodes the chips to be sorted by using integers, and the encoding sequence is from top to bottom and from left to right, as shown in figure 2. The simulated annealing algorithm finally outputs a sequence consisting of chip numbersAs shown in formula (7)/>Indicating that the sorting mechanism starts from 0 and chips numbered 3, 9, etc. eventually return to 0, where 0 indicates the starting position of the chip sorting robot arm,/>Is the number of chips.
（7）
According to the analysis of the chip sorting process, setting the initial temperature of the simulated annealing algorithmAs shown in formula (8), in whichIs the average moving speed of the mechanical arm,/>For chip/>Distance from target storage location,/>Is the radius of the chip wafer disc,/>Index for chip,/>Is the number of chips.
（8）
At the same time, a temperature decay function as shown in formula (9) is adopted, whereinIs an algorithm iteration ordinal.
（9）
The simulated annealing algorithm does not discard the worse solution immediately in order to jump out the locally optimal solution, but with a certain probabilityAccept worse solution, probability/>The calculation of (2) is shown in the formula (10):
（10）
wherein, For algorithm iteration ordinal,/>And (4) taking the difference value of the objective function after two adjacent iterations as the objective function, wherein the objective function is shown in a formula (4).
The invention uses a new disturbance mechanism to improve the simulated annealing algorithm. The flow of the modified simulated annealing algorithm in the present invention is shown in fig. 5. First randomly dividing the current solved chip sorting path intoThe blocks are generated and all permutation and combination of the blocks are generated, and the operation efficiency and the solving efficiency are comprehensively considered,/>The value range of (2) is/>. And then calculating an objective function value for each new path combination, selecting an optimal combination from all combinations after iteration is completed as a current optimal solution path, repeating the process until the iteration is finished, and setting the iteration number to be 200.
In order to verify the improvement effect of the invention, sorting efficiency tests are carried out on wafers with three specifications of 6, 8 and 12 inches, a method of taking an average value through multiple tests is adopted, and compared with a traditional chip sorting method, the experimental results are shown in table 1.
Table 1 comparison of chip sorting optimization effect experiments
From the table, the method of the invention has obvious improvement on the chip sorting efficiency.
An iterative calculation pair for chip sorting using the algorithm of the present invention with a conventional simulated annealing algorithm is shown in fig. 6.
The foregoing examples are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the foregoing examples, and any other changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principles of the present invention should be made therein and are intended to be equivalent substitutes within the scope of the present invention.

Claims (7)

1. The chip sorting optimization method is characterized by comprising the following steps of:
S01: establishing a target optimization function for chip sorting according to the total movement time of the mechanical arm and the balance parameters of the wafer disc ：
，
To normalize the total time parameter of the mechanical arm movement,/>To normalize the wafer balance parameters,/>、/>Coefficients respectively;
S02: randomly dividing the currently solved chip sorting path into a plurality of blocks, generating full permutation and combination of the blocks, comprehensively considering the operation efficiency and the solving efficiency, and calculating an objective function value for each new path combination; the method specifically comprises the following steps:
S21: calculating an objective function value of the current path;
S22: randomly dividing the currently solved chip sorting path into m blocks, regarding each block as a whole, and generating full-permutation combination of the m blocks;
s23: calculating objective function values for each new path ，/>Is an algorithm iteration number;
S24: judging whether the difference between the objective function value of the new path and the objective function value of the current path is smaller than 0, if so, calculating probability to select whether to accept the new path, and if not, setting the new path as the current path;
S03: and selecting the optimal combination from the iterated combinations as the current optimal solution path.
2. The method of claim 1, wherein the normalized mechanical arm motion total time parameter：
，
Wherein,For the time taken for the robotic arm to move from the initial position to the first target chip,/>Index for chip,/>To move the chip to the target storage position/>Time of use,/>To move to the next chip/>The time taken for the time to elapse,In order to continuously move the chips until the chips on the wafer are all sorted, the time for the chips to return to the initial positions is used,For the total number of chips,/>To maximize time consumption of sorting chips,/>Is the average moving speed of the mechanical arm,/>For chip/>Distance from the target storage location.
3. The method of claim 1, wherein the normalized wafer disc balance parameterThe calculation formula of (2) is as follows:
，
wherein, For the total number of chips,/>The radius of the wafer disc is the radius of the chip wafer disc, and the center point coordinate of the wafer disc isChip/>Is/>。
4. The chip sorting optimization method according to claim 1, wherein the formula for calculating the probability in step S24 is:
，
wherein, For algorithm iteration ordinal,/>Is the difference of the objective function after two adjacent iterations,/>As a function of temperature decay.
5. The chip sorting optimization method according to claim 1, wherein the step S21 is preceded by setting an initial temperature of a simulated annealing algorithmTemperature decay function/>，Is an algorithm iteration ordinal.
6. A chip sort optimization system, comprising:
The target optimization function construction module is used for establishing a chip sorting target optimization function according to the total movement time of the mechanical arm and the wafer balance parameters ：
，
To normalize the total time parameter of the mechanical arm movement,/>To normalize the wafer balance parameters,/>、/>Coefficients respectively;
The iterative optimization module randomly divides the currently solved chip sorting path into a plurality of blocks, generates full permutation and combination of the blocks, comprehensively considers the operation efficiency and the solving efficiency, and calculates an objective function value for each new path combination; the method specifically comprises the following steps:
S21: calculating an objective function value of the current path;
S22: randomly dividing the currently solved chip sorting path into m blocks, regarding each block as a whole, and generating full-permutation combination of the m blocks;
s23: calculating objective function values for each new path ，/>Is an algorithm iteration number;
S24: judging whether the difference between the objective function value of the new path and the objective function value of the current path is smaller than 0, if so, calculating probability to select whether to accept the new path, and if not, setting the new path as the current path;
And the optimal solution path planning module is used for selecting an optimal combination from all the combinations after iteration is completed as a current optimal solution path.
7. A computer storage medium having stored thereon a computer program, characterized in that the computer program, when executed, implements the chip sorting optimization method of any of claims 1-5.
CN202410161781.6A 2024-02-05 2024-02-05 Chip sorting optimization method, system and storage medium Active CN117708549B (en)

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