CN117708036A - AT instruction processing method and device, terminal and terminal equipment - Google Patents
AT instruction processing method and device, terminal and terminal equipment Download PDFInfo
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Abstract
The invention provides an AT instruction processing method, an AT instruction processing device, a terminal and terminal equipment, and relates to the technical field of communication. The method comprises the following steps: matching a received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT characteristic set; determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction; and executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result. According to the scheme, the AT instruction execution and the physical serial port decoupling are realized by matching the first AT instruction to the virtual data verification interface; and providing uniform interfaces for different platforms, and eliminating the platform correlation of the AT instruction codes. The method solves the problems that AT instruction codes on different platforms are required to be independently developed and the code reusability for serving the AT instructions is poor.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a terminal, and a terminal device for processing an AT instruction.
Background
Because the software architecture of each chip provider is different, the AT instruction processing methods are different, and the baseband chip formats provided by different providers are also different, if the AT instruction codes need to be repeatedly rewritten on each chip along the AT processing architecture for the same platform, the AT instruction codes comprise core codes and AT logic codes on the service side. The AT command cannot be standardized from the root, and the compatibility of the AT command on different modules cannot be ensured; meanwhile, if the AT processing architecture of different platforms is adopted, AT instruction codes on different platforms are required to be independently developed, the code reusability for serving the AT instruction is poor, the development period is longer, and the maintenance difficulty is higher.
Disclosure of Invention
The invention aims to provide an AT instruction processing method, an AT instruction processing device, a terminal and terminal equipment, which are used for solving the problems that AT instruction codes on different platforms in the prior art all need to be independently developed and the code multiplexing property for serving the AT instruction is poor.
To achieve the above object, an embodiment of the present invention provides an AT instruction processing method, including:
matching a received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT characteristic set;
determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction;
and executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
Further, before matching the received first AT instruction with the hash list, the method includes:
receiving an AT instruction set in a preset format;
acquiring prefix information of each AT instruction in the AT instruction set in the preset format, and determining an AT feature set according to the prefix information;
generating the hash list and a first hash algorithm according to the AT characteristic set;
and loading the data information of the AT instruction set with the preset format into the hash list.
Further, before matching the received first AT instruction with the hash list, the method further includes:
and generating AT least one data check interface and AT least one data structure according to the AT characteristic set.
Further, the AT instruction in the preset format AT instruction set includes:
prefix information and data information;
wherein the data information includes at least one of: instruction type, instruction entry, parameter type, parameter range, and default specification.
Further, the matching the received first AT instruction with the hash list to obtain a target AT instruction matched with the first AT instruction includes:
calculating an instruction prefix of the first AT instruction through the first hash algorithm to obtain a calculation result;
and comparing the calculation result with the hash list, and determining a target AT instruction corresponding to the hash value matched with the calculation result in the hash list.
Further, the determining, through a target data check interface corresponding to the target AT instruction, the type and parameter information of the first AT instruction includes:
determining a target data verification interface corresponding to the target AT instruction according to the AT least one data verification interface;
determining a target data structure corresponding to the target data verification interface;
and carrying out parameter verification on the first AT instruction through the target data structure to obtain the type and parameter information of the first AT instruction.
To achieve the above object, an embodiment of the present invention further provides an AT instruction processing apparatus, including:
the matching module is used for matching the received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT feature set;
the determining module is used for determining the type and parameter information of the first AT instruction through a target data checking interface corresponding to the target AT instruction;
and the execution module is used for executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
To achieve the above object, an embodiment of the present invention also provides a terminal including a processor and a transceiver, wherein,
the transceiver is used for matching a received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT characteristic set;
the processor is used for determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction;
and executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
To achieve the above object, an embodiment of the present invention further provides a terminal device, including a transceiver, a processor, a memory, and a program or instructions stored on the memory and executable on the processor; the processor, when executing the program or instructions, implements the AT instruction processing method as described above.
To achieve the above object, an embodiment of the present invention provides a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps in the AT instruction processing method as described above.
The technical scheme of the invention has the following beneficial effects:
the AT instruction processing method of the embodiment of the invention matches the received first AT instruction with the hash list, determines a target data check interface corresponding to the target AT instruction after determining the target AT instruction, and further determines the type and parameter information of the first AT instruction; and executing the first AT instruction according to the type and parameter information of the first AT instruction. According to the scheme, the virtual data verification interface is matched according to the first AT instruction, and the AT instruction is decoupled from the physical serial port through the execution of the AT instruction, so that the virtual calling of the AT instruction can be realized. And providing interfaces with unified specifications for different platforms, and eliminating the platform correlation of service side codes. The method solves the problems that in the prior art, AT instruction codes on different platforms are required to be independently developed and the code reusability of serving AT instructions is poor.
Drawings
Fig. 1 is a flow chart of an AT instruction processing method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of preprocessing an AT instruction set with a preset format according to an embodiment of the present invention;
fig. 3 is a logic diagram of an AT instruction processing method according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a framework for executing an AT instruction processing method according to an embodiment of the present invention;
FIG. 5 is a block diagram illustrating an AT command processing apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a terminal according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In various embodiments of the present invention, it should be understood that the sequence numbers of the following processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
In addition, the terms "system" and "network" are often used interchangeably herein.
In the examples provided herein, it should be understood that "B corresponding to a" means that B is associated with a from which B may be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.
As shown in fig. 1, an AT instruction processing method in an embodiment of the present invention includes the following steps:
step 101, matching a received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is pre-generated according to an AT feature set.
And 102, determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction.
And step 103, executing the first AT instruction according to the type and parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
Optionally, executing the first AT instruction according to the type and parameter information of the first AT instruction, including:
and acquiring a target execution strategy according to the type of the first AT instruction, and processing the parameter information according to the target execution strategy.
In an embodiment of the invention, after receiving a first AT instruction, a communication module matches in a hash list through a hash algorithm, and after matching a target AT instruction, the communication module brings tail data of the first AT instruction into a target data checking interface corresponding to the target AT instruction to obtain type and parameter information of the first AT instruction; and executing the first AT instruction (processing data corresponding to the parameter information in an entity function) according to the type of the first AT instruction, obtaining an execution result and outputting the execution result in a parameter-out form. The AT instruction processing method provided by the embodiment of the invention can realize the virtual call (non-serial port call, namely virtual AT channel) of the AT instruction. And (3) normalizing the parameter processing process, eliminating the chip interface difference, realizing transmission modes such as a transparent transmission mode, a data mode, an escape character string, a Json character string and the like, and decoupling an AT instruction and a serial port component.
The AT instruction processing method of the embodiment of the invention matches the received first AT instruction with the hash list, determines a target data check interface corresponding to the target AT instruction after determining the target AT instruction, and further determines the type and parameter information of the first AT instruction; and executing the first AT instruction according to the type and parameter information of the first AT instruction. According to the scheme, the virtual data verification interface is matched according to the first AT instruction, and the AT instruction is decoupled from the physical serial port through the execution of the AT instruction, so that the virtual calling of the AT instruction can be realized. And providing interfaces with unified specifications for different platforms, and eliminating the platform correlation of service side codes. The method solves the problems that in the prior art, AT instruction codes on different platforms are required to be independently developed and the code reusability of serving AT instructions is poor.
Optionally, before matching the received first AT instruction with the hash list, the method includes:
receiving an AT instruction set in a preset format;
acquiring prefix information of each AT instruction in the AT instruction set in the preset format, and determining an AT feature set according to the prefix information;
generating the hash list and a first hash algorithm according to the AT characteristic set;
and loading the data information of the AT instruction set with the preset format into the hash list.
Optionally, the generating the hash list according to the AT feature set includes:
and carrying out hash calculation on prefix information of each AT instruction in the AT characteristic set, and generating the hash list according to a calculation result.
Optionally, the loading the data information of the AT instruction set in the preset format into the hash list includes:
matching data information of the AT instructions in the AT instruction set with the preset format with hash values in the hash list;
the data information of each AT instruction is matched with the hash value corresponding to the prefix information of the AT instruction.
In an embodiment of the present invention, the AT instruction set in a preset format may be an AT instruction set stored in an XML file format, where the XML file format includes: an instruction prefix, an instruction type, an instruction entry, a parameter type, a parameter range, a default specification, etc. of the AT instruction; meanwhile, a Python parser can be adopted to import the AT instruction set in the preset format, and according to the received XML file identification description information, a parameter specification list (comprising various data structures) and a parameter verification interface are automatically generated, a source file is created to store the corresponding data structure and interface, and meanwhile, the instruction prefix is extracted to form an AT feature set.
According to the AT instruction processing method, a large number of AT parameter check codes can be automatically generated through a preprocessing flow in an XML file description mode, so that the development process of AT instructions is simplified, the input and output of the AT instructions are standardized, and the mutual compatibility of the AT instructions among modules is ensured.
As shown in fig. 2, in an embodiment of the present invention, a received set of AT instructions in a preset format needs to be preprocessed before matching the received first AT instruction with the hash list:
after receiving an AT instruction set in a loaded XML file format, generating an AT feature set according to prefix information of each AT instruction in the AT instruction set;
AT least one data check interface, AT least one data structure, a hash list, and a first hash algorithm MPHF are generated from the AT feature set.
In an embodiment of the present invention, a hash list (minimum perfect hash list) and a first hash algorithm are generated according to the AT feature set; and loading data information in the AT instruction set into the hash list. The spatial complexity of the AT information store does not change relative to the sequence table, does not increase the overhead of the embedded system, reduces the average time complexity of AT instruction matching from O (n) to O (1), and does not change with an increase in the number of AT instructions.
Optionally, before matching the received first AT instruction with the hash list, the method further includes:
and generating AT least one data check interface and AT least one data structure according to the AT characteristic set.
It should be noted that, the data checking interface is a virtual interface.
According to the AT instruction processing method, the parameter checking interface is generated in advance, the development flow of the AT instruction is simplified, and the excitation response of the system is standardized. The AT commands among different communication modules can be mutually compatible and used instead.
Optionally, the AT instruction in the AT instruction set in the preset format includes:
prefix information and data information;
wherein the data information includes at least one of: instruction type, instruction entry, parameter type, parameter range, and default specification.
Optionally, the matching the received first AT instruction with the hash list to obtain a target AT instruction matched with the first AT instruction includes:
calculating an instruction prefix of the first AT instruction through the first hash algorithm to obtain a calculation result;
and comparing the calculation result with the hash list, and determining a target AT instruction corresponding to the hash value matched with the calculation result in the hash list.
According to the AT instruction processing method, the hash algorithm is adopted for AT instruction matching, so that the average time of AT instruction inquiry is reduced, the matching time is not changed along with the quantity of data information carried in the AT instruction, and the processing efficiency of the AT instruction is further improved.
Optionally, the determining, through a target data check interface corresponding to the target AT instruction, the type and parameter information of the first AT instruction includes:
determining a target data verification interface corresponding to the target AT instruction according to the AT least one data verification interface;
determining a target data structure corresponding to the target data verification interface;
and carrying out parameter verification on the first AT instruction through the target data structure to obtain the type and parameter information of the first AT instruction.
Optionally, parameter verification is performed on the first AT instruction through the target data structure on the target data verification interface.
The AT instruction processing method provided by the embodiment of the invention is only matched with a virtual data checking interface, the execution process is isolated from a port, the decoupling of AT instruction execution and a physical serial port is realized, the interface with unified specification is provided for different platforms, and the platform correlation of service side codes is eliminated. The method solves the problems that in the prior art, AT instruction codes on different platforms are required to be independently developed and the code reusability of serving AT instructions is poor.
As shown in fig. 3, logic of an AT instruction processing method according to an embodiment of the present invention:
inputting an AT command AT a port of the communication module;
reading an instruction prefix of the AT instruction and matching the instruction prefix in an AT hash list;
after matching to the target AT instruction, determining a target data check interface and a target data structure;
parameter verification is carried out on the driller AT instruction through a target data structure AT a target data verification interface, and the type and parameter information of the first AT instruction are obtained;
after the parameter verification is successful, determining an execution strategy according to the target data verification interface, and executing the first AT instruction;
and obtaining an execution result, and outputting the execution result in a parameter-output form.
It should be noted that, the AT instruction processing method in the embodiment of the present invention may be implemented by the following architecture:
the communication module comprises a platform layer, an abstract interface layer, an AT service layer and a service layer, as shown in figure 4.
Specifically, in an embodiment of the present invention, the software of the communication module is evolved from the original 2-layer structure (platform layer and AT layer) to the 4-layer structure. When the code of the AT instruction is developed on different chip platforms, only an abstract interface layer is required to be adapted, and both the AT service layer and the service layer can be directly multiplexed.
According to the communication module provided by the embodiment of the invention, the service side codes are decoupled from the chip platform through the core ideas of software layering, dependence inversion and the like, so that the cohesiveness of the service side codes is improved. The method can realize the good cross-platform characteristic of AT command processing, and when a new communication module is developed, a developer only needs to realize board-level adaptation of an abstract interface, and upper-layer codes can be directly multiplexed.
Optionally, performing parameter verification on the first AT instruction through the abstract interface layer;
the AT log track in the received preset format is subjected to the pretreatment through the AT service layer;
and executing the first AT instruction according to the type and the parameter information of the first AT instruction through the service layer.
Abstract the AT layer dependence inversion principle to an abstract interface layer, and provide chip platform board level adaptation and business layer interface dependence:
in an embodiment of the present invention, the abstract interface layer includes: at least one of a CMOS interface, an Asyn Socket interface, an Asyn DNS interface, an Asyn SSL interface, a general interface and the like;
the CMOS interface is a formulated CMOS standard interface, and is used for shielding the use difference of an operating system, a memory stack and the like, so that decoupling of the original system and the application program is realized, and the cohesiveness of the application program is improved;
the method comprises the steps of uniformly realizing an asynchronous Socket and an abstract interface, realizing a Socket, an encryption and decryption asynchronous event driven model and asynchronous domain name resolution at an Asyn Socket interface, an Asyn DNS interface and an Asyn SSL interface; meanwhile, the abstract interfaces provide standard asynchronous processing access for application layer data services, so that the problems of thread resource consumption, power consumption increase and the like caused by a blocking mode under the condition of multiple services are avoided;
by abstracting the hardware interface and the universal interface, the platform correlation of the application program, such as input and output of a serial port, access of a file system and the like, is thoroughly relieved.
In an embodiment of the invention, the APP program of the AT service layer adopts a policy mode, virtual APP management execution policy is obtained, service layer codes meeting the policy can be replaced AT any time, the coupling between the AT service layer and the service layer is reduced, and the functions of the AT layer APP and the service layer can be used simultaneously.
In an embodiment of the present invention, the service side code (AT instruction code of the service layer) depends on the basic abstract interface, and may be placed in the GitLab server in a packet management mode for unified iterative maintenance. Only board-level adaptation of an abstract interface layer is needed to be completed when communication module software is developed, and after a target parameter checking interface is determined, an AT service side code is acquired from a GitLab warehouse according to the target parameter checking interface as required. The AT instruction processing method of the embodiment of the invention standardizes the excitation response behavior of the AT system, improves the reusability of codes and ensures the compatibility and the replaceability among modules.
As shown in fig. 5, an embodiment of the present invention further provides an AT instruction processing apparatus 500, including:
the matching module 501 is configured to match a received first AT instruction with a hash list, to obtain a target AT instruction matched with the first AT instruction, where the hash list is generated in advance according to an AT feature set;
a determining module 502, configured to determine, through a target data check interface corresponding to the target AT instruction, type and parameter information of the first AT instruction;
and the executing module 503 is configured to execute the first AT instruction according to the type and parameter information of the first AT instruction, obtain an execution result, and output the execution result.
The AT instruction processing device provided by the embodiment of the invention matches the received first AT instruction with the hash list, determines a target data verification interface corresponding to the target AT instruction after determining the target AT instruction, and further determines the type and parameter information of the first AT instruction; and executing the first AT instruction according to the type and parameter information of the first AT instruction. According to the scheme, the virtual data verification interface is matched according to the first AT instruction, and the AT instruction is decoupled from the physical serial port through the execution of the AT instruction, so that the virtual calling of the AT instruction can be realized. And providing interfaces with unified specifications for different platforms, and eliminating the platform correlation of service side codes. The method solves the problems that in the prior art, AT instruction codes on different platforms are required to be independently developed and the code reusability of serving AT instructions is poor.
Optionally, the AT instruction processing apparatus further includes:
the receiving module is used for receiving an AT instruction set in a preset format;
the acquisition module is used for acquiring prefix information of each AT instruction in the AT instruction set in the preset format, and determining an AT characteristic set according to the prefix information;
the first generation module is used for generating the hash list and a first hash algorithm according to the AT characteristic set;
and the loading module is used for loading the data information of the AT instruction set with the preset format into the hash list.
Optionally, the AT instruction processing apparatus further includes:
and the second generation module is used for generating AT least one data check interface and AT least one data structure according to the AT characteristic set.
Optionally, the matching module is further configured to:
calculating an instruction prefix of the first AT instruction through the first hash algorithm to obtain a calculation result;
and comparing the calculation result with the hash list, and determining a target AT instruction corresponding to the hash value matched with the calculation result in the hash list.
Optionally, the determining module is further configured to:
determining a target data verification interface corresponding to the target AT instruction according to the AT least one data verification interface;
determining a target data structure corresponding to the target data verification interface;
and carrying out parameter verification on the first AT instruction through the target data structure to obtain the type and parameter information of the first AT instruction.
As shown in fig. 6, a mobile terminal 600 of an embodiment of the present invention includes a processor 610 and a transceiver 620, wherein,
the transceiver is used for matching a received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT characteristic set;
the processor is used for determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction;
and executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
A terminal device according to another embodiment of the present invention, as shown in fig. 7, includes a transceiver 710, a processor 700, a memory 720, and a program or instructions stored on the memory 720 and executable on the processor 700; the processor 700, when executing the program or instructions, implements the above-described methods for AT instruction processing.
The transceiver 710 is configured to receive and transmit data under the control of the processor 700.
Wherein in fig. 7, a bus architecture may comprise any number of interconnected buses and bridges, and in particular one or more processors represented by processor 700 and various circuits of memory represented by memory 720, linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. The transceiver 710 may be a number of elements, i.e. comprising a transmitter and a receiver, providing a unit for communicating with various other apparatus over a transmission medium. The user interface 730 may also be an interface capable of interfacing with an inscribed desired device for a different user device, including but not limited to a keypad, display, speaker, microphone, joystick, etc.
The processor 700 is responsible for managing the bus architecture and general processing, and the memory 720 may store data used by the processor 700 in performing operations.
The readable storage medium of the embodiment of the present invention stores a program or an instruction, which when executed by a processor, implements the steps in the AT instruction processing method described above, and can achieve the same technical effects, and is not described herein again for avoiding repetition.
Wherein the processor is a processor in the terminal device described in the above embodiment. The readable storage medium includes a computer readable storage medium such as a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a magnetic disk or an optical disk.
It is further noted that the terminals described in this specification include, but are not limited to, smartphones, tablets, etc., and that many of the functional components described are referred to as modules in order to more particularly emphasize their implementation independence.
In an embodiment of the invention, the modules may be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different bits which, when joined logically together, comprise the module and achieve the stated purpose for the module.
Indeed, a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Likewise, operational data may be identified within modules and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices.
Where a module may be implemented in software, taking into account the level of existing hardware technology, a module may be implemented in software, and one skilled in the art may, without regard to cost, build corresponding hardware circuitry, including conventional Very Large Scale Integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components, to achieve the corresponding functions. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
The exemplary embodiments described above are described with reference to the drawings, many different forms and embodiments are possible without departing from the spirit and teachings of the present invention, and therefore, the present invention should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the drawings, the size of the elements and relative sizes may be exaggerated for clarity. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise indicated, a range of values includes the upper and lower limits of the range and any subranges therebetween.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (10)
1. An AT instruction processing method, comprising:
matching a received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT characteristic set;
determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction;
and executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
2. The AT instruction processing method of claim 1, wherein before matching the received first AT instruction with the hash list, comprising:
receiving an AT instruction set in a preset format;
acquiring prefix information of each AT instruction in the AT instruction set in the preset format, and determining an AT feature set according to the prefix information;
generating the hash list and a first hash algorithm according to the AT characteristic set;
and loading the data information of the AT instruction set with the preset format into the hash list.
3. The AT instruction processing method of claim 2, further comprising, before matching the received first AT instruction with the hash list:
and generating AT least one data check interface and AT least one data structure according to the AT characteristic set.
4. The AT instruction processing method according to claim 2 or 3, wherein the AT instructions in the AT instruction set in the preset format include:
prefix information and data information;
wherein the data information includes at least one of: instruction type, instruction entry, parameter type, parameter range, and default specification.
5. The AT instruction processing method according to claim 2, wherein the matching the received first AT instruction with the hash list to obtain the target AT instruction matched with the first AT instruction includes:
calculating an instruction prefix of the first AT instruction through the first hash algorithm to obtain a calculation result;
and comparing the calculation result with the hash list, and determining a target AT instruction corresponding to the hash value matched with the calculation result in the hash list.
6. The AT instruction processing method according to claim 3, wherein the determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction includes:
determining a target data verification interface corresponding to the target AT instruction according to the AT least one data verification interface;
determining a target data structure corresponding to the target data verification interface;
and carrying out parameter verification on the first AT instruction through the target data structure to obtain the type and parameter information of the first AT instruction.
7. An AT instruction processing apparatus, comprising:
the matching module is used for matching the received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT feature set;
the determining module is used for determining the type and parameter information of the first AT instruction through a target data checking interface corresponding to the target AT instruction;
and the execution module is used for executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
8. A terminal, comprising: a transceiver and a processor;
the transceiver is used for matching a received first AT instruction with a hash list to obtain a target AT instruction matched with the first AT instruction, wherein the hash list is generated in advance according to an AT characteristic set;
the processor is used for determining the type and parameter information of the first AT instruction through a target data check interface corresponding to the target AT instruction;
and executing the first AT instruction according to the type and the parameter information of the first AT instruction, obtaining an execution result and outputting the execution result.
9. A terminal device, comprising: a transceiver, a processor, a memory, and a program or instructions stored on the memory and executable on the processor; the AT instruction processing method according to any one of claims 1 to 6, characterized in that the processor implements the AT instruction processing method when executing the program or instructions.
10. A readable storage medium having stored thereon a program or instructions which when executed by a processor realizes the steps in the AT instruction processing method according to any of claims 1-6.
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|---|---|---|---|
| CN202211100387.9A CN117708036A (en) | 2022-09-08 | 2022-09-08 | AT instruction processing method and device, terminal and terminal equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211100387.9A CN117708036A (en) | 2022-09-08 | 2022-09-08 | AT instruction processing method and device, terminal and terminal equipment |
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| CN117708036A true CN117708036A (en) | 2024-03-15 |
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