CN117708032A - Multichannel synchronous parallel I2C communication method, system and electronic equipment - Google Patents

Abstract

The application discloses a multichannel synchronous parallel I2C communication method, a multichannel synchronous parallel I2C communication system and electronic equipment, wherein the method comprises the steps of counting according to a preselected clock signal in a preset counting period, and comparing a current counting value with at least three preset sub-target numbers respectively to generate trigger signals; simulating a plurality of I2C bus channels by using a GPIO interface, wherein the bit period of I2C communication comprises at least three phase points; acquiring data pre-written to the GPIO interface at a first phase point according to a first trigger signal and storing the data into an output data memory of the GPIO interface; acquiring data pre-written to the GPIO interface at a second phase point according to the second trigger signal and storing the data into an output data memory of the GPIO interface; and the data read by the input data memory of the GPIO interface is according to the third trigger signal. And the synchronous communication of multiple paths of I2C bus channels simulated by GPIO interfaces is realized, so that the CPU resource occupation is greatly reduced.

Description

Multichannel synchronous parallel I2C communication method, system and electronic equipment

Technical Field

The application belongs to the technical field of data communication, and particularly relates to a multichannel synchronous parallel I2C communication method, a multichannel synchronous parallel I2C communication system and electronic equipment.

Background

I2C communication is one of the most basic communication methods for communication between devices, and plays an extremely important role in electronic systems. It is widely used in various electronic systems such as: industrial automation, medical, consumer, test measurement, etc. In these systems, a scenario is included in which an I2C master communicates with a single or multiple I2C slaves. For example, a CPU serves as an I2C master device, and is connected to various I2C slave devices, including various I2C interface sensors, ADCs, DACs, and the like. I2C plays an irreplaceable role as a communication bridge between the master device and the slave device.

However, I2C communication has many limitations in many applications. For example, an ADC, DAC and sensor with multiple I2C interfaces are mounted in one MCU system. To communicate synchronously with all I2C devices, it is difficult to use a common scheme, and synchronization is a typical requirement in test measurement and industrial control. The conventional I2C operation method is serial asynchronous communication to implement multi-channel data measurement, and each I2C device communicates sequentially. Additional phase compensation is often required to solve the synchronization problem, which is not only difficult, but also not usable in all systems. Another limitation of I2C communication is that I2C devices are low-speed devices, which have the problem of occupying high-speed device bandwidth in communicating with high-speed devices. For example, the CPU runs a real-time operating system, and the I2C communication thread occupies the CPU for a long time, reducing the running efficiency of the system.

In the field of test measurement, increasing the number of DUTs measured simultaneously is a major means of reducing the measurement effort. Increasing the number of measurement channels for the device under test of the I2C interface is also an urgent issue to be addressed.

Disclosure of Invention

The technical purpose is that: the application aims to provide a multichannel synchronous parallel I2C communication method which is used for realizing multichannel synchronous parallel I2C interface communication without occupying high-speed equipment for a long time.

In order to achieve the technical purpose, the following technical scheme is adopted in the application.

In a first aspect, an embodiment of the present application provides a multi-channel synchronous parallel I2C communication method, including:

counting according to a preselected clock signal in a preset counting period to obtain a current count value;

comparing the current count value with at least three preset sub-target numbers respectively to obtain comparison results, and generating at least three corresponding trigger signals respectively according to the comparison results;

simulating a multipath I2C bus channel by using a GPIO interface, wherein the bit period of I2C communication comprises at least three phase points, the phase points are in one-to-one correspondence with the sub-target numbers, the first phase point is positioned at the beginning of the bit period, the second phase point is positioned at the signal rising edge of an I2C clock line in the bit period, and the third phase point is positioned at the signal high level of the I2C clock line in the bit period;

acquiring data pre-written to a GPIO interface at a first phase point according to a first trigger signal, and storing the data into an output data memory of the GPIO interface; acquiring data which is written into the GPIO interface at the second phase point according to the second trigger signal, and storing the data into an output data memory of the GPIO interface; and according to the third trigger signal, reading data from an input data memory of the GPIO interface at the third phase point and storing the data in a designated area.

In a second aspect, embodiments of the present application provide a multi-channel synchronous parallel I2C communication system, including:

the counting module counts according to a preselected clock signal in a preset counting period to obtain a current count value;

the comparison module is used for comparing the current count value with at least three preset sub-target numbers respectively to obtain comparison results, and generating at least three corresponding trigger signals according to the comparison results;

the GPIO interface is used for simulating a multipath I2C bus channel, the bit period of I2C communication comprises at least three phase points, the phase points are in one-to-one correspondence with the sub-target numbers, wherein the first phase point is positioned at the beginning of the bit period, the second phase point is positioned at the signal rising edge of an I2C clock line in the bit period, and the third phase point is positioned at the signal high level of the I2C clock line in the bit period;

the direct access storage module is used for acquiring data which is written into the GPIO interface at the first phase point in advance according to the first trigger signal and storing the data into an output data memory of the GPIO interface; acquiring data pre-written to the GPIO interface at a second phase point according to the second trigger signal and storing the data into an output data memory of the GPIO interface; and according to the third trigger signal, reading data from an input data memory of the GPIO interface at the third phase point and storing the data in a designated area.

In a third aspect, an embodiment of the present application provides an electronic device, including: a multi-channel synchronous parallel I2C communication system as provided by any one of the possible embodiments of the second aspect.

The beneficial effects are that: compared with the prior art, the multichannel synchronous parallel I2C communication method provided by the embodiment of the application has the advantages that at least three sub-target numbers related to the bit period of the I2C bus are preset, the three sub-target numbers are respectively related to three phase points on the bit period of the I2C communication, and jump of a clock line and a data line of the I2C bus can be determined according to the three pre-determined sub-target numbers. The current count value is compared with the three sub-target numbers to generate corresponding trigger signals, the data of each path of I2C bus channel is synchronously transmitted to the data output register of the GPIO interface at the first phase point and the second phase point, the signals on the data line of each path of I2C bus channel are read out from the data input register of the GPIO interface at the third phase point, the communication protocol of the I2C bus is simulated by controlling the level change of the GPIO interface, the synchronous communication of multiple paths of I2C bus channels simulated by the GPIO interface is realized, and the occupation of CPU resources is greatly reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an NCA9548 multi-channel I2C application circuit;

FIG. 2 is a schematic diagram of an FPGA/CPLD multichannel I2C application;

fig. 3 is a schematic flow chart of a multi-channel synchronous parallel I2C communication method according to a first embodiment of the present application;

fig. 4 is a schematic diagram of dividing each phase point in a multi-channel synchronous parallel I2C communication method according to a first embodiment of the present application;

FIG. 5 is a waveform diagram of write operation timing of a multi-channel synchronous parallel I2C communication method according to an embodiment of the present application;

FIG. 6 is a waveform diagram of a read operation timing sequence of a multi-channel synchronous parallel I2C communication method according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a multi-channel synchronous parallel I2C communication system according to a second embodiment of the present application;

reference numerals:

the system comprises a 1-multichannel synchronous parallel I2C communication system, an 11-counting module, a 12-comparing module, a 13-direct access storage module, a 14-GPIO interface, a 111-automatic reload register, a 112-timer, a 121-first comparing register, a 122-second comparing register, a 123-third comparing register, a 131-first direct access storage unit, a 132-second direct access storage unit, a 133-third direct access storage unit, a 141-output data storage, a 142-input data storage, a 143-GPIO pin, a 151-first write data storage unit, a 152-second write data storage unit, a 161-read data storage module, a 101-first sub-target number, a 102-second sub-target number, a 103-third sub-target number, a 104-first trigger signal, a 105-second trigger signal and a 106-third trigger signal.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein.

Furthermore, it should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

I2C (Inter-Integrated Circuit) is a serial communication protocol for communication between devices in a digital system. The I2C bus consists of two signal lines: SCL (clock line) and SDA (data line). SCL is controlled by a Master device (Master) for providing a clock signal. SDA is used to transfer data between a master device and a Slave device (Slave).

Each device connected to the bus has an independent address with which the host can access between different devices. The I2C bus is designed with an open drain, and the bus is connected to the power supply through a pull-up resistor (the pull-up resistor is typically 4.7 k). When the IC device is idle, a high resistance state is output, and when all devices are idle, the high resistance state is output, and the bus is pulled to be high level by the pull-up resistor.

To facilitate an understanding of the present application, the I2C protocol is briefly described below.

The SDA and SCL signal lines of the I2C bus are simultaneously out of high, and are defined as idle state of the bus. At this time, the output stage field effect transistors of the devices are in an off state, namely the bus is released, and the level is pulled up by the pull-up resistors of the two signal lines.

During the period when SCL is high, SDA jumps from high to low, and the IIC bus is the start signal. The start signal and stop signal are typically generated by the host. When SCL is a high level device, the SDA transitions from low to high to a stop signal.

The master device will send a device address to select the slave device to communicate upon initiation of the communication. The device address is a unique identification of the slave devices, each slave device having a unique address. After sending the device address, the master device will send a read/write bit to indicate the direction of the communication. The read bit indicates that the master device is to read data from the slave device and the write bit indicates that the master device is to send data to the slave device. After the device address and the read-write bits, data transfer between the master and slave devices is possible. Data is transmitted through the SDA line, with each data byte being transmitted at an edge of the clock. The master and slave synchronize data transmissions by control of a clock signal. After each data byte transmission is completed, the recipient sends an acknowledgement bit (ACK) to acknowledge receipt of the data. The ACK bit is sent by the recipient pulling SDA low when SCL is low, indicating that data was received.

For the method of expanding the multi-channel I2C, as shown in fig. 1, in the prior art, a CPU or MCU is used as an I2C communication master device, and data communication of the multi-channel I2C device is realized through analog switch switching or an I2C HUB chip such as NCA 9548. According to the scheme, a channel required to perform data test measurement is selected according to a communication protocol specified by NCA9548, so that I2C multi-channel test measurement in a serial mode can be realized.

The scheme shown in fig. 1 only solves the problem of multi-channel expansion, and the scheme needs to set an I2C expansion chip first, select a channel needing to be communicated, and perform I2C data test measurement normally, so that the data test measurement can be performed only in a serial mode, not only occupies a large amount of resources of a CPU, but also has slower communication efficiency, and is difficult to realize multi-channel synchronous data test measurement.

The existing method for expanding the multi-channel I2C further comprises a scheme shown in fig. 2, wherein the scheme takes an FPGA or a CPLD as an I2C multi-channel communication management platform, and establishes IIC connection with a communication slave device through a preset IO interface, so that data information can be synchronously acquired in parallel and stored in a preset storage medium. As shown in FIG. 2, the FPGA/CPLD can conveniently process and collect information by using the coding program, and the IO port of the FPGA/CPLD supports a plurality of levels, can be connected with other devices with different levels, and is also convenient for testers to test IIC communication and Debug.

However, the scheme FPGA/CPLD shown in fig. 2 is a platform, the system is relatively complex, the reliability cannot be effectively ensured, and the cost is high, so that the system is not suitable for large-scale batch test.

Embodiments of the present application will be described in detail below with reference to the drawings attached to the specification.

Example 1

The embodiment provides a multichannel synchronous parallel I2C communication method, which comprises the following steps:

step S101: and counting according to the preselected clock signal in a preset counting period to obtain a current count value.

Step S102: and comparing the current count value with at least three preset sub-target numbers respectively to obtain comparison results, and generating at least three corresponding trigger signals respectively according to the comparison results.

Step S103: the GPIO interface is utilized to simulate a multipath I2C bus channel, the bit period of I2C communication comprises at least three phase points, the phase points are in one-to-one correspondence with the sub-target numbers, wherein the first phase point is positioned at the starting position of the bit period, the second phase point is positioned at the rising edge of a signal of an I2C clock line in the bit period, and the third phase point is positioned at the high level of the signal of the I2C clock line in the bit period.

Acquiring data pre-written to the GPIO interface at a first phase point according to a first trigger signal and storing the data into an output data memory of the GPIO interface; acquiring data pre-written to the GPIO interface at a second phase point according to the second trigger signal and storing the data into an output data memory of the GPIO interface; and reading data from the input data memory of the GPIO interface at a third phase point according to the third trigger signal and storing the data in the designated area.

In step S101, counting may be performed by a timer. As an example, step S101 includes: counting the preselected clock by using a timer to obtain a current count value; the counting period of the timer is a bit period of I2C communication, and when the timing time reaches the bit period, the current counting value in the timer is automatically cleared to perform the timing of the next counting period.

In particular embodiments, the preselected clock may be a high-speed clock, which may be an internal clock of a high-speed device (e.g., MCU).

The timer period of the timer is the length of time that the timer is given to complete a complete count. The timing period of the timer is equal to the period corresponding to the frequency of the I2C communication, i.e. the timing period of the timer is determined as the bit period of the I2C communication. In I2C communication, a bit period (bit period) of I2C communication refers to a time required to transmit one bit (bit).

It will be appreciated that a timer is pre-configured, which is not an inventive point of the present application and will not be described in detail.

At least three preset sub-target numbers in step S102 are related to the bit period of the I2C bus, the three sub-target numbers are related to three phase points on the bit period, and the transitions of the clock line and the data line of the I2C bus can be determined according to the three preset sub-target numbers.

For step S103, as illustrated in fig. 4, each bit period is divided into three phase (phase) points, a first phase point phase0, a second phase point phase1, and a third phase point phase2, as an example. The first phase point phase0 is located at the beginning of the bit period, the second phase point phase1 is located at the rising edge of the signal of the I2C clock line of the bit period, and the third phase point phase2 is located at the high level of the signal of the I2C clock line of the bit period. In this embodiment, SCL and SDA are written at one phase point phase0, SCL is written at the second phase point phase1, and data is read from the data line SDA at the third phase point phase2. It will be appreciated that while the second phase point phase1 is writing SCL, SDA is also being written, which requires the data of the first phase point phase0 to be maintained.

It will be appreciated that according to the I2C communication protocol, data is transmitted via the SDA line, each data byte being transmitted at an edge of the clock, and therefore the first phase point phase0 and the second phase point phase1 are necessary, and thus the first sub-target number and the second sub-target number of the first phase point phase0 and the second phase point phase1 are also necessary.

In addition, it is necessary to read data from the data line, so that it is also necessary to set the third phase point phase2 at a delay time after the second phase point phase1 for reading data, so that it is also necessary to determine the third sub-target number of the third phase point.

The embodiment of the application adopts the GPIO interface to simulate a plurality of I2C bus channels. The GPIO (General Purpose Input/Output ) interface is a general purpose interface for digital signal interaction with external devices. It can be used to read the state of the external device (input) or to control the state of the external device (output). GPIO interfaces are typically composed of multiple GPIO pins, each of which may be independently configured in either input or output mode and connected to an external device. Each GPIO pin has a corresponding register for controlling and reading its state. The GPIO-IDR (Input Data Register ) is a register in the GPIO interface for reading the state of the input pin. By reading the GPIO-IDR register, the current state of the GPIO pin, i.e., the input state of the external device, can be obtained. The GPIO-ODR (Output Data Register ) is a register in the GPIO interface for writing the state of the output pin. By writing the GPIO-ODR register, the output state of the GPIO pin, namely the state of the external device, can be controlled. Thus, GPIO-IDR and GPIO-ODR are two important registers in the GPIO interface for reading and writing the state of the GPIO pin. Prior to using GPIO-IDR and GPIO-ODR, the associated GPIO pins typically need to be preconfigured, including GPIO mode settings, GPIO speed settings, GPIO pull-up settings, such as GPIO multiplexing function settings (optional), etc.

Optionally, the GPIO interface includes a plurality of GPIO pins, one GPIO pin in the plurality of GPIO pins simulates clock lines of all I2C bus channels, and all remaining GPIO pins or part of the remaining GPIO pins are selected to respectively simulate data lines of all I2C bus channels.

In a specific embodiment, the preset value (i.e. the corresponding sub-target number) of the comparison register is used to compare with the current count value obtained by the timer, and when the current count value exceeds the current count value, a trigger signal is generated. It will be appreciated that the comparison registers need to be preconfigured, which is not the subject of this application and will not be described in detail.

Optionally, acquiring data pre-written to the GPIO interface at the first phase point phase0 according to the first trigger signal by using the direct access memory and storing the data to an output data memory of the GPIO interface; acquiring data pre-written to the GPIO interface at a second phase point phase1 by using the direct access memory according to the second trigger signal and storing the data into an output data memory of the GPIO interface; and the direct access memory is used for reading and storing the data from the input data memory of the GPIO interface at the third phase point phase2 according to the third trigger signal.

Direct access memory (Direct Memory Access, DMA) is a data transfer technique that allows peripherals (e.g., hard disk, network adapter, etc.) to transfer data directly to memory without direct intervention from the CPU. Before directly accessing the memory for reading and writing, the CPU needs to configure the DMA controller to specify a source address (e.g., a peripheral data buffer) and a destination address (e.g., a data buffer in the memory) of the data transfer, and a data length of the transfer. The peripheral device sends a DMA request signal to the DMA controller to request data transmission, and in the application, at least three trigger signals corresponding to at least three phase points in a bit period for determining I2C communication are respectively sent out through the comparison register. After receiving the DMA request signal, the DMA controller directly accesses the peripheral and the memory through the bus, reads data from the buffer area of the peripheral into the memory, or writes data from the memory into the buffer area of the peripheral. This process does not require the intervention of a CPU and the DMA controller directly controls the transfer of data.

It can be understood that the multi-channel synchronous parallel I2C communication method provided by the embodiment of the application can be applied to simulating one I2C channel so as to solve the problem that the current I2C device occupies the bandwidth of the high-speed device when communicating with the high-speed device.

Specifically, taking one path of I2C channel as an example, the write operation timing chart is shown in fig. 5, and the read operation timing chart is shown in fig. 6. When the write operation is needed, waveform data of each path of I2C bus channel is needed to be integrated, namely, each bit of data to be written of I2C serial data to be transmitted is arranged into a phase sequence, according to three trigger signals generated by a timer, the phase sequence data of a first phase point and the phase sequence data of a second phase point are sequentially sent out, data are read from a data line at a third phase point, and after all the sequences corresponding to all bits of the data to be written are transmitted, the complete write operation I2C waveform is sent out. Taking an I2C communication bit period as an example, in which 1 is written to the data line SDA in the I2C communication bit period, for example, SCL of the first phase point (phase 0) is 0, SDA of the first I2C bus channel is 1, and in some embodiments, for example, 15I 2C bus channels are included, and all channels data are consistent, SDA is 1, then the integrated data of the first phase point is: 0xFFFE, 0xFFFE is stored in the first write data storage area memory-send 0. If SCL of the second phase point (phase 1) is 1 and SDA of the 15I 2C bus channels is written with 1, then the integrated second phase point data is: 0xFFFF, which is stored in the second write data storage area memory-send 1. During the writing of data, data is read from SCL, SDA at the third phase (phase 2), at which time the data read at this phase is not of interest.

As shown in fig. 5, the start signal is implemented by two periods (-1 and 0), the first SCL and SDA are both set high, the second SCL is high and SDA is pulled low, representing the start signal of the communication; the write data bit is composed of a period, the state of SCL and SDA in each period is stored in the form of data according to the I2C communication protocol, optionally, the data written in the first phase point to the GPIO interface in advance and the data written in the second phase point to the GPIO interface can be stored in a write data storage area memory-send (which can be stored in the first write data storage area memory-send0 and the second write data storage area memory-send1 respectively), such as a random access memory (Random Access Memory, RAM) and wait for DMA (direct memory access (Direct Memory Access, DMA) to carry the data to the corresponding GPIO-ODR bit, the ACK bit (also called acknowledgement bit or response bit) is composed of a period, the data read from the data line SDA at the second phase point phase2 of the period is used as an ACK signal, if the slave device successfully receives the data or address, it can send a low-level response signal indicating that the reception was successful, if the slave device fails to correctly receive the data or the slave device can not process the data in the periods, and the host cannot not receive the high-level response signal, which can not be used for processing the data in the periods.

As shown in fig. 6, each cycle is divided into three phase (phase) points, the first phase point phase0 is the writing SCL and SDA, and the second phase point phase1 is the writing SCL, it will be understood that while the second phase point phase1 is writing SCL, the writing SDA is also needed, and the SDA needs to hold the data of the first phase point phase 0. The third phase2 is the read data line SDA. When the reading operation is needed, the I2C waveform data is also needed to be integrated, that is, the data sequences read in the first phase point phase0, the second phase point phase1 and the third phase point phase2 are sorted according to a certain rule, so as to obtain the data of the reading operation.

Taking a bit period of I2C communication as an example, data is read from the data line SDA in the bit period, for example, SCL of the first phase point (phase 0) is 0, because the I2C bus is an open drain output, and SDA of all I2C bus channels needs to be written with 1, then the data corresponding to the first phase point is: 0xFFFE, 0xFFFE is stored in the first write data storage area memory-send 0. If SCL of the second phase point (phase 1) is 1, since the I2C bus is an open drain output, SDA of all I2C bus channels needs to write 1, then the integrated data of the second phase point is: 0xFFFF, which is stored in the second write data storage area memory-send 1. The third phase point is to read data from the SDA and store the read data in a read register memory-receiver.

As shown in fig. 6, the start signal is implemented by two periods (-1 and 0), the first SCL and SDA are both set high, the second SCL is high and SDA is pulled low, representing the start signal of the communication; the writing data bit consists of a period, according to an I2C communication protocol, the state of SCL and SDA in each period is stored in a memory-send of the writing data storage area in the form of data, and DMA is waited to carry the data to the corresponding GPIO-ODR bit; the read data bit consists of a period, and in the period, the SDA state obtained by the third phase point phase2 is stored into a read data memory-receiver in a data form; the ACK bit consists of a period, and the data read from the data line SDA by the third phase point phase2 of the period is used as an ACK signal; the nop signal is mainly used to distinguish between byte data, during which period both SCL and SDA are pulled low.

When synchronous parallel I2C communication is needed, a timer is started to count to obtain a current count value, when the current count value reaches a first sub-target number, a first trigger signal (corresponding to a first phase point phase 0) is sent, and the first direct access memory DMA1 takes out data to be sent from a memory-send and conveys the data to a corresponding GPIO-ODR (SCL & SDA) bit, so that the effect of simulating IO port operation is achieved. When the second sub-target number is reached, a first trigger signal (corresponding to a second phase point phase 1) is sent, the second direct access memory DMA2 fetches the data to be sent from the memory-send to the corresponding GPIO-ODR (SCL) bit, and when the third sub-target number is reached, a third trigger signal (corresponding to a third phase point phase 2) is sent, the third direct access memory DMA3 receives the data from the GPIO-IDR (SDA) and carries the data to the memory-receiver.

Optionally, when the I2C clock line SCL signal transitions to a high level, the SDA signal may not have stabilized to a correct level yet, and in order to make the signal on the read data line more stable, the third phase point is located at a time after the signal on the I2C clock line transitions to a high level within the bit period, and is delayed by a preset time. A period of time is required to wait before reading the SDA signal to ensure that the SDA signal is stable and reaches an active level.

In some embodiments, for finer timing control of the I2C bus, besides the three phase points of the bit period corresponding to the above three sub-target numbers, more sub-target numbers may be set, so as to determine more phase points of the clock signal, for example, by setting a fourth sub-target number, a fourth phase point is correspondingly determined, and the fourth phase point may be located at a signal high level of the I2C clock line and has a certain delay time with the second phase point, so as to ensure signal stability on the data line.

The multi-channel synchronous parallel I2C communication method provided by the embodiment of the application simulates multi-channel I2C synchronous communication by adopting a GPIO group operation mode, so that all channels can share the same SCL, and the number (N-1) of SDAs depends on the number (N) of interfaces of the hardware corresponding to the GPIOs.

In some embodiments, since the SDA data bus state is read in each bit period and stored in the memory-receive buffer, when the data is read, the memory-receive contains a large amount of useless information, so that data analysis is required, and single bit data of each channel is indexed according to the channel sequence to be spliced, so that the data finally read out by each channel is obtained.

It should be noted that, in the multi-channel synchronous parallel I2C communication method provided in the embodiments of the present application, steps 101 to 103 are labeled for convenience of description, and those skilled in the art will understand that, in the foregoing method of the specific embodiment, the writing order of each step does not mean a strict execution order, but rather any limitation is imposed on the implementation process, and the specific execution order of each step should be determined according to its function and possible internal logic.

The multi-channel synchronous parallel I2C communication method provided by the embodiment of the application realizes the conversion from the existing serial communication to the parallel communication, and greatly improves the test and measurement efficiency; and from serial asynchronous communication to parallel synchronous communication; the method solves the problem that the I2C occupies the CPU/MCU, reduces the load of the system, and has the advantages of lower cost and high reliability.

Example two

Corresponding to the multi-channel synchronous parallel I2C communication method provided in the above embodiment, as shown in fig. 7, the present embodiment provides a multi-channel synchronous parallel I2C communication system 1, including a counting module 11, a comparing module 12, a GPIO interface 14, and a direct access storage module 13.

The counting module 11 counts according to a preset clock signal in a preset counting period to obtain a current count value; the comparison module 12 respectively compares the current count value with at least three preset sub-target numbers to obtain comparison results, and respectively generates at least three corresponding trigger signals according to the comparison results.

The GPIO interface 14 is used for simulating a multipath I2C bus channel, the I2C bus includes a clock line and a data line, the bit period of the I2C communication includes at least three phase points, the phase points are in one-to-one correspondence with the sub-target numbers, wherein the first phase point is located at the start of the bit period, the second phase point is located at the signal rising edge of the I2C clock line in the bit period, and the third phase point is located at the signal high level of the I2C clock line in the bit period.

The direct access storage module 13 is configured to acquire data pre-written to the GPIO interface at a first phase point according to the first trigger signal and store the data to an output data memory of the GPIO interface; acquiring data pre-written to the GPIO interface at a second phase point according to the second trigger signal and storing the data into an output data memory of the GPIO interface; and the data read by the input data memory of the GPIO interface according to the third trigger signal is stored in the designated area.

In some embodiments, the system further comprises a write data storage module and a read data storage module.

The write data storage module is used for storing data which is written into the GPIO interface in advance at the first phase point and data which is written into the GPIO interface in advance at the second phase point. It should be noted that, as described above, when a write operation is required, waveform data of each I2C bus channel needs to be integrated, and the specific way of integration is as described in the above embodiment, which is not described again.

When the reading operation is needed, the I2C waveform data is also needed to be integrated, that is, the data sequences read in the first phase point phase0, the second phase point phase1 and the third phase point phase2 are sorted according to a certain rule, so as to obtain the data of the reading operation. Specifically, as described in the above embodiments, the present embodiment is not described in detail.

The read data storage module is used for storing data to be read from the GPIO interface at the third phase point.

In some embodiments, as shown in fig. 7, the counting module 11 includes an auto reload register 111 and a timer 112 (or timer). An Auto-reload register 111 (Auto-reload register) is a special register used in a timer or timer 112. It is used to set a timer or reload value of timer 112 to implement an automatic reset or cycle count function. The auto reload register 111 allows setting the initial value of the timer or timer 112 and automatically resets to the initial value when the timer or timer 112 reaches this value, thereby achieving periodic timing or counting.

The comparison module 12 comprises at least a first comparison register 121, a second comparison register 122 and a third comparison register 123.

The direct access storage module 13 includes a first direct access storage unit 131, a direct access storage unit 132, and a direct access storage unit 133.

The write data storage module includes at least a first write data storage unit 151 and a second write data storage unit 152; the first write data storage unit 151 is configured to store data written to the GPIO interface in advance at a first phase point; the second write data storage unit 152 is used to store data pre-written to the GPIO interface at a second phase point. The read data storage module comprises at least one read data storage unit 161.

The first comparing register 121 is configured to compare the current count value with a preset first sub-target number 101, obtain a first comparison result, and generate a first trigger signal 104 according to the comparison result; the first direct access storage unit 131 acquires data pre-written to the GPIO interface 14 at the first phase point from the first write data storage unit 151 according to the first trigger signal 104 and stores it to the output data memory 141 of the GPIO interface 14.

The second comparing register 122 is configured to compare the current count value with a preset second sub-target number 102 to obtain a second comparison result, and generate a second trigger signal 105 according to the comparison result; the second direct access storage unit 132 acquires the data pre-written to the GPIO interface 14 at the second phase point from the second write data storage unit 152 according to the second trigger signal 105 and stores it to the output data memory 141 of the GPIO interface 14.

The third comparison register 123 is configured to compare the current count value with a preset third sub-target number 103, obtain a third comparison result, and generate a third trigger signal 106 according to the comparison result; the third direct access storage unit 133 is configured to read data from the input data memory 142 of the GPIO interface 14 at a third phase point according to the third trigger signal 106 and store the data in the read data storage unit 161.

In some embodiments, the multi-channel synchronous parallel I2C communication system 1 may be implemented using an MCU. MCU stands for microcontroller unit (Microcontroller Unit), which is an integrated circuit chip, a special microprocessor with CPU (Central processing Unit), memory (such as flash memory and SRAM), input/output interface and other peripheral components. An MCU having a GPIO pin that meets the GPIO pin requirements may be selected to support the required number of I2C bus channels.

The multichannel synchronous parallel I2C communication system 1 solves the problem that CPU/MCU resources are occupied in 2-wire I2C communication, and the scheme is not only suitable for multichannel synchronous test measurement, but also suitable for a single-channel test measurement scheme, and effectively reduces the load of the CPU/MCU; the embodiment can realize the synchronous communication from serial asynchronous communication to parallel synchronous communication, can support the data-transmission of the multi-channel I2C bus, and has wide application, such as the synchronous acquisition of multi-channel DC data.

Example III

The present embodiment provides an electronic device, including: a multi-channel synchronous parallel I2C communication system as above.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims (10)

1. A method of multi-channel synchronous parallel I2C communication, the method comprising:

counting according to a preselected clock signal in a preset counting period to obtain a current count value;

comparing the current count value with at least three preset sub-target numbers respectively to obtain comparison results, and generating at least three corresponding trigger signals respectively according to the comparison results;

simulating a multipath I2C bus channel by using a GPIO interface (14), wherein the bit period of I2C communication comprises at least three phase points, the phase points are in one-to-one correspondence with the sub-target numbers, the first phase point is positioned at the beginning of the bit period, the second phase point is positioned at the signal rising edge of an I2C clock line, and the third phase point is positioned at the signal high level of the I2C clock line;

acquiring data pre-written to the GPIO interface (14) at a first phase point according to a first trigger signal and storing the data in an output data memory (141) of the GPIO interface (14); acquiring data pre-written to the GPIO interface (14) at a second phase point according to a second trigger signal, and storing the data in an output data memory (141) of the GPIO interface (14); and data read from an input data memory (142) of the GPIO interface (14) at a third phase point according to a third trigger signal is stored in a designated area.

2. The multi-channel synchronous parallel I2C communication method according to claim 1, characterized in that the method comprises:

the data pre-written to the GPIO interface (14) at a first of the phase points includes data pre-written to the I2C clock line and the I2C data line simultaneously;

pre-writing data to the GPIO interface (14) at a second of the phase points includes pre-writing data to the I2C clock line;

the data to be read from the GPIO interface (14) at the third of the phase points is the data of the I2C data line.

3. The multi-channel synchronous parallel I2C communication method according to claim 1, wherein the GPIO interface (14) comprises a plurality of GPIO pins (143), one GPIO pin (143) of the plurality of GPIO pins (143) simulates the I2C clock lines of all I2C bus channels, and all remaining GPIO pins (143) or part of the remaining GPIO pins (143) are selected to respectively simulate I2C data lines of each path of I2C bus channel.

4. The multi-channel synchronous parallel I2C communication method according to claim 1, wherein counting is performed according to a preselected clock signal to obtain a current count value, comprising the steps of:

counting the preselected clock signals by using a timer to obtain a current count value; the counting period of the timer is the bit period of I2C communication;

and when the timing time reaches the bit period, automatically resetting the current count value in the timer, and timing the next count period.

5. The multi-channel synchronous parallel I2C communication method of claim 4, wherein the method comprises:

and/or comparing the current count value with at least three preset sub-target numbers respectively by using a comparison register to obtain a comparison result, and generating at least three corresponding trigger signals respectively according to the comparison result;

and/or, acquiring data pre-written to the GPIO interface (14) at a first one of the phase points according to a first one of the trigger signals using a direct access memory and storing the data in an output data memory (141) of the GPIO interface (14); acquiring data pre-written to the GPIO interface (14) at a second phase point according to a second trigger signal and storing the data in an output data memory (141) of the GPIO interface (14); and according to the third trigger signal, the data read by the input data memory (142) of the GPIO interface (14) are stored.

6. The multi-channel synchronous parallel I2C communication method of claim 5, wherein a third one of the phase points is located at a time after a preset time delay after the signal of the I2C clock line jumps to a high level.

7. A multi-channel synchronous parallel I2C communication system (1), characterized in that the system comprises:

the counting module (11), the said counting module (11) counts according to the preselected clock signal in the preset counting period, obtain the present count value;

the comparison module (12) is used for comparing the current count value with at least three preset sub-target numbers respectively to obtain comparison results, and at least three corresponding trigger signals are generated according to the comparison results respectively;

a GPIO interface (14), where the GPIO interface (14) is configured to simulate a multi-channel I2C bus channel, and a bit period of the I2C communication includes at least three phase points, where the phase points correspond to the sub-target numbers one by one, a first phase point is located at a start of the bit period, a second phase point is located at a signal rising edge of an I2C clock line, and a third phase point is located at a signal high level of the I2C clock line;

a direct access storage module (13), wherein the direct access storage module (13) is used for acquiring data pre-written to the GPIO interface (14) at the first phase point according to the first trigger signal and storing the data into an output data memory (141) of the GPIO interface (14); acquiring data pre-written to the GPIO interface (14) at a second phase point according to a second trigger signal, and storing the data in an output data memory (141) of the GPIO interface (14); and data read from an input data memory (142) of the GPIO interface (14) at a third phase point according to a third trigger signal is stored in a designated area.

8. The multi-channel synchronous parallel I2C communication system of claim 7, further comprising a write data storage module and a read data storage module;

the write data storage module is used for storing data which is pre-written to the GPIO interface (14) at a first phase point and data which is pre-written to the GPIO interface (14) at a second phase point;

the read data storage module is used for storing data to be read from the GPIO interface (14) at a third phase point.

9. The multi-channel synchronous parallel I2C communication system according to claim 8, wherein the comparison module (12) comprises at least a first comparison register (121), a second comparison register (122) and a third comparison register (123);

the direct access storage module (13) comprises at least a first direct access storage unit (131), a second direct access storage unit (132) and a third direct access storage unit (133);

the write data storage module comprises at least a first write data storage unit (151) and a second write data storage unit (152); the first write data storage unit (151) is configured to store data pre-written to the GPIO interface (14) at a first one of the phase points; the second write data storage unit (152) is configured to store data pre-written to the GPIO interface (14) at a second of the phase points;

the read data storage module comprises at least one read data storage unit (161);

the first comparison register (121) is configured to compare the current count value with a preset first sub-target number (101) respectively, obtain a first comparison result, and generate a first trigger signal (104) according to the comparison result;

the first direct access storage unit (131) acquires data pre-written to the GPIO interface (14) at a first phase point from the first write data storage unit (151) according to a first trigger signal and stores the data into an output data memory (141) of the GPIO interface (14);

the second comparison register (122) is configured to compare the current count value with a preset second sub-target number (102) respectively, obtain a second comparison result, and generate a second trigger signal (105) according to the comparison result;

the second direct access storage unit (132) acquires data pre-written to the GPIO interface (14) at a second phase point from the second write data storage unit (152) according to a second trigger signal and stores the data in an output data memory (141) of the GPIO interface (14);

the third comparison register (123) is configured to compare the current count value with a preset third sub-target number (103) respectively, obtain a third comparison result, and generate a third trigger signal (106) according to the comparison result;

the third direct access storage unit (133) is configured to store data read by the input data memory (142) of the GPIO interface (14) according to the third trigger signal into the read data storage unit (161).

10. An electronic device, comprising: the multi-channel synchronous parallel I2C communication system of any of claims 7-9.