CN117693820A

CN117693820A - Gate-around transistor, manufacturing method thereof, CMOS transistor and electronic equipment

Info

Publication number: CN117693820A
Application number: CN202180100879.5A
Authority: CN
Inventors: 刘明山; 侯朝昭; 董耀旗; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-09-26
Filing date: 2021-09-26
Publication date: 2024-03-12
Also published as: WO2023044870A1

Abstract

A gate-all-around transistor, a manufacturing method thereof, a CMOS transistor and an electronic device, wherein the gate-all-around transistor (100) comprises a substrate (01), a fin-shaped structure (02) arranged on the substrate (01), a source electrode (031), a drain electrode (032), an internal isolation part (04) and a gate structure (05). Because the internal isolation part (04) is formed by oxidizing the side of the source electrode (031) close to the side wall (051) and the side of the drain electrode (032) close to the side wall (051), the source electrode (031) and the drain electrode (032) can start along the exposed surfaces of the sacrificial layer (022) and the channel layer (021) during epitaxial growth, the initial growth surfaces of the source electrode (031) and the drain electrode (032) are continuous surfaces, compared with the initial growth surfaces of the source electrode (031) and the drain electrode (032) which are a plurality of discontinuities, the source electrode (031) and the drain electrode (032) with better crystal quality can grow, and for the P-type circular gate transistor, the strain of the source electrode (031) and the drain electrode (032) can not relax, and enough compressive strain is formed on the channel. For an N-type gate-all-around transistor, the epitaxially grown source (031) and drain (032) will not affect the performance of the transistor.

Description

Gate-around transistor, manufacturing method thereof, CMOS transistor and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a gate-all-around transistor, a method for manufacturing the same, a CMOS transistor, and an electronic device.

Background

Along with the continuous promotion of moore's law, the size of a transistor in a chip is continuously reduced, the integration level is continuously improved, and the working voltage is continuously reduced, so that the requirements of high performance and low power consumption of the chip are met. From the first transistor invention to the current mainstream 5nm technology node, over half a century, at each technology node, innovative process technologies have been proposed to further drive the development of transistors. The continued scaling of conventional transistor feature sizes has reached physical limits, resulting in contradiction of chip power consumption, performance and cost, and thus complementary metal oxide semiconductor (Complementary metal oxide semiconductor, CMOS) devices have entered the 3D Fin Field effect transistor (Fin Field-Effect Transistor, fin FET) era from two-dimensional planar structures and have continued to 5nm process nodes. To further extend moore's law, microelectronics and industry have been increasingly laying out the next generation device developments based on new materials and new architectures. The Gate-all-around (GAA) transistor has better current driving capability and better Gate control performance than Fin FET, so that the Gate-all-around (GAA) transistor has advantages in terms of transistor size shrink, layout area and power consumption, and becomes a candidate structure of nodes below 5nm. However, in the conventional P-type surrounding gate transistor, the source and drain electrodes only start to be epitaxially grown along the exposed surface of the channel layer, but do not epitaxially grow at the SiN internal isolation portion, and then the interface epitaxially grown along the channel layer is fused together so as to cover the surface of the SiN internal isolation portion, but defects (defects) or stacking faults (stacking faults) are formed at the interface where the fusion is grown. The strain of the source and drain thus formed is relaxed and compressive strain effective for channel formation is not achieved, thereby reducing hole mobility.

Disclosure of Invention

The application provides a gate-all-around transistor, a preparation method thereof, a CMOS transistor and electronic equipment, which are used for improving compressive strain of a source electrode and a drain electrode on a channel in a P-type gate-all-around transistor.

In a first aspect, a gate-all-around transistor is provided that may include a substrate and a fin structure, a source, a drain, an internal spacer, and a gate structure on the substrate. Wherein the fin structure comprises a plurality of channel layers stacked at intervals along a direction perpendicular to the substrate; the source electrode and the drain electrode are respectively positioned at two sides of the fin-shaped structure; two internal isolation parts are arranged on one side of each channel layer facing the substrate, and any two internal isolation parts are formed by oxidizing one side of the source electrode, which is close to the fin-shaped structure, and one side of the drain electrode, which is close to the fin-shaped structure; the gate structure is located between the source and the drain and covers the fin structure.

According to the gate-all-around transistor, the source electrode is close to one side of the side wall and the drain electrode is close to one side of the side wall, oxidation is carried out to form the inner isolation part, so that in the previous step, epitaxial growth of the source electrode and the drain electrode is started along the exposed surfaces of the sacrificial layer and the channel layer, the initial growth surfaces of the source electrode and the drain electrode are continuous surfaces, compared with the prior art, the initial growth surfaces of the source electrode and the drain electrode are a plurality of discontinuities, the source electrode and the drain electrode with good crystal quality can be grown, fusion interfaces, defects and dislocation in epitaxial growth of the source electrode and the drain electrode are obviously reduced, strain of the source electrode and the drain electrode is not relaxed, and enough compressive strain is formed on a channel. For an N-type gate-all-around transistor, the epitaxially grown source and drain do not affect the transistor performance. Thereby providing a transistor structure compatible with N-type and P-type gate-all-around transistors.

For example, in the present application, the gate structure may include two sidewalls disposed opposite to each other, a gate dielectric layer surrounding each of the channel layers, and a gate layer filling a gap between the two sidewalls, where one of the two sidewalls is disposed near the source and the other sidewall is disposed near the drain.

In a specific implementation, the source electrode and the drain electrode are made of the same material, and the materials of the source electrode and the drain electrode can be set according to the structure of the device.

When the gate-all-around transistor is a P-type transistor, the source and drain materials may be P-type doped semiconductors, for example, P-type doped silicon germanium semiconductors. The doped P-type ions may be trivalent ions, such as boron, aluminum, gallium, and the like.

In a specific implementation, when the source and drain electrodes are P-doped silicon germanium semiconductor, the material of the internal isolation portion may include silicon germanium oxide.

When the gate-all-around transistor is an N-type transistor, the source and drain materials may be N-type doped semiconductors, for example, N-type doped silicon semiconductors. The doped N-type ions may be pentavalent ions, such as nitrogen, phosphorus, arsenic, and the like.

In an embodiment, when the source and drain electrodes are made of N-doped silicon semiconductor, the material of the internal isolation portion may include silicon oxide.

For effective isolation of the source and gate layers and the drain and gate layers, the thickness of the internal isolation portion in the channel direction may be controlled to be between 1nm and 5nm, for example, 1nm, 2nm, 3nm, 4nm or 5nm. Wherein, in this application, the channel direction is parallel to the direction in which the source points to the drain.

In a second aspect, a method for manufacturing a gate-all-around transistor is provided, which may include the steps of: firstly, forming a fin on a substrate, and crossing a sacrificial grid electrode and two side walls of the fin; the fins comprise sacrificial layers and channel layers which are stacked and alternately and repeatedly arranged, and the two side walls are respectively positioned at two sides of the sacrificial grid; then epitaxially growing a source electrode and a drain electrode on the exposed fin outside the side wall; then removing the sacrificial grid electrode and the sacrificial layer to form a plurality of suspended channel layers; oxidizing one side of the source electrode close to the side wall and one side of the drain electrode close to the side wall to form a plurality of internal isolation parts; and finally, forming a gate dielectric layer and a gate layer between the two side walls.

In this application, since the source and drain electrodes are epitaxially grown along the exposed surfaces of the sacrificial layer and the channel layer, the initial growth surfaces of the source and drain electrodes are continuous surfaces, and the source and drain electrodes with better crystal quality can be grown compared with the initial growth surfaces of the source and drain electrodes in the related art, so that the fusion interface in the source and drain electrodes is significantly reduced, and the strain of the epitaxially grown source and drain electrodes is not relaxed, and thus effective compressive strain is formed on the channel. And because the source electrode and the drain electrode are more doped than the channel layer, the heavily doped source electrode and the drain electrode are more easily oxidized than the channel layer, and the oxidation rate of the source electrode and the drain electrode is faster than that of the channel layer, so that an internal isolation part can be formed only in a suspended area of the source electrode, which is close to one side of the side wall, and in a suspended area of the drain electrode, which is close to one side of the side wall, and the channel layer is not oxidized basically. Thereby physically isolating the source, drain and gate layer formed in the floating region using the internal isolation, thereby reducing parasitic capacitance.

The thicknesses of the sacrificial layer and the channel layer are not limited, and can be set according to the actual requirements of the gate-all-around transistor.

In the present application, the substrate may be a semiconductor material, for example, the material of the substrate may be one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide, and is not limited to the examples listed herein.

In the application, the sacrificial layer can be formed by selecting a material with a similar lattice constant to that of the channel layer, and in the same etching process, the sacrificial layer and the channel layer have a higher etching selectivity ratio, so that the sacrificial layer can be etched away and the channel layer is reserved when the subsequent selective etching is performed, thereby forming the suspended channel layer. Illustratively, the channel layer may be formed of a Si semiconductor material and the sacrificial layer may be formed of a SiGe semiconductor material.

In a specific implementation, the bottom layer in the fin is a sacrificial layer, and the top layer is a channel layer. During preparation, the sacrificial layer and the channel layer can be sequentially epitaxially grown on the substrate, and the epitaxial growth is repeated for a plurality of times, so that a plurality of layers of sacrificial layers and a plurality of layers of channel layers which are sequentially stacked are formed. The sacrificial layer and the channel layer are then patterned using a patterning process to form the fin.

In one possible implementation, the doping concentration of the source and the drain is greater than the doping concentration of the channel layer; oxidizing the side of the source electrode near the side wall and oxidizing the side of the drain electrode near the side wall to form a plurality of internal isolation parts can comprise: oxidizing one side of the source electrode close to the side wall and one side of the drain electrode close to the side wall, so that the oxidation rate of one side of the source electrode close to the side wall and the oxidation rate of one side of the drain electrode close to the side wall are larger than the oxidation rate of the channel layer; and forming a plurality of internal isolation parts on one side of the source electrode close to the side wall and one side of the drain electrode close to the side wall respectively.

In one possible implementation, the sacrificial gate and two sidewalls across the fin may be formed by: forming a sacrificial gate material layer overlying the fins; forming a mask protection layer on the sacrificial gate material layer; patterning the mask protection layer and the sacrificial gate material layer to form a sacrificial gate that spans the fin; and forming side walls on two sides of the sacrificial grid respectively.

The sacrificial gate material layer may be formed of any suitable material, including one of polysilicon, germanium, silicon nitride, silicon oxide, or a combination thereof. In this embodiment, a masking protective layer is used to protect the sacrificial gate material layer from exposure during subsequent processing steps. By way of example, the mask protection layer may be formed using a hard mask material, such as silicon nitride.

Illustratively, the sidewall may be formed of a low dielectric constant material, including, for example, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, and combinations thereof. In practice, the sidewall spacers may be deposited by conventional chemical vapor deposition (Chemical Vapor Deposition, CVD) or atomic layer deposition (Atomic Layer Deposition, ALD), without limitation.

In a third aspect, a CMOS transistor is provided, which includes two gate-all-around transistors according to the first aspect or the various embodiments of the first aspect, wherein the two gate-all-around transistors may be N-type transistors and P-type transistors, respectively.

In a fourth aspect, an electronic device is provided, which comprises a circuit board, a gate-all-around transistor according to the first aspect or the various embodiments of the first aspect, and/or a CMOS transistor according to the various embodiments of the third aspect, which are arranged on the circuit board.

The technical effects achieved by the third aspect and the fourth aspect may be described with reference to any possible design of the first aspect, and the description is not repeated here.

Drawings

Fig. 1 is a schematic perspective view of a related art gate-all-around transistor;

fig. 2 is a schematic cross-sectional structure of the gate-all-around transistor shown in fig. 1 along the AA' direction;

fig. 3a to 3i are schematic structural diagrams of a manufacturing process of a gate-all-around transistor according to the related art;

fig. 4 is a schematic diagram of source and drain growth in a related art provided gate-all-around transistor;

fig. 5 is a schematic structural diagram of a gate-all-around transistor according to an embodiment of the present application;

fig. 6 is a flowchart of a method for manufacturing a gate-all-around transistor according to an embodiment of the present application;

fig. 7a to 7h are schematic perspective views of a process for manufacturing a pass transistor according to an embodiment of the present application;

FIGS. 8a to 8i are schematic cross-sectional views illustrating the process of fabricating a gate-around transistor according to embodiments of the present application;

fig. 9 is a schematic structural diagram of a CMOS transistor according to an embodiment of the present disclosure;

fig. 10 is a flowchart of a method for manufacturing a CMOS transistor according to an embodiment of the present disclosure;

fig. 11a to 11h are schematic perspective views illustrating a process of manufacturing a CMOS transistor according to an embodiment of the present application.

Reference numerals illustrate:

100. a gate-all-around transistor; a 01 substrate;

02. a fin structure; 02' fins;

021. a channel layer; 022 a sacrificial layer;

031. a source electrode; 032 drain electrode;

04. an internal isolation section; 05 gate structure;

051. a side wall; 052 a gate dielectric layer;

053. a gate layer; 06 sacrificial gate;

061. a sacrificial gate material layer; 062 mask protection layer;

a 100_n N-type transistor; 100_p type transistor.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations, not to scale.

It is noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present application. This application may be carried out in a variety of other ways than those herein set forth, and similar generalizations may be made by those skilled in the art without departing from the spirit of the application. Therefore, the present application is not limited by the specific embodiments disclosed below. The following description is of the preferred embodiments for carrying out the present application and is intended to be illustrative of the general principles of the present application and not in limitation of the scope of the present application. The scope of the present application is defined by the appended claims.

In order to facilitate understanding of the gate-all-around transistor provided in the embodiments of the present application, an application scenario thereof is first described below.

The gate-all-around transistor can realize ideal control of the channel due to the fact that the gate structure can be arranged around the channel, so that the gate-all-around transistor provided by the embodiment of the application can be widely applied to various scenes as components of electronic equipment, such as logic devices, processors and the like, and it should be noted that the gate-all-around transistor provided by the embodiment of the application is intended to be applied to these and any other suitable types of electronic equipment.

At present, a structure of a common gate-all-around transistor is shown in fig. 1 and 2, wherein fig. 1 is a schematic perspective view of a gate-all-around transistor in the related art; fig. 2 is a schematic cross-sectional view of the gate-all-around transistor shown in fig. 1 along the AA' direction. The preparation process flow comprises the following steps: (1) As shown in fig. 3a, siGe layers 11 and Si layers 12 are alternately epitaxially grown; (2) Patterning the SiGe layer 11 and the Si layer 12 to form the fin 1, as shown in fig. 3 b; (3) As shown in fig. 3c, a sacrificial gate (dummy gate) 2 and side walls 3 positioned at both sides of the sacrificial gate 2 are formed; (4) removing the fins 1 outside the side wall 3 as shown in fig. 3 d; (5) as shown in fig. 3e, removing the SiGe layer 11 under the side wall 3; (6) As shown in fig. 3f, an SiN internal spacer (inner spacer) 4 is deposited at the void under the sidewall 3; (7) epitaxially growing a source 51 and a drain 52 as shown in fig. 3 g; (8) As shown in fig. 3h, the sacrificial gate 2 is removed to expose the SiGe layer 11 and the Si layer 12 under the sacrificial gate 2; (9) As shown in fig. 3i, the SiGe layer 11 remaining in the fin 1 is removed, leaving the Si layer 12 suspended as channel material; (10) As shown in fig. 1 and 2, a gate dielectric layer 6 and a gate layer 7 are formed.

In the gate-all-around transistor, the epitaxial growth of the source and drain is critical, and it is desirable to introduce source-drain strain sources, such as SiGe, in P-type devices to induce compressive strain on the channel, which is advantageous for improved hole mobility in the channel and improved electrical performance. However, in the actual manufacturing process, as shown in fig. 4, the source electrode 51 and the drain electrode 52 first start to be grown along the exposed surface of the Si layer 12, and then these grown surfaces are fused together and cover the surface of the SiN internal isolation portion 4, and then defects (defects) or stacking faults (stacking faults) are formed at the interface of the growth fusion until the growth of the entire source electrode 51 and the drain electrode 52 is completed. The strain of the source 51 and drain 52 is relaxed and compressive strain is not effective for channel formation, thereby not contributing to the improvement of hole mobility.

Therefore, the embodiment of the application provides the gate-all-around transistor and the preparation method thereof, and the epitaxially grown source electrode and drain electrode can keep enough compressive strain on a channel. The present application will be described in further detail with reference to the accompanying drawings.

The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a gate-all-around transistor according to an embodiment of the present application. The gate-all-around transistor 100 may comprise a substrate 01, a fin structure 02 on said substrate 01, a source 031, a drain 032, a plurality of internal spacers 04 and a gate structure 05. Wherein the fin structure 02 includes a plurality of channel layers 021 stacked at intervals in a direction perpendicular to the substrate 01; the source 031 and the drain 032 are located on two sides of the fin structure 02, respectively; two internal isolation parts 04 are arranged on the side, facing the substrate 01, of each channel layer 021, and any two internal isolation parts 04 are formed by oxidizing the side, close to the fin-shaped structure 02, of the source electrode 031 and the side, close to the fin-shaped structure 02, of the drain electrode 032; the gate structure 05 is located between the source 031 and the drain 032 and covers the fin structure 02.

In a specific implementation, as shown in fig. 5, the gate structure 05 may include two side walls 051 disposed opposite to each other, a gate dielectric layer 052 surrounding each channel layer 021, and a gate layer 053 filling a gap between the two side walls 051, where one side wall 051 of the two side walls 051 is disposed near the source 031 and the other side wall 051 is disposed near the drain 032.

Referring to fig. 6, fig. 6 shows a schematic flow chart of a method for manufacturing a gate-all-around transistor according to an embodiment of the present application, where the method may include the following steps:

step S101, forming a fin on a substrate, and crossing a sacrificial grid and two side walls of the fin; the fins comprise sacrificial layers and channel layers which are stacked and alternately and repeatedly arranged, and the two side walls are respectively positioned at two sides of the sacrificial grid;

in one possible implementation, as shown in fig. 7a and 8a, a fin 02 'is first formed on a substrate 01, where the fin 02' includes a sacrificial layer 022 and a channel layer 021 that are stacked and alternately repeated. As shown in fig. 7b and 8b, a sacrificial gate 06 and two side walls 051 are then formed across the fins 02', and the two side walls 051 are located on both sides of the sacrificial gate 06, respectively. As shown in fig. 7c and 8c, the fin 02 'exposed outside the sidewall 051 is finally removed, and the fin 02' located under the sacrificial gate 06 and the sidewall 051 is remained. Fig. 8a is a schematic cross-sectional view of the structure shown in fig. 7a along the AA ' direction, fig. 8b is a schematic cross-sectional view of the structure shown in fig. 7b along the AA ' direction, and fig. 8c is a schematic cross-sectional view of the structure shown in fig. 7c along the AA ' direction. In fig. 7a, a gate-all-around transistor is illustrated as including three sacrificial layers 022 and three channel layers 021. It will be appreciated that in the gate-all-around transistor, the number of layers of the sacrificial layer 022 and the channel layer 021 may be determined according to the actual requirements of the device, and is not limited herein. For example, the number of layers of the sacrificial layer 022 and the channel layer 021 may be set according to the conductive performance of the gate around transistor.

The thicknesses of the sacrificial layer 022 and the channel layer 021 are not limited in the present application, and the thicknesses of the sacrificial layer 022 and the channel layer 021 can be set according to actual gate-around transistor requirements.

In the present application, the substrate 01 may be a semiconductor material, for example, the material of the substrate 01 may be one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide, and is not limited to the examples listed herein.

In the present application, the sacrificial layer 022 may be formed by selecting a material having a lattice constant similar to that of the channel layer 021, and in the same etching process, the sacrificial layer 022 and the channel layer 021 have a higher etching selectivity ratio, so that the sacrificial layer 022 can be etched away during the subsequent selective etching, and the channel layer 021 is remained, thereby forming the suspended channel layer 021. Illustratively, the channel layer 021 may be formed using a Si semiconductor material and the sacrificial layer 022 may be formed using a SiGe semiconductor material.

In particular, the bottom layer in fin 02' is sacrificial layer 022 and the top layer is channel layer 021. In preparation, the sacrificial layer 022 and the channel layer 021 may be epitaxially grown on the substrate 01 in sequence, and the epitaxial growth may be repeated a plurality of times, thereby forming a plurality of sacrificial layers 022 and a plurality of channel layers 021 which are stacked in sequence. The sacrificial layer 022 and the channel layer 021 are then patterned by a patterning process, thereby forming the fin 02'.

In particular implementations, the extension method of the sacrificial gate 06 may be set perpendicular to the extension direction of the fin 02'.

In one possible implementation, the sacrificial gate 06 may be formed by: first forming a layer of sacrificial gate material covering the fins 02'; then forming a mask protection layer on the sacrificial gate material layer; patterning the mask protection layer and the sacrificial gate material layer to form a sacrificial gate 06 spanning the fin 02' as shown in fig. 7b and 8b, i.e., the sacrificial gate 06 includes a patterned sacrificial gate material layer 061 and a mask protection layer 062; and then forming side walls 051 on two sides of the sacrificial grid electrode 06 respectively.

The sacrificial gate material layer 061 may be formed of any suitable material including one of polysilicon, germanium, silicon nitride, silicon oxide, or a combination thereof. In this embodiment, a mask protection layer 062 is used to protect the sacrificial gate material layer 061 from being exposed in subsequent process steps. Illustratively, the mask protection layer 061 may be formed using a hard mask material, such as silicon nitride.

Illustratively, the sidewalls 051 can be formed from low dielectric constant materials, including, for example, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, and combinations thereof. In specific implementation, the sidewall 051 may be deposited by a conventional CVD method or an ALD method, which is not limited herein.

Step S102, as shown in fig. 7d and fig. 8d, epitaxially grows a source 031 and a drain 032 on the outer side of the sidewall 051 and the exposed fin 02'. Wherein FIG. 8d is a schematic cross-sectional view of the structure of FIG. 7d along the direction AA'.

In implementation, the materials of the source 031 and the drain 032 are the same, and the materials of the source 031 and the drain 032 may be set according to the structure of the device.

When the gate-all-around transistor is a P-type transistor, the material of the source 031 and the drain 032 may be a P-type doped semiconductor, for example, a P-type doped silicon germanium semiconductor. The doped P-type ions may be trivalent ions, such as boron, aluminum, gallium, and the like.

When the gate-all-around transistor is an N-type transistor, the material of the source 031 and the drain 032 may be an N-type doped semiconductor, for example, an N-type doped silicon semiconductor. The doped N-type ions may be pentavalent ions, such as nitrogen, phosphorus, arsenic, and the like.

In this step, since the source electrode 031 and the drain electrode 032 are epitaxially grown along the exposed surfaces of the sacrificial layer 022 and the channel layer 021, the initial growth surfaces of the source electrode 031 and the drain electrode 032 are a continuous surface. Compared with the prior art that the initial growth surfaces of the source electrode 031 and the drain electrode 032 are a plurality of discontinuities, the source electrode 031 and the drain electrode 032 with better crystal quality can be grown, so that the fusion interface in the source electrode 031 and the drain electrode 032 is obviously reduced, and for the P-type gate-all-around transistor, the strain of the epitaxially grown source electrode 031 and the drain electrode 032 can not relax, and further effective compressive strain is formed on a channel. For an N-type gate-all-around transistor, the epitaxially grown source 031 and drain 032 will not affect the performance of the transistor. Thereby providing a transistor structure compatible with N-type and P-type gate-all-around transistors.

Step S103, removing the sacrificial grid electrode and the sacrificial layer to form a plurality of suspended channel layers.

Illustratively, as shown in fig. 7e and 8e, the sacrificial gate 06 may be removed first to expose the fin 02' under the sacrificial gate 06. As shown in fig. 7f and 8f, the sacrificial layer 022 in the fin 02' is then removed, so as to form a plurality of suspended channel layers 021. Fig. 8e is a schematic cross-sectional view of the structure shown in fig. 7e along the AA 'direction, and fig. 8f is a schematic cross-sectional view of the structure shown in fig. 7f along the AA' direction.

In specific implementations, the sacrificial gate 06 may be removed by dry etching, wet etching, or a combination of both, which is not limited herein.

In specific implementation, the sacrificial layer 022 in the fin 02' may be removed by a dry etching method or a wet etching method, which is not limited herein.

Illustratively, the sacrificial layer 022 in the fin 02' may be selectively etched away by an etching method having a significantly higher etching rate than the channel layer 021, so that the remaining channel layer 021 is suspended, which may be referred to herein as a nanowire channel.

In step S104, as shown in fig. 8g, the side of the source 031 close to the side wall 051 and the side of the drain 032 close to the side wall 051 are oxidized to form a plurality of internal isolation portions 04.

In practice, the doping concentration of the source and drain is generally greater than the doping concentration of the channel layer. When the source electrode is oxidized at one side close to the side wall and the drain electrode is oxidized at one side close to the side wall, the oxidation rate of the source electrode at one side close to the side wall and the oxidation rate of the drain electrode at one side close to the side wall are larger than the oxidation rate of the channel layer, so that a plurality of internal isolation parts are formed at one side close to the side wall of the source electrode and one side close to the side wall of the drain electrode respectively.

This is because the source electrode 031 and the drain electrode 032 are more doped than the channel layer 021, the heavily doped source electrode 031 and the drain electrode 032 are more easily oxidized than the channel layer 021, the oxidation rate of the source electrode 031 and the drain electrode 032 is faster than that of the channel layer 021, the oxidation is performed on the side of the source electrode 031 close to the side wall 051 and the side of the drain electrode 032 close to the side wall 051, so that the oxidized part volume of the source electrode 031 and the drain electrode 032 can expand towards the suspended area, and therefore an internal isolation part 04 can be formed only in the suspended area of the source electrode 031 close to the side wall 051 and the suspended area of the drain electrode 032 close to the side wall 051, and the channel layer 021 is not oxidized basically.

In an embodiment, when the material of the source 031 and the drain 032 is P-type doped silicon germanium semiconductor, the material of the internal isolation portion 04 may include silicon germanium oxide. When the material of the source electrode 031 and the drain electrode 032 is an N-type doped silicon semiconductor, the material of the internal isolation portion 04 may include silicon oxide.

Illustratively, taking the channel layer 021 as an example of a Si semiconductor material, the channel layer 021 has a lower doping concentration or is undoped, and the source 031 and drain 032 have a higher doping concentration.

When the source 031 and the drain 032 are P-type doped SiGe semiconductors, siGeO can be formed by using the source 031 and the drain 032 which oxidize faster than the Si channel layer 021 due to the fact that SiGe oxidizes more easily than Si and that heavily doped SiGe oxidizes more easily than undoped or lightly doped Si _x Is provided in the inner partition 04. When the source electrode 031 and the drain electrode 032 are N-type doped Si semiconductors, siO can be formed by using the oxidation rate of the source electrode 031 and the drain electrode 032 which is faster than that of the Si channel layer 021 because the heavily doped Si is more oxidized than the undoped Si _x Is provided in the inner partition 04.

For example, a low temperature steam oxidation (steam oxidation) method may be used to oxidize the source and drain, where the low temperature may effectively avoid diffusion of impurity atoms and germanium atoms in the source and drain, so that a relatively fast oxidation rate of SiGe may be achieved, and under this condition, the silicon channel layer may only generate a thin native oxide (native oxide), so as to achieve the purpose of selective oxidation.

In this application, the internal isolation portion 04 is made of a low dielectric constant material, and can physically isolate the source electrode 031, the drain electrode 032 and the gate layer formed in the suspended region, thereby reducing parasitic capacitance.

For effective isolation of the source electrode 031 from the gate electrode layer 053 and the drain electrode 032 from the gate electrode layer 053, the thickness of the internal isolation portion 04 in the channel direction may be controlled to be 1nm to 5nm, for example, 1nm, 2nm, 3nm, 4nm, or 5nm, for example. Wherein in the present application the channel direction is parallel to the direction of the source 031 pointing towards the drain 032.

And step S105, forming a gate dielectric layer and a gate layer between the two side walls.

In one possible implementation, as shown in fig. 7g and 8h, a gate dielectric layer 052 surrounding each of the channel layers 021 may be formed first; as shown in fig. 7h and 8i, a gate layer 053 is then formed between the two sidewalls 051. Wherein FIG. 8h is a schematic cross-sectional view of the structure shown in FIG. 7g along the direction AA ', and FIG. 8i is a schematic cross-sectional view of the structure shown in FIG. 7h along the direction AA'.

In a specific implementation, an atomic layer deposition method or a low-pressure chemical vapor deposition method may be used to form a fully-enclosed gate dielectric layer 052 on the surface of each channel layer 021. The gate dielectric layer 052 may be formed of a high dielectric constant material such as an oxide or oxynitride of Si, titanium (Ti), zirconium (Zr), hafnium (Hf), for example, the gate dielectric layer 052 may be SiO ₂ 、HfON、HfO ₂ 、ZrO、TiO ₂ A dielectric layer formed of any one of them or a stack of them.

In a specific implementation, a gate layer 053 may be formed on the surface of the gate dielectric layer 052 by using an atomic layer deposition method until the gate layer 053 completely fills the gap between the two side walls 051. The gate layer 053 may be formed of titanium, titanium nitride, aluminum, tungsten, tantalum nitride, a stack of the above materials, or the like, for example.

Thus, the preparation of the gate-all-around transistor is completed. The gate-all-around transistor provided by the present application forms the internal isolation portion 04 by oxidizing the side of the source electrode 031 close to the side wall 051 and the side of the drain electrode 032 close to the side wall 051, so that the source electrode 031 and the drain electrode 032 start along the exposed surfaces of the sacrificial layer 022 and the channel layer 021 during epitaxial growth, and therefore the initial growth surfaces of the source electrode 031 and the drain electrode 032 are continuous surfaces. Compared with the prior art that the initial growth surfaces of the source electrode 031 and the drain electrode 032 are a plurality of discontinuities, the source electrode 031 and the drain electrode 032 with better crystal quality can be grown, so that the fusion interface in the source electrode 031 and the drain electrode 032 is obviously reduced, and for the P-type gate-all-around transistor, the strain of the epitaxially grown source electrode 031 and the drain electrode 032 can not relax, and further effective compressive strain is formed on a channel. For an N-type gate-all-around transistor, the epitaxially grown source 031 and drain 032 will not affect the performance of the transistor.

In addition, the preparation method is compatible with the existing CMOS transistor process, and is particularly suitable for preparing N-type MOS transistors and P-type MOS transistors with the nodes below 5nm.

Correspondingly, the embodiment of the application also provides a CMOS transistor, as shown in fig. 9, which includes two gate-all-around transistors 100_n and 100_p, and the two gate-all-around transistors 100_n and 100_p are N-type transistors 100_n and P-type transistors 100_p, respectively. Since the principle of solving the problem of the CMOS transistor is similar to that of the aforementioned gate-all-around transistor, the implementation of the CMOS transistor can be referred to the implementation of the aforementioned gate-all-around transistor, and the repetition is omitted.

For example, in the present application, two of the gate-all transistors may share a gate structure.

In order to facilitate understanding of the CMOS transistor provided in the embodiments of the present application, a method for fabricating the same is described in detail below with reference to the accompanying drawings. As shown in fig. 10, in the embodiment of the present application, the preparation method includes the following steps:

in step S201, as shown in fig. 11a, two fins 02 'arranged along the first direction X are formed on the substrate 01, and each of the fins 02' includes a sacrificial layer 022 and a channel layer 021 which are stacked and alternately repeated. In fig. 11a, the first direction X is perpendicular to the AA' direction.

In step S202, as shown in fig. 11b, a sacrificial gate 06 and two side walls 051 are formed across the two fins 02', and the two side walls 051 are respectively located at two sides of the sacrificial gate 06, and the sacrificial gate 06 and the side walls 051 extend along the first direction X.

In step S203, as shown in fig. 11c, the portions of the two fins 02 'exposed outside the side wall 051 are removed, and the portions of the two fins 02' located below the sacrificial gate 06 and the side wall 051 are reserved.

In step S204, as shown in fig. 11d, a source 031 and a drain 032 are epitaxially grown on the outer side of the sidewall 051 and the exposed two fins 02'.

Wherein, the material of the source electrode 031 and the drain electrode 032 at two sides of one fin 02 'is a P-type doped semiconductor, and the material of the source electrode 031 and the drain electrode 032 at two sides of the other fin 02' is an N-type doped semiconductor.

In step S205, as shown in fig. 11e, the sacrificial gate 06 is removed to expose two fins 02' under the sacrificial gate 06.

In step S206, as shown in fig. 11f, the sacrificial layer 022 in each fin 02' is removed, so as to form a plurality of suspended channel layers 021.

In step S207, as shown in fig. 8g, the side of the source 031 close to the sidewall 051 and the side of the drain 032 close to the sidewall 051 are oxidized to form an internal isolation portion 04.

In step S208, as shown in fig. 11g, a gate dielectric layer 052 is formed to encapsulate each of the channel layers 021.

In step S209, as shown in fig. 11h, a gate layer 053 is formed between the two side walls 051.

Thus, the preparation of the CMOS transistor is completed. In specific implementation, the implementation of steps S201 to S209 can refer to steps S101 to S105, and will not be described herein.

Correspondingly, the embodiment of the application also provides electronic equipment, which comprises a circuit board, a gate-all-around transistor arranged on the circuit board, and/or a CMOS transistor arranged on the circuit board. Since the principle of the electronic device for solving the problem is similar to that of the aforementioned gate-all-around transistor, the implementation of the electronic device can be referred to the implementation of the aforementioned gate-all-around transistor, and the repetition is omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

A gate-all-around transistor, comprising:

a substrate;

a fin structure on the substrate, the fin structure comprising a plurality of channel layers stacked at intervals along a direction perpendicular to the substrate;

the source electrode and the drain electrode are respectively positioned at two sides of the fin-shaped structure;

two internal isolation parts positioned on one side of each channel layer facing the substrate, wherein any two internal isolation parts are formed by oxidizing one side of the source electrode close to the fin-shaped structure and one side of the drain electrode close to the fin-shaped structure;

a gate structure located between the source and the drain and overlying the fin structure.
The gate-all-around transistor of claim 1, wherein the material of the source and drain is a P-doped semiconductor.
The gate-all-around transistor of claim 2 wherein said P-doped semiconductor is a P-doped silicon germanium semiconductor.
The gate-all-around transistor of claim 3, wherein the material of said internal spacers comprises silicon germanium oxide.
The gate-all-around transistor of claim 1, wherein the material of the source and drain is an N-doped semiconductor.
The gate-all-around transistor of claim 5 wherein said N-doped semiconductor is an N-doped silicon semiconductor.
The surround gate transistor of claim 6, wherein the material of the internal spacers comprises silicon oxide.
The gate-all-around transistor according to any one of claims 1 to 7, wherein a thickness of the internal isolation portion in a channel direction is 1nm to 5nm.
The gate-all-around transistor of any of claims 1-8, wherein the gate structure comprises: the two side walls are arranged oppositely, the gate dielectric layer wraps each channel layer, and the gate layer fills a gap between the two side walls.
A CMOS transistor comprising two gate-all-around transistors according to any one of claims 1 to 9, wherein the two gate-all-around transistors are N-type and P-type transistors, respectively.
An electronic device comprising a circuit board, a gate-around transistor according to any of claims 1-9 provided on the circuit board, and/or a CMOS transistor according to claim 10 provided on the circuit board.
A method of fabricating a gate-all-around transistor, comprising:

forming a fin on a substrate, and crossing a sacrificial grid electrode and two side walls of the fin; the fins comprise sacrificial layers and channel layers which are stacked and alternately and repeatedly arranged, and the two side walls are respectively positioned at two sides of the sacrificial grid;

epitaxially growing a source electrode and a drain electrode on the exposed fin outside the side wall;

removing the sacrificial grid electrode and the sacrificial layer to form a plurality of suspended channel layers;

oxidizing one side of the source electrode close to the side wall and one side of the drain electrode close to the side wall to form a plurality of internal isolation parts;

and forming a gate dielectric layer and a gate layer between the two side walls.
The method of manufacturing of claim 12, wherein the doping concentration of the source and drain is greater than the doping concentration of the channel layer;

oxidizing the side of the source electrode close to the side wall and the side of the drain electrode close to the side wall to form a plurality of internal isolation parts, wherein the method comprises the following steps:

oxidizing one side of the source electrode close to the side wall and one side of the drain electrode close to the side wall, so that the oxidation rate of one side of the source electrode close to the side wall and the oxidation rate of one side of the drain electrode close to the side wall are larger than the oxidation rate of the channel layer;

and forming a plurality of internal isolation parts on one side of the source electrode close to the side wall and one side of the drain electrode close to the side wall respectively.
The method of manufacturing of claim 12 or 13, wherein forming a sacrificial gate and two sidewalls across the fin comprises:

forming a sacrificial gate material layer overlying the fins;

forming a mask protection layer on the sacrificial gate material layer;

patterning the mask protection layer and the sacrificial gate material layer to form a sacrificial gate that spans the fin;

and forming side walls on two sides of the sacrificial grid respectively.