CN117693192A

CN117693192A - Semiconductor structure and preparation method thereof

Info

Publication number: CN117693192A
Application number: CN202211046968.9A
Authority: CN
Inventors: 韩清华
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-08-30
Filing date: 2022-08-30
Publication date: 2024-03-12
Also published as: WO2024045629A1

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, comprising the following steps: the substrate comprises a substrate and an insulating medium layer, a plurality of grooves extending along a first direction are formed in the substrate, semiconductor columns are formed on the substrate at two sides of the grooves, and the insulating medium layer is positioned on the side wall and the top of the semiconductor columns; the doped region is positioned in the substrate at the bottom of the semiconductor column, a plurality of first bit line grooves which are mutually spaced are arranged in the doped region, a second bit line groove which extends along a second direction is arranged in the substrate below the first bit line groove, an included angle is formed between the second direction and the first direction, and the second bit line groove is communicated with the plurality of first bit line grooves; the bit line is positioned in the first bit line groove and the second bit line groove. The method for forming the bit line in the first bit line groove and the second bit line groove reduces the contact resistance of the bit line and the semiconductor column and increases the performance of the vertical full-surrounded grid electrode by etching the doped region at the bottom of the groove to form the first bit line groove and the second bit line groove.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to integrated circuit technology, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

With the development of semiconductor technology, the transistor size is smaller and smaller, and Vertical Gate-all-around (VAGG) is widely used due to its advantages in integration and wiring.

In conventional VAGG, bit lines are buried using an embedding method. Firstly, doping ions into the groove at the bottom of the semiconductor column, and then hollowing out the groove at the bottom of the semiconductor column and filling bit line metal to form bit lines. The doped ions are removed, so that the contact effect between the bit line and the semiconductor column is poor, and the use of VAGG is affected.

Disclosure of Invention

Based on this, it is necessary to provide a semiconductor structure and a method for fabricating the same, which are directed to the problem of poor ohmic contact effect of bit lines and semiconductor pillars in the prior art.

To achieve the above object, in one aspect, the present invention provides a semiconductor structure, comprising:

the substrate comprises a substrate and an insulating medium layer, wherein a plurality of grooves extending along a first direction are formed in the substrate, semiconductor columns are formed on two sides of the substrate of the grooves, and the insulating medium layer is positioned on the side walls and the top of the semiconductor columns;

the doped region is positioned in the substrate at the bottom of the semiconductor column and the bottom of the groove, a plurality of first bit line grooves which are mutually spaced are formed in the doped region, a second bit line groove which extends along a second direction is formed in the substrate below the first bit line groove, an included angle is formed between the second direction and the first direction, and the second bit line groove is communicated with the plurality of first bit line grooves;

and the bit line is positioned in the first bit line groove and the second bit line groove.

In one embodiment, the first bit line trench is a bottom of the trench between the semiconductor pillars.

In one embodiment, the doped region is an ion implantation region; the doped region comprises a first doped region and a second doped region which are vertically arranged, the second doped region is positioned at two sides of the first doped region, and the doping concentration of the first doped region is greater than that of the second doped region; the bottom of the first bit line groove is positioned in the first doped region.

In one embodiment, a top of the second bit line trench is located within the first doped region.

In one embodiment, the semiconductor structure further comprises:

and the passivation protection layer is positioned on the side wall of the first bit line groove.

In one embodiment, the passivation protection layer comprises a polymer layer.

In one embodiment, the bit line includes:

metal silicide on the first and second bit line groove surfaces;

and the bit line conducting layer is positioned on the surface of the metal silicide.

The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:

providing a substrate, wherein the substrate comprises a substrate and an insulating medium layer, a plurality of grooves extending along a first direction are formed in the substrate, semiconductor columns are formed on two sides of the grooves, and the insulating medium layer is positioned on the side walls and the top of the semiconductor columns;

doping the substrate at the bottom of the semiconductor column through the groove to form a doped region;

etching the doped region at the bottom of the groove to form a plurality of first bit line grooves which are mutually spaced in the doping;

etching the substrate below the first bit line groove to form a second bit line groove extending along a second direction, wherein an included angle is formed between the second direction and the first direction, and the second bit line groove is communicated with a plurality of first bit line grooves;

and forming bit lines in the first bit line groove and the second bit line groove.

In one embodiment, etching the doped region at the bottom of the trench to form a plurality of first bit line trenches spaced apart from each other in the doping, including:

and etching the doped region at the bottom of the groove in the vertical direction to form the first bit line groove.

In one embodiment, the doped region is formed by ion implantation; the doped region comprises a first doped region and a second doped region which are vertically arranged, the second doped region is positioned at two sides of the first doped region, and the doping concentration of the first doped region is greater than that of the second doped region; the bottom of the first bit line groove is positioned in the first doped region.

In one embodiment, before the etching the substrate under the first bit line trench to form the second bit line trench extending along the second direction, the method further includes:

and forming a passivation protection layer on the side wall of the first bit line groove.

In one embodiment, the forming a passivation layer on the sidewall of the first bit line groove includes:

introducing passivation gas to form a passivation material layer on the side wall and the bottom of the first bit line groove;

and etching to remove the passivation material layer at the bottom of the first bit line groove so as to form the passivation protection layer.

In one embodiment, after the passivation material layer at the bottom of the first bit line groove is etched and removed in the same ion etching chamber, the substrate below the first bit line groove is etched to form a second bit line groove extending along the second direction.

In one embodiment, the forming the bit line in the first bit line groove and the second bit line groove includes:

forming metal silicide on the surface of the first bit line groove and the surface of the second bit line groove;

and forming a bit line conducting layer on the surface of the metal silicide.

The semiconductor structure and the preparation method thereof have the following beneficial effects:

according to the semiconductor structure, the bit line formed by the first bit line grooves with the intervals and the second bit line grooves extending along the second direction is arranged in the doped region, so that the contact resistance between the bit line and the semiconductor column is reduced, and the performance of the VAGG is further improved.

According to the preparation method of the semiconductor structure, the first bit line groove and the second bit line groove are formed by etching the doped region at the bottom of the groove, and the bit line is formed in the first bit line groove and the second bit line groove, so that the contact resistance of the bit line and the semiconductor column is reduced, and the integration level of the VAGG is increased.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 2 is a schematic diagram of a structure of a VAGG according to one embodiment;

FIG. 3 is a schematic diagram of an insulating dielectric layer according to an embodiment;

FIG. 4 is a schematic diagram of an insulating dielectric layer according to an embodiment;

FIG. 5 is a schematic diagram of a doped region according to an embodiment;

FIG. 6 is a schematic diagram of a first slot according to an embodiment;

FIG. 7 is a schematic diagram of a passivation layer according to an embodiment;

FIG. 8 is a schematic diagram of a second bit line slot according to an embodiment;

FIG. 9 is a schematic diagram of a metal silicide provided in an embodiment;

FIG. 10 is a schematic diagram of a bit line conductive layer according to an embodiment.

For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.

Reference numerals illustrate:

100-a substrate; 110-semiconductor pillars; 120-doped regions; 120 a-a first doped region; 120 b-a first doped region; 130-a first bit line slot; 131-passivation protection layer; 132-a passivation material layer; 140-a second bit line slot; 200-an insulating medium layer; 200 a-a first dielectric layer; 200 b-a second dielectric layer; 300-bit line; 310-metal silicide; 320-bit line conductive layer.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type, slot or section discussed below could be termed a second element, component, region, layer, slot or section without departing from the teachings of the present invention; for example, a first bit line slot may be referred to as a second bit line slot, and similarly, a second bit line slot may be referred to as a first bit line slot; the first and second trunking are different trunking.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques.

In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, including the following steps:

in step S100, referring to fig. 2 to 4, a base is provided, the base includes a substrate 100 and an insulating dielectric layer 200, a plurality of trenches extending along a first direction are formed in the substrate 100, the substrate 100 on two sides of the trenches forms a semiconductor pillar 110, and the insulating dielectric layer 200 is located on a sidewall and a top of the semiconductor pillar 110.

In step S200, referring to fig. 5, the substrate 100 at the bottom of the semiconductor pillar 110 is doped through the trench to form the doped region 120.

In step S300, referring to fig. 6, the doped region 120 at the bottom of the trench is etched, and a plurality of first bit line trenches 130 are formed in the doped region 120.

In step S500, referring to fig. 8, the substrate 100 under the first bit line groove 130 is etched to form a second bit line groove 140 extending along a second direction, wherein an included angle is formed between the second direction and the first direction, and the second bit line groove 140 is communicated with the plurality of first bit line grooves 130.

In step S600, referring to fig. 10, the bit line 300 is formed in the first bit line trench 130 and the second bit line trench 140.

In step S100, referring to fig. 2 to 4, the substrate 100 may be, for example, a silicon substrate, a silicon germanium carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium phosphide substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 100 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator, or silicon-germanium-on-insulator. The type of substrate 100 should not limit the scope of the present disclosure.

The trenches in the substrate 100 may be formed by etching the substrate 100 in the first direction, and the trenches may be plural. After etching, the substrate 100 on both sides of the trench forms semiconductor pillars 110. Likewise, the number of the semiconductor pillars 110 may be plural. As an example, the plurality of semiconductor pillars 110 may be arranged in parallel and at equal intervals in a column. The number of trenches and semiconductor pillars is not limited in this application.

The material of the insulating dielectric layer 200 may include, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, and the like. Meanwhile, the insulating dielectric layer 200 may be formed using a deposition process. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process, an atomic layer deposition process, a high density plasma deposition process, a plasma enhanced deposition process, and a spin-on dielectric layer.

The insulating dielectric layer 200 may be formed by a different deposition process, or a material. Specifically, referring to fig. 3 and 4, the insulating dielectric layer 200 may include a first dielectric layer 200a and a second dielectric layer 200b. The first dielectric layer 200a may be located at the top of the semiconductor pillar 110 and the second dielectric layer 200b may be located at the sidewall of the semiconductor pillar 110. The first dielectric layer 200a and the second dielectric layer 200b may be formed using different deposition processes and materials, respectively.

The insulating dielectric layer 200 may protect the semiconductor pillars 110 when doping ions and etching the first and second bit line trenches 130, 140. Meanwhile, the insulating dielectric layer 200 may cover the semiconductor pillars 110 along the second direction, enhancing the stability of the semiconductor pillars 110.

In step S200, referring to fig. 5, the doping method may be solid diffusion doping, gas diffusion doping, ion implantation doping, or other methods, which are not limited in this application. Likewise, the present application is not limited to the type of ions doped. As an example, the doped ions may be As ions, P ions, N ions, or the like.

Forming the doped region 120 within the substrate 100 may allow the bit line 300 to contact the bottom of the semiconductor pillar 110 through the doped region 120, thereby reducing the contact resistance between the bit line 300 and the bottom of the semiconductor pillar 110. In addition, the doped region 120 may increase an etching rate of the substrate 100, and the first and second bit line trenches 130 and 140 may be more rapidly and effectively formed.

In step S300, referring to fig. 6, the first bit line trench 130 may be at least partially located in the doped region 120 of the substrate 100. The shape, size, and number of the first bit line grooves 130 are not particularly limited.

The plurality of first bit line trenches 130 are spaced apart from each other to retain a portion of the doped region 120. The pitch between the plurality of first bit line grooves 130 is not particularly limited.

In some cases, doped region 120 may be in contact with the surface of substrate 100. At this time, the first bit line trenches 130 may be all located in the doped region 120.

In some cases, the doped region 120 may also be spaced apart from the surface of the substrate 100. At this time, the first bit line groove 130 may be partially located in the doped region 120 and partially located in the substrate 100 of the undoped region in the vertical direction. That is, the bottom of the first bit line trench 130 is located in the doped region 120 and the top may be located in the substrate 100 of the undoped region.

In step S500, referring to fig. 8, the second slot 140 may be in communication with the first slot 130. The second bit line trenches 140 may be formed using an isotropic etching method. Specifically, isotropic dry etching may be used, or isotropic wet etching may be used, which is not limited in this application. Specifically, for example, dry etching may be performed using carbon tetrafluoride and sulfur hexafluoride; in some cases, sulfur tetrafluoride may also be used as the etching gas.

The etching conditions are controlled such that the second bit line groove 140 communicates with the plurality of first bit line grooves 130 in the second direction. The included angle between the second direction and the first direction may be that the second direction is perpendicular to the first direction, or may be other angles. Specifically, for example, 80 degrees or 60 degrees. In some cases, the first direction, the second direction, and the extension direction of the semiconductor pillar 110 may be perpendicular to each other.

Referring to fig. 8, the second bit line trench 140 is located in the substrate 100 and is connected to the plurality of first bit line trenches 130 along the second direction, such that the second bit line trench 140 is located partially under the semiconductor pillar 110 and partially under the trench. The dimensions of the first and second bit line grooves 130 and 140 and the specific shapes thereof are not limited herein.

The second bit line trench 140 is at least partially located in the doped region 120, and the relationship between the bottom of the second bit line trench 140 and the doped region 120 is not limited in this application.

Also, in the vertical direction, the second bit line trench 140 may be partially located in the doped region 120 and partially located in the undoped region of the substrate 100. That is, the top of the second bit line trench 140 is located in the doped region 120, and the bottom of the second bit line trench 140 may be located in the substrate 100 of the undoped region.

In step S600, referring to fig. 9 and 10, the bit line 300 may be formed by depositing a bit line metal. After depositing the bit line metal in the first bit line trench 130 and the second bit line trench 140, the bit line 300 is fabricated by etching back.

In this embodiment, the removal of the doped region 120 is reduced by etching the doped region 120 to form the first bit line trench 130 and then etching the second bit line trench 140 in the substrate 100 to connect the first bit line trench 130. After the bit lines 300 are formed in the first bit line trenches 130 and the second bit line trenches 140, the remaining doped regions 120 are formed between the bottoms of the semiconductor pillars 110 and the bit lines 300, so that the contact resistance between the bottoms of the semiconductor pillars 110 and the bit lines 300 can be effectively reduced.

Meanwhile, since the bit lines are formed in both the first and second bit line grooves 130 and 140, a contact area of the bit line 300 and the bottom of the semiconductor pillar 110 is increased, and contact resistance can be further reduced.

In one embodiment, referring to fig. 6, step S300 includes: the doped region 120 at the bottom of the trench is etched in the vertical direction to form a first bit line trench 130.

The first bit line groove 130 may be formed using an anisotropic etching method. Specifically, anisotropic dry etching may be used, and anisotropic wet etching may also be used. The anisotropic etch may prevent the first bit line trenches 130 from expanding laterally, thereby better preventing the doped regions 120 from being removed entirely.

In one embodiment, the doped region 120 is formed by ion implantation in step 200; the doped region 120 includes a first doped region 120a and a second doped region 120b vertically arranged, the second doped region 120b is located at two sides of the first doped region 120a, and the doping concentration of the first doped region 120a is greater than the doping concentration of the second doped region 120b. In step 300, the bottom of the first bit line trench 130 is located in the first doped region 120a.

At the time of ion implantation, a target implantation depth may be set. Ideally, the ion concentration of the doped region 120 is greatest at the target implant depth, with the doping concentrations decreasing sequentially on both sides of the target implant depth. Of course, in actual implantation, there is some process error in the depth where the doping concentration is maximum.

At this time, referring to fig. 5 and 6, as an example, the doped region 120 may be provided to include a first doped region 120a and a second doped region 120b vertically arranged. The first doped region 120a may be set within a range having a first preset distance from the target implantation depth. The second doped region 120b is located at two sides of the first doped region 120a, and the doping concentration of the first doped region 120a is greater than that of the second doped region 120b. The dimensions of the first preset distance, the first doped region 120a, and the second doped region 120b are not specifically limited in this application.

Meanwhile, referring to fig. 6, in the forming of the first bit line trench 130 in step S300, the bottom of the first bit line trench 130 may be located in the first doped region 120. For example, the bottom of the first bit line trench 130 may be etched to the target implantation depth. At this time, the subsequently formed bit line 300 has a larger contact area with the region of the doped region 120 having a larger ion concentration, thereby further reducing the contact resistance between the semiconductor pillar 110 and the bit line 300.

In one embodiment, in step 400, the top of the second bit line trench 140 is located within the first doped region.

The second bit line trench 140 is formed by etching the substrate 100 under the first bit line trench 130. Thus, in the case that the bottom of the first bit line groove 130 is located in the first doped region 120a, the top of the second bit line groove 140 connected to the bottom of the first bit line groove 130 is also located in the first doped region 120a.

Meanwhile, the top of the second bit line trench 140 under the semiconductor pillar 110 may also be located in the first doped region 120a. At this time, the subsequently formed bit line 300 has a larger contact area with the region with larger ion concentration of the doped region 120, which is beneficial to further reducing the contact resistance between the semiconductor pillar 110 and the bit line 300.

In one embodiment, referring to fig. 7, before step S500, the method further includes:

step S400: a passivation layer 131 is formed on the sidewall of the first bit line trench 130.

The passivation protection layer 131 may serve to protect sidewalls of the first bit line groove 130. The passivation layer 131 may prevent the sidewalls of the first bit line groove 130 from being etched when the second bit line groove 140 is etched, preventing more of the doped region 120 from being removed.

In one embodiment, referring to fig. 6 and 7, in step S400, the method includes:

in step S410, a passivation gas is introduced to form a passivation material layer 132 on the sidewall and bottom of the first bit line trench 130.

In step S420, the passivation layer 132 at the bottom of the first bit line trench 130 is etched away to form the passivation layer 131.

The passivation gas may be a gas comprising fluorocarbon gas, hydrofluorocarbon gas, hydrochlorocarbon gas, hydrochlorofluorocarbon gas, hydrocarbon gas, or combinations thereof, which is not limited in this application. The passivation material layer 132 may be a passivation gas to form a dense carbon polymer film layer.

Specifically, the passivation gas may be carbon tetrafluoride, as an example. Under the action of a strong electric field, the carbon tetrafluoride is dissociated to form carbon ions, and the carbon ions are polymerized to form a dense carbon polymer film, which is attached to the side wall and the bottom of the first bit line groove 130.

Etching to remove the passivation material layer 132 at the bottom of the first bit line trench 130 may be a method using physical bombardment to remove the passivation material layer 132 at the bottom. Specifically, inert gas can be used to impact the passivation material layer 132 at a high speed under the action of an external electric field, so that atoms or molecules on the surface of the passivation material layer 132 are separated, and the purpose of removing the passivation material layer 132 at the bottom of the first bit line groove 130 is achieved. Specifically, for example, under high voltage conditions, argon ions may be used to vertically bombard the passivation material layer 132 at the bottom of the first bit line trench 500. The passivation material layer 132 at the bottom of the first bit line groove 500 is removed, and the passivation material layer 132 at the sidewall of the first bit line groove 130 remains, so that the second bit line groove 140 is etched later.

Of course, in other embodiments, the passivation protection layer 131 may be formed in other ways. Specifically, an oxide layer is formed on the sidewalls and bottom of the first bit line trench 130, for example, by a thermal oxidation method. And then etching to remove the oxide layer at the bottom of the first bit line groove 130, and forming a passivation protection layer 131 by the oxide layer remained on the side wall of the first bit line groove 130.

In one embodiment, in step S500, it includes: in the same ion etching chamber, after the passivation material layer 132 at the bottom of the first bit line trench 130 is etched and removed, the substrate 100 under the first bit line trench 130 is etched to form a second bit line trench 140 extending along the second direction.

In this embodiment, the substrate may be placed in the ion etching chamber, the first bit line groove 130 is etched first, then the passivation material layer 132 at the bottom of the first bit line groove 130 is etched and removed to form the passivation protection layer 131, and then the second bit line groove 140 is etched, so that the process efficiency can be effectively improved.

Of course, etching may also be performed in a different process chamber. Specifically, for example, a substrate is placed in a first ion etching chamber, and a first bit line groove 130 is formed by etching; and placing the substrate into a second ion etching cavity, and etching to form a second bit line groove 140.

In one embodiment, referring to fig. 9 and 10, in step S600, the method includes:

in step S610, metal silicide 310 is formed on the surface of the first bit line trench 130 and the surface of the second bit line trench 140.

In step S620, a bit line conductive layer 320 is formed on the surface of the metal silicide 310.

The metal silicide 310 may reduce contact resistance of the bit line 300 and the bottom of the semiconductor pillar 110. Specifically, as examples, the metal silicide 310 may be titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, palladium silicide, platinum silicide, cobalt silicide, or a metal silicide of several combinations.

Bit line conductive layer 320 may be a conductive layer formed of bit line metal deposited on the surface of metal silicide 310. Specifically, the bit line metal may be tungsten/titanium amide, or may be one or more of ruthenium, iridium, platinum, rhodium, and molybdenum, as examples. The specific material combinations, concentrations, and deposition processes of the metal silicide 310 and the bit line conductive layer 320 are not particularly limited in this application.

After the bit line conductive layer 320 is formed, a back etch may be performed to obtain a relatively flat top surface of the substrate 100 for subsequent processing. The method of etching back is not particularly limited in this application.

In this embodiment, by forming the metal silicide 310 and the bit line conductive layer 320 on the surface of the first bit line trench 130 and the surface of the second bit line trench 140, the contact between the bit line 300 and the doped region 120 is improved, and thus the contact resistance between the bottom of the semiconductor pillar 110 and the bit line 300 is reduced, and finally the performance of VAGG is improved.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.

Please continue to refer to fig. 2-10. The invention also provides a semiconductor structure comprising: a substrate, doped region 120, bit line 300.

Referring to fig. 2 to 4, the base includes a substrate 100 and an insulating dielectric layer 200, a plurality of trenches extending along a first direction are formed in the substrate 100, semiconductor pillars 110 are formed on the substrate 100 at two sides of the trenches, and the insulating dielectric layer 200 is located on the sidewalls and top of the semiconductor pillars 110.

The material of the insulating dielectric layer 200 may include, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, and the like.

Referring to fig. 5 to 8, the doped region 120 is located in the substrate 100 at the bottom of the semiconductor pillar 110 and at the bottom of the trench, and the doped region 120 has a plurality of first bit line trenches 130 spaced apart from each other.

The substrate 100 under the first bit line groove 130 has a second bit line groove 140 extending along a second direction, an included angle is formed between the second direction and the first direction, and the second bit line groove is communicated with the plurality of first bit line grooves.

Also, in the vertical direction, the second bit line trench 140 may be partially located in the doped region 120 and partially located in the undoped region of the substrate 100. That is, the top of the second bit line trench 140 is located in the doped region 120, and the bottom of the second bit line trench 140 may be located in the substrate 100 of the undoped region. The positional relationship between the bottom of the second bit line groove 140 and the doped region 121 is not particularly limited.

Referring to fig. 10, the bit line 300 is located in the first bit line trench 130 and the second bit line trench 140.

In this embodiment, the second bit line grooves are formed in the semiconductor structure substrate 100, and a plurality of first bit line grooves 130 are also formed, and the same second bit line groove 140 communicates with the plurality of first bit line grooves 130. The doped region 120 is disposed between the first bit line trenches 130, so that the contact resistance between the bottom of the semiconductor pillars 110 and the bit lines 300 can be effectively reduced.

In some embodiments, the first bit line trench 130 is located at the bottom of the trench between the semiconductor pillars 110.

The first bit line groove 130 may be formed at the bottom of the trench between the semiconductor pillars 110 by vertical etching.

In some embodiments, doped region 120 is an ion implanted region; the doped region 120 includes a first doped region 120a and a second doped region 120b vertically arranged, the second doped region 120b is located at two sides of the first doped region 120a, the doping concentration of the first doped region 120a is greater than that of the second doped region 120b, and the bottom of the first bit line trench 130 is located in the first doped region 120a.

In the case of forming the doped region 120 by ion implantation, the ion concentration may reach a peak at the center of the first doped region 120a. The ion concentration gradually decreases from the first doped region 120a to the second doped region 120b. Specifically, the ion concentration of the first doped region 120a may be 3e+20cm- ³ To 8e+17cm- ³ The ion concentration of the second doped region 120b may be-1.8e+18cm- ³ To-5e+15cm- ³ . The above ion concentrations are merely examples, and specific values of ion concentrations are not limited in practical embodiments.

In some embodiments, a top of the second bit line trench is located within the first doped region.

In some embodiments, referring to fig. 7, the semiconductor structure further comprises: passivation layer 131. The passivation layer 131 is located on a sidewall of the first bit line groove 130.

In some embodiments, the passivation protection layer 131 includes a polymer layer.

The polymer layer may be a structure formed by polymerization of a passivation gas. For example, in the case of using carbon tetrafluoride as a passivation gas, the carbon tetrafluoride is dissociated and carbon ions are polymerized to form carbon chains by the application of a strong electric field, and in this case, the polymer layer is a carbon polymer layer formed of carbon chains. The above-described polymer layers are merely examples. In some cases, the passivation gas may also be a mixed gas such that the polymer layer is a mixed layer. In practical embodiments, the composition, thickness, and the like of the polymer layer are not limited.

In some embodiments, referring to fig. 9 and 10, the bit line 300 includes: metal silicide 310, bit line conductive layer 320. The metal silicide 310 is located on the surface of the first bit line trench 130 and the surface of the second bit line trench 140. The bit line conductive layer 320 is located on the surface of the metal silicide 310.

In this embodiment, by disposing the bottom of the first bit line trench 130 in the first doped region 120a, the contact area between the bit line and the first doped region 120 with a larger concentration is increased, the contact resistance between the bottom of the semiconductor pillar 110 and the bit line 300 is reduced, and thus the use performance of VAGG is increased.

In some embodiments, there may be a plurality of bit lines 300 on the substrate, and the plurality of bit lines 300 may extend in the second direction. When the bottom of the semiconductor pillar 110 is a drain, the drain may be connected to the bit line 300.

In some embodiments, the semiconductor structure may be applied to a dynamic random access memory transistor. Because the bit line 300 formed by the first bit line groove 130 and the second bit line groove 140 can reduce the contact resistance between the bottom of the semiconductor pillar 110 and the bit line 300, the input and output of current are facilitated, and the reading and writing speeds of the dynamic random access memory transistor are increased.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features of the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A semiconductor structure, comprising:

the substrate comprises a substrate and an insulating medium layer, wherein a plurality of grooves extending along a first direction are formed in the substrate, semiconductor columns are formed on the substrate at two sides of the grooves, and the insulating medium layer is positioned on the side walls and the top of the semiconductor columns;

the doped region is positioned in the substrate at the bottom of the semiconductor column, a plurality of first bit line grooves which are mutually spaced are formed in the doped region, a second bit line groove which extends along a second direction is formed in the substrate below the first bit line groove, an included angle is formed between the second direction and the first direction, and the second bit line groove is communicated with the plurality of first bit line grooves;

2. The semiconductor structure of claim 1, wherein the first bit line trench is located at a bottom of the trench between the semiconductor pillars.

3. The semiconductor structure of claim 1, wherein the doped region is an ion implantation region; the doped region comprises a first doped region and a second doped region which are vertically arranged, the second doped region is positioned at two sides of the first doped region, and the doping concentration of the first doped region is greater than that of the second doped region;

the bottom of the first bit line groove is positioned in the first doped region.

4. The semiconductor structure of claim 3, wherein a top of the second bit line trench is located within the first doped region.

5. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:

6. The semiconductor structure of claim 5, wherein the passivation protection layer comprises a polymer layer.

7. The semiconductor structure of claim 1, wherein the bit line comprises:

metal silicide on the first and second bit line groove surfaces;

8. A method of fabricating a semiconductor structure, comprising the steps of:

providing a base, wherein the base comprises a substrate and an insulating medium layer, a plurality of grooves extending along a first direction are formed in the substrate, semiconductor columns are formed on the substrate at two sides of the grooves, and the insulating medium layer is positioned on the side walls and the top of the semiconductor columns;

9. The method of claim 8, wherein etching the doped region at the bottom of the trench forms a plurality of first bit line trenches spaced apart from each other in the doped region, comprising:

10. The method for manufacturing a semiconductor structure according to claim 8 or 9, wherein the doped region is formed by ion implantation; the doped region comprises a first doped region and a second doped region which are vertically arranged, the second doped region is positioned at two sides of the first doped region, and the doping concentration of the first doped region is greater than that of the second doped region; the bottom of the first bit line groove is positioned in the first doped region.

11. The method of claim 10, wherein a top portion of the second bit line trench is located within the first doped region.

12. The method of claim 8, wherein the etching the substrate under the first bit line trench, before forming a second bit line trench extending in a second direction, further comprises:

13. The method of manufacturing a semiconductor structure according to claim 12, wherein forming a passivation layer on a sidewall of the first trench comprises:

14. The method of claim 13, wherein etching the substrate under the first bit line trench after etching the passivation layer at the bottom of the first bit line trench in the same ion etching chamber forms a second bit line trench extending along a second direction.

15. The method of manufacturing a semiconductor structure according to claim 8, wherein forming a bit line in the first bit line trench and the second bit line trench comprises:

and forming a bit line conducting layer on the surface of the metal silicide.