CN117691972A - Method and device for calibrating clock phase and chip - Google Patents

Abstract

The application relates to the technical field of near field communication, and discloses a method for calibrating clock phase, which comprises the following steps: performing frequency division processing on the initial clock signals to generate a first number of first clock signals; determining a first target clock signal from the first clock signal according to the carrier amplitude of the first clock signal; generating a second number of second clock signals based on the first target clock signal; a clock calibration signal is determined from the second clock signal based on the carrier amplitude of the second clock signal. The technical effect of this method is described in this application. In the method, the selected first target clock signal is processed into the plurality of second clock signals, and then the clock calibration signal is selected from the plurality of second clock signals, so that the accuracy of clock phase calibration is improved. The accuracy of clock signals provided for the receiver by the NFC chip during card detection is improved, and the accuracy of card detection is guaranteed. The application also discloses a device and a chip for calibrating the clock phase.

Description

Method and device for calibrating clock phase and chip

Technical Field

The present application relates to the field of near field communication technology, for example, to a method and apparatus for calibrating clock phase, and a chip.

Background

Currently, near field communication technology (Near Field Communication, NFC) is applied to intelligent electronic devices (smart watches, mobile phones, etc.). The MCU (Micro Control Unit, microcontroller) of the NFC chip realizes communication through an ADC (Analog-to-Digital Converter) circuit check card, so that the power consumption can be reduced, but the MCU is required to continuously do the action of the check card, and the workload of the MCU is increased.

In the related art, in order to solve the problem, an LPCD (wake-on-time) function is set in the chip, and the card detection action is automatically completed through the card reading chip, so that the workload of the MCU is reduced.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

in the related art, when the NFC chip works in the LPCD mode, it is necessary to determine whether there is a card approach by detecting the variation of the carrier amplitude of the card machine antenna. However, if the clock provided inside the NFC chip has a phase deviation, a change in carrier amplitude may be caused, resulting in lower accuracy of card detection.

It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a method, a device and a chip for calibrating clock phase, which can improve the accuracy of clock phase signals provided by NFC (near field communication) inside, and further can improve the accuracy of card detection.

In some embodiments, a method for calibrating clock phase includes: performing frequency division processing on the initial clock signals to generate a first number of first clock signals; determining a first target clock signal from the first clock signal according to the carrier amplitude of the first clock signal; generating a second number of second clock signals based on the first target clock signal; a clock calibration signal is determined from the second clock signal based on the carrier amplitude of the second clock signal.

Optionally, the initial clock signal is obtained as follows: processing the on-chip clock signal into a plurality of third clock signals; the frequencies of the plurality of third clock signals are the same, and the phase difference between two adjacent signals in the plurality of third clock signals is set to be a set angle; the plurality of third clock signals are used as initial clock signals.

Optionally, the frequency dividing process is performed on the initial clock signal to generate a first number of first clock signals, including: the plurality of third clock signals are divided into a first number of first clock signals in an order of 0 degrees to 360 degrees in phase.

Optionally, determining the first target clock signal from the first clock signal according to the carrier amplitude of the first clock signal includes: determining a carrier amplitude value of each first clock signal; and taking the first clock signal with the maximum carrier amplitude value as a first target clock signal.

Optionally, generating a second number of second clock signals based on the first target clock signal includes: determining a second target clock signal that is phase-preceded and adjacent to the first target clock signal; the time interval between the second target clock signal and the first target clock signal is divided by a second number to determine a second number of second clock signals.

Optionally, determining the clock calibration signal from the second clock signal according to the carrier amplitude of the second clock signal comprises: determining a carrier amplitude value of each second clock signal; and taking the second clock signal with the maximum carrier amplitude value as a clock calibration signal.

Optionally, after determining the clock calibration signal from the second clock signal according to the carrier amplitude of the second clock signal, the method further comprises: a clock calibration signal is sent to the receiver.

In some embodiments, an apparatus for calibrating clock phase comprises: a frequency dividing circuit configured to perform frequency dividing processing on the initial clock signal to generate a first number of first clock signals; a calibration circuit, coupled to the frequency divider circuit, configured to determine a first target clock signal from the first clock signal based on a carrier amplitude of the first clock signal; a delay circuit, coupled to the calibration circuit, configured to generate a second number of second clock signals based on the first target clock signal; the calibration circuit is further configured to determine a clock calibration signal from the second clock signal based on the carrier amplitude of the second clock signal.

In some embodiments, an apparatus for calibrating clock phase includes a processor and a memory storing program instructions configured to perform a method for calibrating clock phase as described above when the program instructions are executed.

In some embodiments, a chip includes: a chip body; the device for calibrating the clock phase is mounted on the chip body.

The method, the device and the chip for calibrating the clock phase provided by the embodiment of the disclosure can realize the following technical effects:

in the embodiment of the disclosure, after the phase-locked loop circuit of the NFC chip generates an initial clock signal, first, the initial clock signal is subjected to frequency division processing to obtain a plurality of first clock signals, and a first target clock signal with an accurate clock phase is selected from the plurality of first clock signals according to carrier amplitude. Then, the second target clock signals of the clock phase are selected from the plurality of second clock signals according to the carrier amplitude by the plurality of second clock signals generated for the first target clock signal. The clock phase calibration accuracy can be improved by processing the selected first target clock signal into a plurality of second clock signals and then selecting a clock calibration signal from the plurality of second clock signals. Therefore, the embodiment of the disclosure can improve the accuracy of the clock signal provided to the receiver inside the NFC chip, and further can improve the accuracy of card detection.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a chip provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a method for calibrating clock phase provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another method for calibrating clock phase provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another method for calibrating clock phase provided by embodiments of the present disclosure;

FIG. 5 is a schematic diagram of another method for calibrating clock phase provided by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of an apparatus for calibrating clock phase provided by an embodiment of the present disclosure;

fig. 7 is a schematic diagram of another apparatus for calibrating clock phase provided by an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.

The chip provided by the embodiments of the present disclosure is shown in fig. 1, and the chip 100 includes a chip body 110 and an apparatus 600 (700) for calibrating a clock phase.

In particular, the chip 100 is applied to an NFC chip on an intelligent electronic device.

Optionally, the means 700 for calibrating the clock phase comprises a processor. The processor may divide the initial clock signal to generate a first number of first clock signals, and determine a first target clock signal from the first clock signals based on a carrier amplitude of the first clock signals. A second number of second clock signals may be generated based on the first target clock signal; a clock calibration signal is determined from the second clock signal based on the carrier amplitude of the second clock signal.

In connection with the chip described in fig. 1, an embodiment of the present disclosure provides a method for calibrating clock phase, as shown in fig. 2, the method including:

s201, the processor performs frequency division processing on the initial clock signals to generate a first number of first clock signals.

Specifically, the initial clock signal is a clock signal which is generated by preprocessing an on-chip clock signal by a phase-locked loop circuit in the NFC chip and has the same frequency and a certain phase difference.

Optionally, the initial clock signal is obtained as follows: processing the on-chip clock signal into a plurality of third clock signals; the frequencies of the plurality of third clock signals are the same, and the phase difference between two adjacent signals in the plurality of third clock signals is set to be a set angle; the plurality of third clock signals are used as initial clock signals.

Specifically, the initial clock signal includes a plurality of third clock signals having the same frequency and being out of phase by a set angle. For example, the on-chip clock signal is processed into 4 third clock signals having the same frequency and 90 degrees out of phase as the initial clock signal.

Optionally, the frequency dividing process is performed on the initial clock signal to generate a first number of first clock signals, including: the plurality of third clock signals are divided into a first number of first clock signals in an order of 0 degrees to 360 degrees in phase.

Specifically, the first number is set according to the frequency and clock phase alignment accuracy of the on-chip clock signal. For example, the frequency of the on-chip clock signal is 13.56MHz, the accuracy of the clock phase calibration is required to be 5 degrees, and the first number may be set to 36. I.e. the initial clock signal needs to be processed into 36 first clock signals.

Specifically, it is necessary to ensure that the phase relationship of the first number of first clock signals is sequentially arranged in order from 0 degrees to 360 degrees.

S202, the processor determines a first target clock signal from the first clock signal according to the carrier amplitude of the first clock signal.

Specifically, the carrier amplitude of the clock signal may vary due to the phase deviation of the clock signal. Therefore, the first target clock signal with relatively accurate phase in the plurality of first clock signals can be determined according to the carrier amplitude of the first clock signals.

S203, the processor generates a second number of second clock signals based on the first target clock signal.

Specifically, after the first target clock signal is asserted, a second number of second clock signals needs to be generated based on the first target clock signal in order to further improve the accuracy of the phase calibration of the clock signals. Specifically, the second number of second clock signals may be obtained by dividing the time or phase between the first target clock signal and the clock signal whose phase is preceding it.

Specifically, the second number is set according to the accuracy of the required clock phase calibration. For example, the accuracy of the obtained first target clock signal is 5 degrees, the accuracy required to obtain the final clock phase calibration is 0.25 degrees, and the second number may be set to 20. For another example, the accuracy of the obtained first target clock signal is 10 degrees, and the accuracy of the final clock phase calibration is required to be 1 degree, the second number may be set to 10.

S204, the processor determines a clock calibration signal from the second clock signal according to the carrier amplitude of the second clock signal.

Specifically, the carrier amplitude of the clock signal may vary due to the phase deviation of the clock signal. Therefore, the clock signal with the most accurate phase in the plurality of second clock signals can be determined as the clock calibration signal according to the carrier amplitude of the second clock signals.

In the embodiment of the disclosure, after the phase-locked loop circuit of the NFC chip generates an initial clock signal, first, the initial clock signal is subjected to frequency division processing to obtain a plurality of first clock signals, and a first target clock signal with an accurate clock phase is selected from the plurality of first clock signals according to carrier amplitude. Then, the second target clock signals of the clock phase are selected from the plurality of second clock signals according to the carrier amplitude by the plurality of second clock signals generated for the first target clock signal. The clock phase calibration accuracy can be improved by processing the selected first target clock signal into a plurality of second clock signals and then selecting a clock calibration signal from the plurality of second clock signals. Therefore, the embodiment of the disclosure can improve the accuracy of the clock signal provided to the receiver inside the NFC chip, and further can improve the accuracy of card detection.

Another method for calibrating clock phase is provided in an embodiment of the present disclosure, as shown in fig. 3, the method comprising:

s301, the processor performs frequency division processing on the initial clock signals to generate a first number of first clock signals.

S302, the processor determines a carrier amplitude value of each first clock signal.

Specifically, since the deviation condition of the clock signal can be determined according to the carrier amplitude value of the clock signal, the carrier amplitude value of each first clock signal needs to be determined, so that the clock signal with more accurate clock phase can be determined from the first clock signals according to the carrier amplitude value.

S303, the processor takes the first clock signal with the largest carrier amplitude value as a first target clock signal.

Specifically, the larger the carrier amplitude of the clock signal, the smoother the waveform resulting from taking this clock signal as input. Therefore, the larger the carrier amplitude of the clock signal, the closer the phase of the clock signal to the standard clock phase. Therefore, the first clock signal having the largest carrier amplitude value can be used as the first target clock signal.

S304, the processor generates a second number of second clock signals based on the first target clock signal.

S305, the processor determines a clock calibration signal from the second clock signal according to the carrier amplitude of the second clock signal.

In the embodiment of the disclosure, the clock signal with the largest carrier amplitude value in the first clock signal is used as the first target clock signal, and the larger the carrier amplitude of the clock signal is, the closer the phase of the clock signal is to the standard clock phase. Therefore, the first clock signal with the largest carrier amplitude value is selected as the first target clock signal, so that the accuracy of the clock calibration signal determined based on the first target clock signal in the subsequent step can be improved.

Another method for calibrating clock phase is provided in an embodiment of the present disclosure, as shown in fig. 4, the method comprising:

s401, the processor performs frequency division processing on the initial clock signal to generate a first number of first clock signals.

S402, the processor determines a first target clock signal from the first clock signals according to the carrier amplitude of the first clock signals.

S403, the processor determines a second target clock signal that is phase-preceded and adjacent to the first target clock signal.

Specifically, the second target clock signal is a clock signal which is adjacent to the first target clock signal and whose phase is before the first target clock signal, among the plurality of first clock signals.

S404, the processor divides the time interval between the second target clock signal and the first target clock signal according to a second number, and determines a second number of second clock signals.

Specifically, since the clock phase of the first target clock signal is less different from the standard clock phase, by dividing or separating the time interval between the clock signals adjacent to the first target clock signal phase, a clock signal having a smaller clock phase from the standard clock phase can be selected therefrom. Therefore, the time interval between the second target clock signal and the first target clock signal needs to be divided by the second number to determine the second number of second clock signals.

S405, the processor determines a clock calibration signal from the second clock signal according to the carrier amplitude of the second clock signal.

In an embodiment of the disclosure, a time interval between the second target clock signal and the first target clock signal is divided according to a second number, and the second number of second clock signals is determined. Then, a clock calibration signal is selected from the second clock signal based on the carrier amplitude. The clock phase of the clock calibration signal is less deviated from the standard clock phase than the first target clock signal. Therefore, the embodiments of the present disclosure can improve the accuracy of clock phase calibration.

In some embodiments, the first clock signal of the plurality of first clock signals may be further used as the second target clock signal, wherein the first clock signal is phase-shifted after and adjacent to the first target clock signal.

Another method for calibrating clock phase is provided in an embodiment of the present disclosure, as shown in fig. 5, the method comprising:

s501, the processor performs a frequency division process on the initial clock signal to generate a first number of first clock signals.

S502, the processor determines a first target clock signal from the first clock signals according to the carrier amplitude of the first clock signals.

S503, the processor generates a second number of second clock signals based on the first target clock signal.

S504, the processor determines a carrier amplitude value of each second clock signal.

Specifically, since the deviation condition of the clock signal can be determined according to the carrier amplitude value of the clock signal, the carrier amplitude value of each second clock signal needs to be determined, so that the clock signal with more accurate clock phase is determined from the second clock signals according to the carrier amplitude value.

S505, the processor takes the second clock signal with the largest carrier amplitude value as a clock calibration signal.

Specifically, the larger the carrier amplitude of the clock signal, the smoother the waveform resulting from taking this clock signal as input. Therefore, the larger the carrier amplitude of the clock signal, the closer the phase of the clock signal to the standard clock phase. Therefore, the second clock signal having the largest carrier amplitude value can be used as the clock calibration signal.

In the embodiment of the disclosure, the clock signal with the largest carrier amplitude value in the second clock signal is used as the clock calibration signal, and the larger the carrier amplitude of the clock signal is, the closer the phase of the clock signal is to the standard clock phase. Therefore, the deviation of the clock phase of the clock calibration signal from the standard clock phase can be ensured to be smaller than the deviation of the clock phase of the first target clock signal from the standard clock phase. In this way, the accuracy of the clock phase calibration is improved.

In some embodiments, after determining the clock calibration signal from the second clock signal based on the carrier amplitude of the second clock signal, further comprising: a clock calibration signal is sent to the receiver.

Specifically, the receiver is a module inside a chip for comparing its own clock signal with the clock signal of the card detector.

Specifically, after determining the clock calibration signal, the clock calibration signal is sent to the receiver of the chip, so that the receiver compares the clock signal of the receiver with the clock signal of the card detector. Because the clock phase of the clock calibration signal provided by the embodiment of the disclosure has smaller phase difference with the standard clock phase, the carrier amplitude cannot be changed, the accuracy of card detection of the card detection machine is ensured, and the risk of false wake-up of the chip is reduced.

Referring to fig. 6, an apparatus 600 for calibrating clock phase according to an embodiment of the present disclosure includes a frequency dividing circuit 610, a calibration circuit 620, and a delay circuit 630. The frequency dividing circuit 610 is configured to perform a frequency dividing process on the initial clock signal to generate a first number of first clock signals. The calibration circuit 620 is coupled to the frequency divider circuit 610 and is configured to determine a first target clock signal from the first clock signal based on the carrier amplitude of the first clock signal. The delay circuit 630 is coupled to the calibration circuit 620 and is configured to generate a second number of second clock signals based on the first target clock signal. The calibration circuit 620 is further configured to determine a clock calibration signal from the second clock signal based on the carrier amplitude of the second clock signal.

In some embodiments, delay circuit 630 includes: a buffer 631 and a switching member 632; the input and output of the plurality of buffers are connected in sequence, the input of the first buffer of the plurality of buffers is connected to the output of the calibration circuit 620, and the output of the plurality of buffers is connected to the input of the calibration circuit 620 through the switching element 632.

Specifically, after determining the clock calibration signal, a target buffer corresponding to the clock calibration signal may be determined. The switching element 632 connected to the output of the target buffer is then closed to send a clock calibration signal to the calibration circuit 620 so that the calibration circuit 620 can send the clock calibration signal to the receiver of the chip 600.

In some embodiments, the means for calibrating the clock phase further comprises a phase locked loop circuit 640 for generating a clock phase signal.

As shown in connection with fig. 7, an embodiment of the present disclosure provides an apparatus 700 for calibrating a clock phase, the apparatus 700 for calibrating a clock phase including: a processor (processor) 701 and a memory (memory) 702. Optionally, the apparatus may further comprise a communication interface (Communication Interface) 703 and a bus 704. The processor 701, the communication interface 703 and the memory 702 may communicate with each other via the bus 704. The communication interface 703 may be used for information transfer. The processor 701 may invoke logic instructions in the memory 702 to perform the above embodiments for calibrating clock phase.

Further, the logic instructions in the memory 702 described above may be implemented in the form of software functional units and stored in a computer readable storage medium when sold or used as a stand alone product.

The memory 702 is used as a computer readable storage medium for storing a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 701 executes the functional applications and data processing by running the program instructions/modules stored in the memory 702, i.e. implements the method for calibrating clock phases in the above-described embodiments.

Memory 702 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functionality; the storage data area may store data created according to the use of the terminal device, etc. In addition, memory 702 may include high-speed random access memory, and may also include non-volatile memory.

As shown in connection with fig. 1, an embodiment of the present disclosure provides a chip 10 comprising: the chip body 100, and the above-described apparatus 600 (700) for calibrating clock phases. The apparatus 600 (700) for calibrating clock phase is mounted to the chip body 100. The mounting relationships described herein are not limited to placement within the chip 10, but include mounting connections to other components of the chip 10, including but not limited to physical, electrical, or signal transmission connections, etc. Those skilled in the art will appreciate that the apparatus 600 (700) for calibrating clock phase may be adapted to a viable chip body 100 to implement other viable embodiments.

Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for calibrating clock phase.

Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. While the aforementioned storage medium may be a non-transitory storage medium, such as: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, or the like, which can store program codes.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims (10)

1. A method for calibrating clock phase, comprising:

performing frequency division processing on the initial clock signals to generate a first number of first clock signals;

determining a first target clock signal from the first clock signal according to the carrier amplitude of the first clock signal;

generating a second number of second clock signals based on the first target clock signal;

a clock calibration signal is determined from the second clock signal based on the carrier amplitude of the second clock signal.

2. The method according to claim 1, characterized in that the initial clock signal is obtained in the following way:

processing the on-chip clock signal into a plurality of third clock signals; the frequencies of the plurality of third clock signals are the same, and the phase difference between two adjacent signals in the plurality of third clock signals is set to be a set angle;

the plurality of third clock signals are used as initial clock signals.

3. The method of claim 2, wherein dividing the initial clock signal to generate a first number of first clock signals comprises:

the plurality of third clock signals are divided into a first number of first clock signals in an order of 0 degrees to 360 degrees in phase.

4. The method of claim 1, wherein determining the first target clock signal from the first clock signal based on the carrier amplitude of the first clock signal comprises:

determining a carrier amplitude value of each first clock signal;

and taking the first clock signal with the maximum carrier amplitude value as a first target clock signal.

5. The method of claim 1, wherein generating a second number of second clock signals based on the first target clock signal comprises:

determining a second target clock signal that is phase-preceded and adjacent to the first target clock signal;

the time interval between the second target clock signal and the first target clock signal is divided by a second number to determine a second number of second clock signals.

6. The method of claim 1, wherein determining a clock calibration signal from the second clock signal based on the carrier amplitude of the second clock signal comprises:

determining a carrier amplitude value of each second clock signal;

and taking the second clock signal with the maximum carrier amplitude value as a clock calibration signal.

7. The method of any of claims 1 to 6, further comprising, after determining the clock calibration signal from the second clock signal based on the carrier amplitude of the second clock signal:

a clock calibration signal is sent to the receiver.

8. An apparatus for calibrating clock phase, comprising:

a frequency dividing circuit configured to perform frequency dividing processing on the initial clock signal to generate a first number of first clock signals;

a calibration circuit, coupled to the frequency divider circuit, configured to determine a first target clock signal from the first clock signal based on a carrier amplitude of the first clock signal;

a delay circuit, coupled to the calibration circuit, configured to generate a second number of second clock signals based on the first target clock signal;

the calibration circuit is further configured to determine a clock calibration signal from the second clock signal based on the carrier amplitude of the second clock signal.

9. An apparatus for calibrating clock phase comprising a processor and a memory storing program instructions, wherein the processor is configured to perform the method for calibrating clock phase of any of claims 1 to 7 when the program instructions are run.

10. A chip, comprising:

a chip body;

the device for calibrating clock phase according to claim 8 or 9, mounted on a chip body.