CN117690812A - Packaging method - Google Patents
Packaging method Download PDFInfo
- Publication number
- CN117690812A CN117690812A CN202311801667.7A CN202311801667A CN117690812A CN 117690812 A CN117690812 A CN 117690812A CN 202311801667 A CN202311801667 A CN 202311801667A CN 117690812 A CN117690812 A CN 117690812A
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- China
- Prior art keywords
- cutting
- wiring layer
- encapsulating material
- exposed
- chip
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000005520 cutting process Methods 0.000 claims abstract description 88
- 239000000463 material Substances 0.000 claims abstract description 45
- 238000009713 electroplating Methods 0.000 claims abstract description 23
- 238000005553 drilling Methods 0.000 claims abstract description 13
- 238000003466 welding Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 7
- 239000008393 encapsulating agent Substances 0.000 claims description 9
- 230000000717 retained effect Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 238000005538 encapsulation Methods 0.000 description 13
- 239000005022 packaging material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The application of the invention discloses a packaging method, which comprises the following steps: electroplating: drilling the encapsulating material to expose the conductive posts, and electroplating a wiring layer at the lead-out end of the chip and the exposed conductive posts to realize electrical connection and trend; pre-cutting: the wiring layer is encapsulated by the encapsulating material, part of the encapsulating material is pre-cut and removed at the position of the cutting channel, so that the wiring layer and the conductive column in the drilling hole are partially cut and removed, and the rest side surfaces are exposed in the cutting groove; filling: filling the cutting groove with an encapsulating material, and curing to form a complete whole; cutting: the outer welding leg is exposed through grinding, the bottom surface of the conductive column is electroplated, the outer welding leg is cut into a product unit at the cutting channel, metal cutting of part of the wiring layer and the conductive column is removed through pre-cutting, inner metal is not exposed on the side surface of the packaging body on the basis of guaranteeing the minimum packaging size, the appearance and the yield of a finished product are guaranteed, and the high heat conduction capacity of the back surface of the chip is reserved for the power chip.
Description
Technical Field
The invention belongs to the technical field of package design, and particularly relates to a packaging method.
Background
Packaging is significant, and a long process from design to fabrication is required to obtain an IC chip, however, a chip is relatively small and thin, and if no protection is applied externally, it is easily scratched and damaged. In addition, because the chip is small in size, if a shell with a larger size is not used, the chip is not easy to be arranged on a circuit board, and the packaging has the functions of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and is also a bridge for communicating the world inside the chip with an external circuit.
Under normal conditions, when the trend and the extraction of a circuit are realized in the packaging body, an electric conduction layer or a rewiring layer is required to be electroplated after the packaging layer is drilled, for drilling, the industry generally adopts a laser drilling mode, the formed hole is conical with a large upper part and a small lower part, then the formed hole is cut into product units at the cutting path position of the packaging body, the electroplated layer in the hole is contained in the packaging body, and in order to ensure the stability of electric connection, a hole with a certain size is required to be drilled to realize the electric connection, so that the width dimension (shown in a figure 1) of the whole packaging body is definitely increased, and for a small-space mounting environment, the large-size packaging body is difficult to enter; to reduce the size, the dicing is chosen from the drilling location, resulting in exposure of the inner metal layer to the sides of the package (as shown in fig. 2), affecting the finished appearance and yield.
Therefore, it is desirable to provide a packaging method to solve the above-mentioned problems.
Disclosure of Invention
In order to solve the problems that in the prior art, the size is larger during normal cutting after packaging, and the inner metal is exposed from the side surface of the packaging body during size cutting, so that the appearance and yield of a finished product are affected, the invention provides a packaging method.
In order to achieve the above object, the present invention provides a packaging method, which includes the following steps:
electroplating: drilling the encapsulating material to expose the conductive posts, and electroplating a wiring layer at the lead-out end of the chip and the exposed conductive posts to realize electrical connection and trend;
pre-cutting: the wiring layer is encapsulated by the encapsulating material, part of the encapsulating material is pre-cut and removed at the position of the cutting channel, so that the wiring layer and the conductive column in the drilling hole are partially cut and removed, and the rest side surfaces are exposed in the cutting groove;
filling: filling the cutting groove with an encapsulating material, and curing to form a complete whole;
cutting: and grinding the bottom surface of the exposed conductive column, electroplating the outer welding legs, and cutting into product units in the cutting path.
Further, in the electroplating step, the electroplating device further comprises a wiring layer electroplated on the back surface of the chip, and the wiring layer is electrically connected with the conductive column.
Further, in the pre-cutting step, part of the encapsulating material remains at the bottom of the cutting groove, so that pre-cutting flying materials are prevented.
Further, in the pre-cutting step, the thickness of the encapsulating material reserved at the bottom of the cutting groove is equal to or greater than 0.030mm.
Further, in the pre-cutting step, the encapsulating material with a width larger than the cutting path is pre-cut at the cutting path position.
Further, in the pre-cutting step, the product cutting channel width is less than or equal to the pre-cutting channel width is less than or equal to the product cutting channel width plus 0.04mm.
In the pre-cutting step, one side surface of the pre-cutting channel is overlapped with the product cutting channel, and the other side surface of the pre-cutting channel is positioned at the wiring layer and the conductive column.
The application of the invention: the width of the pre-cutting channel is larger than that of the product cutting channel, metal of part of the wiring layer and the conductive column is cut and removed by pre-cutting, when the product is cut, only the packaging material filled later is cut, the side surfaces of the wiring layer and the conductive column are packaged in the packaging material filled later, the side surfaces are not exposed, the inner metal is not exposed on the side surfaces of the packaging body on the basis of guaranteeing the minimum packaging size, and the appearance and the yield of the finished product are guaranteed; for the power chip, the high heat conduction capacity of the back surface of the chip in the traditional WB process is reserved, and meanwhile, the heat conduction capacity is improved to the maximum extent through the structures of the leading-out end and the wiring layer.
Drawings
FIG. 1 is a cross-sectional view of a conventional package;
FIG. 2 is a cross-sectional view of another package of the prior art;
FIGS. 3-7 are schematic diagrams illustrating steps of electroplating a package method according to the present invention;
FIG. 8 is a schematic diagram of a pre-dicing step of a packaging method according to the present invention;
FIG. 9 is a schematic diagram of a filling step of a packaging method according to the present invention;
fig. 10-12 are schematic diagrams illustrating a dicing step of a packaging method according to the present invention.
The figure indicates: 1. a chip; secondly, conducting columns; third, wiring layer; 4. cutting a groove; 5. an outer leg; 6. and a wiring layer.
Detailed Description
The following description of the embodiments of the present invention will be made more complete and less obvious to those skilled in the art, based on the embodiments of the present invention, for a part, but not all of the embodiments of the present invention, without making any creative effort.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must be specifically oriented, constructed and operated in the specific orientations, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with the interior of two elements, the specific meaning of the terms in this invention will be understood by those of ordinary skill in the art.
For a better understanding of the objects, structures and functions of the present application, a method of packaging the present application is described in further detail below with reference to fig. 3-12.
The packaging method comprises the following steps:
electroplating: drilling the encapsulating material to expose the conductive posts 2, and electroplating the wiring layer 3 at the lead-out end of the chip 1 and the exposed conductive posts 2 to realize electrical connection and trend;
pre-cutting: the wiring layer 3 is encapsulated by the encapsulating material, part of the encapsulating material is pre-cut and removed at the position of the cutting channel, so that the wiring layer 3 and the conductive post 2 in the drill hole are partially cut and removed, and the rest side surfaces are exposed in the cutting groove 4;
filling: filling the cutting groove 4 with an encapsulating material, and curing the encapsulating material into a complete whole;
cutting: the bottom surface of the conductive post 2 is exposed by grinding, and the outer soldering leg 5 is electroplated and cut into product units in the cutting path.
Referring to fig. 3-7 and the electroplating step, the method specifically comprises the following steps:
providing a carrier plate, and attaching a plurality of chips 1 (shown in fig. 3) at corresponding positions on the carrier plate; the carrier plate is a substrate commonly used in the field, in the application, taking mounting 2 chips 1 on the substrate as an example, the back surface of the chip 1 faces the substrate for mounting, and the front surface of the chip 1 is formed into a lead-out end through ball implantation;
after the front surface of the chip 1 is encapsulated and cured, the carrier plate is removed, and the back surface of the chip 1 is exposed to the encapsulation surface (shown in fig. 4); removing the carrier plate in a mechanical stripping mode, wherein the back surface of the chip 1, namely the mounting surface, is exposed to the encapsulation surface;
electroplating a wiring layer 6 on the back surface of the exposed chip 1, electroplating a conductive post 2 on the wiring layer 6, and re-attaching the back surface of the chip 1 to the carrier plate after complete encapsulation (as shown in fig. 5); the chip 1 is provided with double-sided electrodes, the back surface of the chip 1 with the encapsulating material is upwards placed, the back surface of the exposed chip 1 is electroplated, the wiring layer 3 on the back surface of the chip 1 is directly electroplated on the back surface and the encapsulating material, the electric trend of the back surface of the chip 1 is realized, then the conductive columns 2 electrically connected with the wiring layer 6 are electroplated, the wiring layer 3 and the conductive columns 2 are completely encapsulated and solidified, the back surface of the chip 1 faces the carrier and is then attached again, and the high heat conduction capacity of the back surface of the chip 1 in the traditional WB process is reserved for the power chip 1 through back surface electroplating, and meanwhile, the electric conduction capacity is furthest improved through the structures of the lead-out terminal and the wiring layer 6;
grinding and exposing the leading-out end of the front surface of the chip 1, and drilling holes to expose the conductive posts 2 (shown in fig. 6); the upper surface of the encapsulating material is horizontally polished by a mechanical polishing mode until the lead-out end of the chip 1 is exposed, namely the ball implant of the chip 1 is exposed, sometimes, in order to completely expose the lead-out end to ensure stable electrical connection, even the ball implant or other types of lead-out ends need to be polished to a certain height, after polishing, the encapsulating material is thinned, and redundant encapsulating material above the conductive column 2 is removed on the encapsulating material by a laser drilling mode until the top of the conductive column 2 is exposed;
electroplating a wiring layer 3 on the encapsulating material, wherein the wiring layer 3 electrically connects the lead-out end of the chip 1 with the conductive column 2 in the drilled hole (as shown in fig. 7); both routing layer 6 and routing layer 3 are re-routing in the art, wherein the routing layer 3 in the borehole is electroplated against the borehole interior sidewall.
With reference to fig. 8 and the pre-cutting step, the encapsulation is continued, so that the wiring layer 3 is completely encapsulated, a wider cutting knife is used for cutting the encapsulation material, but the encapsulation material is not completely cut off, a part of the encapsulation material remains at the bottom of the cutting groove, pre-cutting flying material is prevented, and the thickness of the encapsulation material remaining at the bottom of the cutting groove is equal to or greater than 0.030mm; the width of the pre-cutting channel is larger than that of the product cutting channel, one side surface of the cutting knife coincides with the product cutting channel, the other side surface is positioned at the positions of the wiring layer 3 and the conductive column 2, the encapsulating material, the wiring layer 3 and the conductive column 2 are cut, the encapsulating material larger than the width of the cutting channel is pre-cut at the positions of the cutting channel, the width of the product cutting channel is smaller than or equal to the width of the product cutting channel, and the width of the product cutting channel is smaller than or equal to +0.04mm, in sum, referring to fig. 8, the dotted line in fig. 8 is the position of the product cutting channel, under the embodiment of the application, the pre-cutting channel is widened by 0.04mm towards the direction of the right wiring layer 3 and the conductive column 2 on the basis of the left side surface of the product cutting channel, so that partial areas of the wiring layer 3 and the conductive column 2 are cut and removed, the side surfaces of the cut wiring layer 3 and the conductive column 2 are exposed in the cutting channel 4, the specific widening thickness is adjusted according to the design of the product, and the drilling holes are formed into a part of the wiring layer 3 and the conductive column 2 with larger width by increasing the pre-cutting step, so that the packaging size is minimized is ensured.
Referring to fig. 9 and the filling step, the formed cutting groove 4 is filled with the encapsulant, so as to ensure the top surface of the encapsulant to be level, and the encapsulant is restored to the state before pre-cutting after filling, and is ready to be cured after filling, and the cured encapsulant is integrated with the previous encapsulant.
Referring to fig. 10-12, the cutting steps specifically include the following steps:
removing the carrier plate, and grinding the encapsulation surface of the back surface of the chip 1 until the conductive posts 2 are exposed (as shown in fig. 10); the encapsulating material is ground horizontally by mechanical grinding until the bottom surface of the conductive post 2 is exposed;
electroplating the electrically connected outer solder pins 5 at the exposed conductive posts 2 (as shown in fig. 11); the outer welding leg 5 is a bridge for realizing the electric connection between the inside and the outside of the chip 1 by the whole package product, and is a welding point for welding the package of the chip 1 to a working area, and the size of the outer welding leg 5 can be designed according to the actual product condition;
cutting at the product cutting path to form product units (as shown in fig. 12); because the width of the pre-cutting channel is larger than that of the product cutting channel, metal of part of the wiring layer 3 and the conductive column 2 is cut and removed by pre-cutting, when the product is cut, only the subsequently filled packaging material is cut, the side surfaces of the wiring layer 3 and the conductive column 2 are packaged in the subsequently filled packaging material, after the product is cut, the side surfaces of the packaging material are only exposed in the cutting channel, the side surfaces of the wiring layer 3 and the conductive column 2 are not exposed, the inner layer metal is not exposed on the side surfaces of the packaging body on the basis of guaranteeing the minimum packaging size, and the appearance and the yield of a finished product are guaranteed.
In all the steps using the electroplating process, electroplating protection is formed on the surface through the photoetching technology of exposure and development, then a metal seed layer is formed in a to-be-electroplated area through sputtering or copper deposition, the copper material is adopted in the metal seed layer, the metal seed layer is used for guaranteeing the binding force between the metal to be electroplated and the to-be-electroplated area, and meanwhile, the surface to which conductive ions are attached is provided for electroplating, so that the electroplating effect is guaranteed.
In this application all use the step of encapsulation technology, all be the mode cooperation mould pressing that uses the plastic envelope material to mould plastics and form the encapsulation, the plastic envelope material that this application adopted is epoxy plastic envelope material, with low costs, and curability is good, effectively prevents the impurity in the air and to the corruption of chip circuit and cause the decline of chip electrical property.
According to the invention, as the width of the pre-cutting channel is larger than that of the product cutting channel, metal of part of the wiring layer 3 and the conductive column 2 is cut and removed by pre-cutting, and only the subsequently filled encapsulating material is cut when the product is cut, the side surfaces of the wiring layer 3 and the conductive column 2 are encapsulated in the subsequently filled encapsulating material, the side surfaces of the wiring layer 3 and the conductive column 2 are not exposed, so that on the basis of ensuring the minimum encapsulation size, the side surfaces of the encapsulation body are not exposed out of inner metal, and the appearance and the yield of the finished product are ensured; for the power chip, the high heat conduction capacity of the back surface of the chip 1 in the traditional WB process is reserved, and meanwhile, the heat conduction capacity is improved to the maximum extent through the structures of the leading-out terminal and the wiring layer 6.
It will be understood that the present application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the present application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (7)
1. A method of packaging comprising the steps of:
electroplating: drilling the encapsulating material to expose the conductive posts, and electroplating a wiring layer at the lead-out ends of the chips and the exposed conductive posts to realize electrical connection and trend;
pre-cutting: the wiring layer is encapsulated by the encapsulating material, part of the encapsulating material is pre-cut and removed at the position of the cutting channel, so that the wiring layer and the conductive column in the drilling hole are partially cut and removed, and the rest side surfaces are exposed in the cutting groove;
filling: filling the cutting groove with an encapsulating material, and curing to form a complete whole;
cutting: and grinding the bottom surface of the exposed conductive column, electroplating the outer welding legs, and cutting into product units in the cutting path.
2. The method of claim 1, further comprising a trace layer electroplated on the back side of the chip, the trace layer being electrically connected to the conductive pillars.
3. The packaging method according to claim 1, wherein in the pre-cutting step, a part of the encapsulant remains at the bottom of the cutting groove to prevent pre-cutting flying material.
4. A packaging method according to claim 3, wherein in the pre-cutting step, the thickness of the encapsulant retained at the bottom of the cutting groove is ∈ 0.030mm.
5. The method of claim 4, wherein in the pre-dicing step, the encapsulant is pre-diced at dicing lane locations to remove encapsulant material greater than the width of the dicing lane.
6. The method of claim 5, wherein in the pre-dicing step, the product scribe line width is less than or equal to +0.04mm.
7. The method of claim 1, wherein in the pre-dicing step, one side of the pre-dicing street coincides with the product dicing street, and the other side is located at the wiring layer and the conductive pillar.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311801667.7A CN117690812A (en) | 2023-12-26 | 2023-12-26 | Packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311801667.7A CN117690812A (en) | 2023-12-26 | 2023-12-26 | Packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117690812A true CN117690812A (en) | 2024-03-12 |
Family
ID=90130103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311801667.7A Pending CN117690812A (en) | 2023-12-26 | 2023-12-26 | Packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117690812A (en) |
-
2023
- 2023-12-26 CN CN202311801667.7A patent/CN117690812A/en active Pending
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